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2020-09-15octeontx2: Add IPv6 fields to default MKEX profileVidhya Vidhyaraman
commit 765264401673131f94bee0c52801728d688b01b5 from git@git.assembla.com:cavium/WindRiver.linux.git Added some IPv6 protocol fields to the default MKEX profile. They include everything from the beginning of IP header and up to source address. The pattern occupies full KW2 in MCAM entry. Only one out of two LD registers for this protocol is used. Signed-off-by: Vidhya Vidhyaraman <vraman@marvell.com> Change-Id: I981847a5741b35b9218f62c1af2cd0a1319ec60d Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/35328 Reviewed-by: Yuri Tolstov <Yuri.Tolstov@cavium.com> Reviewed-by: Devapraba Muthumani <dmuthumani@marvell.com> Tested-by: Devapraba Muthumani <dmuthumani@marvell.com> (cherry picked from commit cb6f43f99a37cd0d92fff31f1efe1dc96f21710b) Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/35390 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Free RVU REE irq properlySmadar Fuks
commit 71b7c917743bd1f0c97344109dbae6e3f65c6e67 from git@git.assembla.com:cavium/WindRiver.linux.git Fix REE crash at free_irq in rvu_ree_unregister_interrupts_block during rmmod of AF driver. In order to support 2 REEs in the same interrupt handler function, request_irq is called with struct rvu_block as a cookie, instead of struct rvu. following that, free_irq should also be called with the same cookie which is struct rvu_block. In addition REE0 and REE1 have different irq names. Change-Id: I6a49d38deec74a866a045d4df3d355425546d2d9 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/35228 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Free RVU NIX IRQs properly.Rakesh Babu
commit 7835f527b1bb499c09940ae5cc38d5f27ad76283 from git@git.assembla.com:cavium/WindRiver.linux.git As 98xx has 2 NIX blocks, "nix_hw" data instance is passed as cookie to RVU NIX IRQ handlers instead of "rvu" data instance to distinguish among the 2 NIX IRQ handlers. To free these Interrupt handlers "nix_hw" instance should be useds as cookie, but it is left unchanged with "rvu" data instance. This leads to kernel panic when removing the AF driver. This patch fixes this panic. Change-Id: Iaa08e65877e6394f6e7eb923110707fef0448c2e Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34979 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Fix REE warnings for no previous prototypeSmadar Fuks
commit ea71358e67412557766479059d99608a4815b792 from git@git.assembla.com:cavium/WindRiver.linux.git These warnings were due to missing static declarations Change-Id: Ic41cc057ea97e18b7be23e24aaa0e2131a0cec89 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34938 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Send transmit link in mboxSubbaraya Sundeep
commit 860d655fab3086ebcbee4f215c8fd909e14a49df from git@git.assembla.com:cavium/WindRiver.linux.git Send transmit link number in the nix_lf_alloc_rsp mailbox response to AF consumers. Change-Id: I3a2a87998121b826ac83231724d6152f63d53212 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34811 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: add npc profile support to parse NAT-T-ESPKiran Kumar K
commit e8e13a268966beb6c23678e6883fb9b3f14eb758 from git@git.assembla.com:cavium/WindRiver.linux.git Add npc profile support to parse NAT-T-ESP. NAT ESP is UDP based protocol.So, moved ESP to LE so that both UDP and ESP can be extracted. Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Change-Id: I51958e5067382e11eed315a34f481297b363b007 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34597 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: add npc profile support to parse CPT_PARSE_HDRKiran Kumar K
commit e8e13a268966beb6c23678e6883fb9b3f14eb758 from git@git.assembla.com:cavium/WindRiver.linux.git Adding npc profile support to parse CPT_PARSE_HDR_S. cpt_parse_hdr_s will be part of LA and both ethernet header and cpt_parse_hdr_s will be extracted as part of LA. PKIND 58 has been reserved for this. Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Change-Id: I242e35bf6dee615cb2ff624127042f7857708862 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34606 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Backport upstream changes.Rakesh Babu
commit abc3a5994008c7167275c2cbcc0f6d77874d8daa from git@git.assembla.com:cavium/WindRiver.linux.git Backported changes from upstream kernel sources. Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Change-Id: I1c6c5b9802bd0c701249e12011ea67589ea9890a Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34589 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Fix REE large rule file programmingSmadar Fuks
commit e6761bca8b4c58a42893015169deeebdb29043a4 from git@git.assembla.com:cavium/WindRiver.linux.git For programming purposes compiled rules (ROF), received via Mbox, are kept in memory blocks of 4MB size. Large compiled rule files require multiple memory blocks. Fixed a case in which instructions of the same ROF (prefix or graph), that were spread over multiple blocks weren't programmed correctly. Change-Id: I2251309317841e8b87cc7c1f2ecfe3a957b82513 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34449 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Fix the BPID maskSubbaraya Sundeep
commit 72d2a3acac11ded56cf2ac212fae246a811f1871 from git@git.assembla.com:cavium/WindRiver.linux.git The backpressure ID to be programmed in NIX_AF_RX_CHAN(0..4095)_CFG has bit definition as [8:0] but the mask used to configure is 0xFF by mistake. This patch fixes that. Fixes: df6e0876b1e8 ("octeontx2-af: Add mbox messages to configure backpressure for an interface") Change-Id: I3949ca78dcae83e0a63d57292c6b370f25dabf2d Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34447 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Fix updating wrong multicast list index in NIX_RX_ACTIONNaveen Mamindlapalli
commit 0dcc41e27a336144457985e8803d7abe6dd76b05 from git@git.assembla.com:cavium/WindRiver.linux.git This patch fixes the issue of updating wrong multicast list index in NIX_RX_ACTION when VF comes up. Otherwise, the NIX hw block receiving the broadcast traffic on the PF will attempt to refer to the incorrect multicast list index entry NIX_RX_MCE_S which was initialized to direct the traffic to another PF FUNC that may not have been initialized resulting in SMMU translation faults. Fixes: 1f2c72a130a ("octeontx2-af: Add NIX1 interfaces to NPC") Change-Id: Iad13241c7a78c40ae6bffa1be3a4c127222096de Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34369 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Ratelimit prints from AF error interrupt handlersNaveen Mamindlapalli
commit 52f6042c889c8bb8a3743614ab1aab6f002ba8ba from git@git.assembla.com:cavium/WindRiver.linux.git Ratelimit prints from AF error interrupt handlers such as NIX AF error interrupt, NIX AF RVU error interrupt and NPA AF RVU error interrupt handler. This prevents unnecessary flooding of error messages on the console when any AF error interrupt condition triggers continuously. Change-Id: I216ef5c95ba7f320f9e7ed0800adc78044551a8e Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/34166 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Add support for VLAN based RSS hashingGeorge Cherian
commit 887e6f37bb4c15728c2b74e6277c1c6fe778032d from git@git.assembla.com:cavium/WindRiver.linux.git Added support for PF/VF drivers to choose RSS flow key algorithm with VLAN tag included in hashing input data. Only CTAG is considered. Change-Id: Ib94984717703556f41f49cfbebb824274cdb3ea2 Signed-off-by: George Cherian <george.cherian@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/33815 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-09-15octeontx2-af: Update forwarding rule action targeting VF with its default oneNaveen Mamindlapalli
commit 568c5c354fafe7dda9a7849113482cd291af282c from git@git.assembla.com:cavium/WindRiver.linux.git Dataplane applications have limitation when installing pkt forwarding rules, where they do not support explicit Rx action to the flow rules which forward the pkts to VFs. So when RVU PF is attached to a dataplane application, all the rules that it installs targeting its VFs will have an action as UCAST resulting in all the pkts being forwarded to the RQ0 of those VFs (i.e. no flow distribution) which will have an effect on performance. This patch solves this by keeping track of all such NPC MCAM entries and ensuring that the action part is in sync with whatever VF has configured in its reserved default entry. If VF configures the default entry action as RSS, the same will be updated to all the MCAM entries that its parent PF has installed targeting this VF. Change-Id: I0751b181d24431e8a1a1699d9279be4dda9dca5d Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/33807 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-25Merge branch 'v5.4/standard/base' into v5.4/standard/cn96xxBruce Ashfield
2020-08-21octeontx2-af: change (struct qmem)->entry_sz from u8 to u16Eric Dumazet
[ Upstream commit 393415203f5c916b5907e0a7c89f4c2c5a9c5505 ] We need to increase TSO_HEADER_SIZE from 128 to 256. Since otx2_sq_init() calls qmem_alloc() with TSO_HEADER_SIZE, we need to change (struct qmem)->entry_sz to avoid truncation to 0. Fixes: 7a37245ef23f ("octeontx2-af: NPA block admin queue init") Signed-off-by: Eric Dumazet <edumazet@google.com> Cc: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-08-18octeontx2-af: Check the msix offset return valueSubbaraya Sundeep
commit a5fd8dfa0c8eaf9d12a0097f4a1f8ba5b889ce67 from git@git.assembla.com:cavium/WindRiver.linux.git rvu_get_msix_offset can return invalid MSIX vector which is 0xFFFF. Hence the caller should check the return value otherwise possible array out of bounds can occur in rvu_clear_msix_offset function. Change-Id: I0757a0308d2e4418b46860e8078a73a72cea79ae Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/33195 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: Stop kpu parsing at layer3 for ipv6 fragmented packets.Abhijit Ayarekar
commit 04f786035c4b55e04d2ddb22bfc85f981ba90788 from git@git.assembla.com:cavium/WindRiver.linux.git ipv6 fragmented packet may not contain completed layer 4 information. So stop kpu parsing after setting ipv6 fragmentation flag. Change-Id: I0f49bcb47dfc5b646c1d296ee452537ea48ba756 Signed-off-by: Abhijit Ayarekar <aayarekar@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32626 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: make tx nibble fixup is always applyStanislaw Kardach
commit 9edebecf71d71add7acd9b3d2603eb342c455768 from git@git.assembla.com:cavium/WindRiver.linux.git NPC_PARSE_NIBBLE for TX interface has to be equal to the RX one for some silicon revisions. Mistakenly this fixup was only applied to the default MKEX profile while it should also be applied to any loaded profile. Change-Id: Idd4b843a5423aeca79027d49deb39b8b26dea487 Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32569 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: Fix max 16 CGX LMACs limitRakesh Babu
commit e6d90f879fa2edf72e3835f183f69785974889b7 from git@git.assembla.com:cavium/WindRiver.linux.git CN98xx supports upto 20 CGX LMAC ports. 'cgxlmac2pf_map' being 16 bit limits the number of CGX LMACs to 16. This patch fixes this limit. Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Change-Id: I1fd818cf4674a51c64920dd2103d4807f5493958 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32611 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: Simplify otx2_mbox_reset callHariprasad Kelam
commit d67f287c2818736ba534f6182dfaaae987bbd80c from git@git.assembla.com:cavium/WindRiver.linux.git Refactor otx2_mbox_reset so that __otx2_mbox_reset can be called without lock protection. Change-Id: I82bc0367530780e20e1a5b455aef1d241e348ebc Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/32457 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-18octeontx2-af: Increase number of CGX interfacesHariprasad Kelam
commit 46922d68230d3cc65bfaf1ffda8ea09c38932bc9 from git@git.assembla.com:cavium/WindRiver.linux.git 98xx board has 5 CGX interfaces adjust CGX_MAX value accordingly. Change-Id: Ide7a3952c4bb5ed35b148b0db82bfd58598f21f2 Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31918 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-08-10octeontx2-af: fix Extended DSA and eDSA parsingSatha Rao
commit 03f7a63a9b71af1657b7b7d5294b41fcf928f624 from git@git.assembla.com:cavium/WindRiver.linux.git KPU profile interpret Extended DSA and eDSA by looking source dev. This was incorrect and it restricts to use few source device ids and also created confusion while parsing regular DSA tag. With below patch lookup was based on bit 12 of Word0. This is always zero for DSA tag and it should be one for Extended DSA and eDSA. Change-Id: I0e38d5343cb630be38a243fac3848313ab6f1d4f Signed-off-by: Satha Rao <skoteshwar@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31683 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-af: reset HWS group mask during FLRMichal Mazur
commit f485b25de66b15c4c04bd708e10f5f06d5ee22a6 from git@git.assembla.com:cavium/WindRiver.linux.git This patch fixes errors caused by deprecated SSOW group mask stored in registers after application is killed and then restarted. Change-Id: I08144ae24b5a43fcecf0bea84f7cf9778dc8239a Signed-off-by: Michal Mazur <mmazur2@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/31273 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-af: Debugfs entry to show mapping btw CGX, NIX and a PF.Rakesh Babu
commit 553e1fa27d03b8907fbff81ee8699b49bdfe1b32 from git@git.assembla.com:cavium/WindRiver.linux.git Unlike earlier silicon variants, OcteonTx2 98xx silicon has 2 NIX blocks and each of the CGX is mapped to either of the NIX blocks. Each NIX block supports 100G. Mapping btw NIX blocks and CGX is done by firmware based on CGX speed config to have a maximum possible network bandwidth. Since the mapping is not fixed, it's difficult for a user to figure out. Hence added a debugfs entry which displays mapping between CGX LMAC, NIX block and RVU PF. Sample result of this entry :: ~# cat /sys/kernel/debug/octeontx2/rvu_pf_cgx_map PCI dev RVU PF Func NIX block CGX LMAC 0002:02:00.0 0x400 NIX0 CGX0 LMAC0 Change-Id: Icadea896dbadc39f7886c0fe1e6f66bab1b104eb Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/30386 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-07-13octeontx2-af: Fix REE error handlingSmadar Fuks
commit 5257c04b1ab44c21dc7027322aebfbda2aa6d742 from git@git.assembla.com:cavium/WindRiver.linux.git Fix few cases in which error indication was not propogated to the calling function: - ree_init didn't pass rvu_ree_init_block failure indication, which can be either memory allocation or polling for CSR init completion - rvu_mbox_handler_ree_rule_db_prog didn't pass programming failure - ree_rof_data_enq didn't pass failure to get AF AQ done indication Change-Id: Iaa5c9ca99b89eaba6c0cf565eede937c9709af54 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29725 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Ruiqiang Hao <Ruiqiang.Hao@windriver.com>
2020-06-25octeontx2-af: Fix deadlock between tx_stall->txsch_lock and rvu->rsrc_lockKevin Hao
The patch ("octeontx2-af: wait for tx link idle for credits change") introduces a ABBA deadlock: kworker/u49:1/257 is trying to acquire lock: 000000009c4ce30c (&tx_stall->txsch_lock){+.+.}, at: rvu_nix_update_link_credits+0x50/0x78 but task is already holding lock: 00000000dd73fbc7 (&rvu->rsrc_lock){+.+.}, at: rvu_mbox_handler_nix_set_hw_frs+0x3e8/0x648 which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (&rvu->rsrc_lock){+.+.}: __mutex_lock+0x94/0x830 mutex_lock_nested+0x3c/0x50 is_valid_txschq+0x94/0x108 rvu_mbox_handler_nix_txschq_cfg+0x16c/0x628 __rvu_mbox_handler+0x1bcc/0x27d8 rvu_afvf_mbox_handler+0x10/0x18 process_one_work+0x29c/0x6d8 worker_thread+0x50/0x418 kthread+0x108/0x138 ret_from_fork+0x10/0x18 -> #0 (&tx_stall->txsch_lock){+.+.}: lock_acquire+0xfc/0x288 __mutex_lock+0x94/0x830 mutex_lock_nested+0x3c/0x50 rvu_nix_update_link_credits+0x50/0x78 rvu_mbox_handler_nix_set_hw_frs+0x5b4/0x648 __rvu_mbox_handler+0x1fec/0x27d8 rvu_afpf_mbox_handler+0x10/0x18 process_one_work+0x29c/0x6d8 worker_thread+0x50/0x418 kthread+0x108/0x138 ret_from_fork+0x10/0x18 other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&rvu->rsrc_lock); lock(&tx_stall->txsch_lock); lock(&rvu->rsrc_lock); lock(&tx_stall->txsch_lock); Adjust the lock sequence in nix_config_link_credits() to fix this. Signed-off-by: Kevin Hao <kexin.hao@windriver.com> Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
2020-06-16octeontx2-af: fix DMAC filter table corruptionSunil Kumar Kori
commit 6c05d2a46a9246b85ed23874fa7a14900648adb1 from git@git.assembla.com:cavium/WindRiver.linux.git DMAC filter table is being corrupted in following 2 scenarios: - If CGXX has more than one lmac connected then default MAC addresses are being written continuosly starting from 0th index. Further if one DMAC filter is added to LMAC0 then entry will be added at index 1 so default MAC address for LMAC1 is corrupted. - If LMAC has DMAC filters confiured and further LMAC is set to promiscious mode then only default MAC address entry is being disabled while remaining are in enable state in conjunction of CGX(0..2)_CMR(0..3)_RX_DMAC_CTL0[CAM_ACCEPT] == 0. Because of this, mathcing traffic is dropped at CGX while they should pass as system is in promiscious mode. Patch fixes both the issues. Change-Id: I85eae1f8b1672e5c0fa3eaf4ffb42940378606e6 Signed-off-by: Sunil Kumar Kori <skori@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29170 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Add new Mbox messages and handlers for new REE blocksSmadar Fuks
commit 49706eeef363a5d492919e91e01489c173dc520b from git@git.assembla.com:cavium/WindRiver.linux.git Mailbox support for REE0 and REE1 blocks in 98xx platform. This patch adds new REE mailbox messages to mbox.h: - Config LF - REE BAR0 registers read and write - REE get Rule database length - REE get Rule database for incremental programming - REE Rule database programming This patch adds the corresponding new mbox handlers to rvu_ree.c The rule database that is passed via mbox contains instruction of address and data and is programmed to REE. For programming REE allocates memory that is accessed by HW: - 128-MB structure containing the complete compiled regular-expression graphs - AF Queue that points to 16KB blocks that hold filtering instructions REE also allocates memory for keeping the rule database that was received via mbox. It is used for immediate programming and future incremental programming Change-Id: I3679b736bafac8ba944f47252dad52fb2fce6506 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29294 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Introducing REE block for 98xxSmadar Fuks
commit a4d454585655319d82d1e97283a91d356ba1d72d from git@git.assembla.com:cavium/WindRiver.linux.git CN98XX Regular Expression Engine (REE) includes a two-part regular expression search engine consisting of filter engine and graph-walk engines. Input data (job) is searched against the regular expression rule set by first traversing the filter engine and if matched passing full Thompson NFA graph walk. These 2 REE blocks (REE0 and REE1) are introduced in 98xx. REE is provisioned using RVU. REE has up to 36 local functions (queues) A new file rvu_ree.c is added to support the new REE block with the following functions: - Initialization - Free memory - Interrupt registration and handling The following changes were done in rvu.c for ree: - Added calls to ree functions init, free memory, register/unregister interrupts and teardown - Added member struct ree_rsrc in struct rvu_pfvf to hold ree data - Added member struct rvu *rvu in struct rvu_block so that interrupt handler will know the block address Change-Id: I33184efaed9bab2954c8604d462b8945dda892d4 Signed-off-by: Smadar Fuks <smadarf@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29293 Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Enable PF BCAST entry for packet replicationSubbaraya Sundeep
commit 17d6f59e6956177ae07b0a13ed42e7ede15d1ec7 from git@git.assembla.com:cavium/WindRiver.linux.git nix_update_bcast_mce_list function used for adding or deleting a PF/VF into replication list disables PF broadcast entry if replication list is empty. Hence it is caller responsibility to enable PF broadcast entry if replication list becomes non-empty. Change-Id: I467ca6647f0b2b92e64c0919aed8213503acccff Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/29173 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Add CUSTOM0 to flow keyx algoKiran Kumar K
commit 0cbcddf12f849ee4443f76c85cac5e65cc4a58bd from git@git.assembla.com:cavium/WindRiver.linux.git Adding support to consider CUSTOM0 for Flow keyx algo hash key generation. Change-Id: Icf3826496eda83990d49f0e9360930d57db815e0 Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/28682 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Increase mbox response timeout to 3 secondsHariprasad Kelam
commit df0f9a703ba6a633789a38327f2327b409e83247 from git@git.assembla.com:cavium/WindRiver.linux.git Upon receiving mbox request from PF to configure speed, fec, higig AF sends commands to firmware and waits for max response time which is 2.2 seconds. In few scenarios firmware is taking more time to process the commands and PF is not getting mbox reply as firmware command takes more time than mbox response timeout which is 2 seconds. So increase the same to 3 seconds to accommodate above case. Change-Id: Ia114f01ae752d32da00f63cdf428aa4549da19f0 Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/28642 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Fix nix_inline_ipsec_cfg mailboxSubbaraya Sundeep
commit ee106e71f590986cd420ab80aa14aaa5040bd95f from git@git.assembla.com:cavium/WindRiver.linux.git nix_inline_ipsec_cfg may be called by AF consumer before any LF is attached to it hence call rvu_get_blkaddr accordingly. Fixes: 3bb5a5 ("octeontx2-af: Return assigned NIX/CPT block address") Change-Id: Ibf1e005f311ec4696c6aafe916cf079787aeecd1 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/28281 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Fix reading SSOW_LF_GWS_TAG after rvu_poll_reg()Radha Mohan Chintakuntla
commit 608c9be1e68ef8792dc7942f07622270204de47b from git@git.assembla.com:cavium/WindRiver.linux.git The commit "octeontx2-af: Make SSO/SSOW LF teardown less CPU intensive" introduced a bug. The value read from SSOW_LF_GWS_TAG is used in next statement. So this patch fixes by reading SSOW_LF_GWS_TAG again. Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com> Change-Id: Iefd0768ce81f6fdd807f0d67dd882ba2628b17db Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/28143 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Do not change maximum NPC interfacesSubbaraya Sundeep
commit c0193bebea210e2627a18c95d7943382048243c4 from git@git.assembla.com:cavium/WindRiver.linux.git As per the software design for loading profiles from firmware, changing the maximum interfaces macro causes incompatibility with existing profile binaries. Hence the macro is reverted. Change-Id: I2cdd28ed50f6692e0bad02b734f8c5cdee5a0ad1 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/28052 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Display NIX1 also in debugfsRakesh Babu
commit 7e9e47f4735a2ff1d4df8c7ab75c694f4387d720 from git@git.assembla.com:cavium/WindRiver.linux.git If NIX1 block is also implemented then add a new directory for NIX1 in debugfs root. Stats of NIX1 block can be read/writen from/to the files in directory "/sys/kernel/debug/octeontx2/nix1/". Change-Id: I87903f29cc681c29606f535408f96f98e3b3edc6 Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27908 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Add NIX1 interfaces to NPCSubbaraya Sundeep
commit 1c31725d1ed28b576b92da1f03a81e878b521d03 from git@git.assembla.com:cavium/WindRiver.linux.git On 98xx silicon, NPC block has additional mcam entries, counters and NIX1 interfaces. Extended set of registers are present for the new mcam entries and counters. This patch does the following: - updates the register accessing macros to use extended set if present. - configures the MKEX profile for NIX1 interfaces also. - updates mcam entry write functions to use assigned NIX0/1 interfaces for the PF/VF. Change-Id: Iaa50708672ffb1b7c3aa66c8276f42005589e2bc Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27907 Tested-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Get block address from slot numberSubbaraya Sundeep
commit e2022a2cfa0a649d9164045e3f68685c8ec9d00c from git@git.assembla.com:cavium/WindRiver.linux.git Currently there is no way in AF driver to get the RVU block address of a attached LF if caller has LFs from two blocks of same type. Hence use the slot number of LF from the caller to retrieve the block address of block from which the LF is attached. It is the responsibility of caller to provide a global slot number in mailbox. Say a PF has 3 LFs from CPT0 and 2 LFs from CPT1. Then slot number from caller is used as below: Slot 0..2 -> block address CPT0 Slot 3..4 -> block address CPT1 Change-Id: Ia88d7d2df11c5a142cd1289429a1d57a1ea957ba Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27906 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Mbox changes for 98xxSubbaraya Sundeep
commit ffda589d1af12048a8f06d441005a6840bc88882 from git@git.assembla.com:cavium/WindRiver.linux.git This patch puts together all mailbox changes for 98xx silicon: Attach -> Modify resource attach mailbox handler to request LFs from a block address out of multiple blocks of same type. If a PF/VF need LFs from two blocks of same type then attach mbox should be called twice. Example: struct rsrc_attach *attach; .. Allocate memory for message .. attach->cptlfs = 3; /* 3 LFs from CPT0 */ .. Send message .. .. Allocate memory for message .. attach->modify = 1; attach->cpt_blkaddr = BLKADDR_CPT1; attach->cptlfs = 2; /* 2 LFs from CPT1 */ .. Send message .. Detach -> Update detach mailbox and its handler to detach resources from REE0, REE1, CPT1 and NIX1 blocks. MSIX -> Updated the MSIX mailbox and its handler to return MSIX offsets for the new blocks CPT1,REE0 and REE1. Free resources -> Update free_rsrc mailbox and its handler to return the free resources count of new blocks NIX1,CPT1, REE0 and REE1. Links -> Number of CGX,LBK and SDP links may vary between platforms. For example, in 98xx number of CGX and LBK links are more than 96xx. Hence the info about number of links present in hardware is useful for consumers to request link configuration properly. This patch sends this info in nix_lf_alloc_rsp. Change-Id: I3789711cc291231917a07d5ffc1c1ad1595f8e96 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27905 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Assign NIX block addressesSubbaraya Sundeep
commit 574254216336d05b135b020203f60681d38cd39d from git@git.assembla.com:cavium/WindRiver.linux.git For CGX mapped PFs attach the NIX block address as either NIX0 or NIX1 based on the info set by firmware. For LBK VFs assign NIX0 for even numbered VFs and NIX1 for odd numbered VFs. Change-Id: I4ed0e10cad109ece7fe8d933af8d13ac37f4faae Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27904 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Add new REE blocks to AFSubbaraya Sundeep
commit ffd68a2a4008d33698905f70d2f285b246ad76a8 from git@git.assembla.com:cavium/WindRiver.linux.git With respect to RVU blocks management AF does tasks like maintaining the used and unused LFs for each block and resetting blocks. This patch adds support to manage new RVU blocks REE0 and REE1 also. Change-Id: Icafa000ac82c46e32e7608d402c9d07868ffe1ad Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27903 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Fix cpt_rd_wr_register mailboxSubbaraya Sundeep
commit 43f12d1af0e8647c4d8ab82967fedd5e4f17b209 from git@git.assembla.com:cavium/WindRiver.linux.git cpt_rd_wr_register may be called by AF consumer before any LF is attached to it hence call rvu_get_blkaddr accordingly. Fixes: 4290f456 ("octeontx2-af: Update get_rsrc_map for new blocks") Change-Id: Idb5a0d06bdf134c597f3fe127f61cbfa2e87345e Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27815 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Srujana Challa <schalla@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> (cherry picked from commit d5b5b5a294bbfad0404ae98a1b4117ceb96c43d2) Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27840 Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Add flow steering support for FDSA tagHariprasad Kelam
commit 32fad52bd254e5286d6ff9876f2680d01f7d7b8e from git@git.assembla.com:cavium/WindRiver.linux.git Marvell switches support distributed switch architecture (DSA) by implementing FORWARD(FDSA). Special pkind 62 is reserved to parse this tag. This patch adds support to configure pkind and flow steering for the same. To distribute fdsa packets among PF/VF , one can specify NPC_FDSA_VAL in mcam features .Rx vtag Type 6 is reserved to strip FDSA tag. *other changes Change mcam rule display to be more clear. Change-Id: Iaec0779fbe4a77e714e7f6d290ee2f94d98eb3a2 Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27667 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Make SSO/SSOW LF teardown less CPU intensiveRadha Mohan Chintakuntla
commit fbbbf242d1a79a0f9d968221dfbd8cf35e3130a0 from git@git.assembla.com:cavium/WindRiver.linux.git Use rvu_poll_reg() instead of continuous reading on bit set. Change-Id: I0690d4104254a0be47bf08d2df47fe0b24405b6e Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27468 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Fix MSIX handler mailboxSubbaraya Sundeep
commit 1aa116e9cea3fd66265df81c6101890d3af738cd from git@git.assembla.com:cavium/WindRiver.linux.git Changes for 98xx in msix_offset mbox handler returns error for NIX block if no NIX LF is attached to the caller. Instead return error in message response only since calling msix_offset before attaching LFs is not invalid. Fixes commit: 3bb5a5d9 ("octeontx2-af: Return assigned NIX/CPT block address") Change-Id: I7ed4226b3fbd4ad6e60059d40a98d0135c23071b Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27534 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Setup MCE context for assigned NIXSubbaraya Sundeep
commit 2306fa321b7ef445db58784c757de522bf6647b8 from git@git.assembla.com:cavium/WindRiver.linux.git Initialize MCE context for the assigned NIX0/1 block for a CGX mapped PF. Modified rvu_nix_aq_enq_inst function to work with nix_hw so that MCE contexts for both NIX blocks can be inited. Change-Id: I35cbffa19972390baeed56ce6f79fa24d8fba63b Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27437 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Map NIX block from CGX connectionSubbaraya Sundeep
commit d0f8f194eaff4b950fdd1a31ebc40d80c37dd6fc from git@git.assembla.com:cavium/WindRiver.linux.git Firmware configures NIX block mapping for all CGXs to achieve maximum throughput. This patch reads the configuration and create mapping between RVU PF and NIX blocks which can later be used for allocating NIX resources to PFs accordingly. Change-Id: I4a92b7c538f483185d36168b446db96113aa877d Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27436 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Return assigned NIX/CPT block addressSubbaraya Sundeep
commit b5cd04150ecb9c9fef05ceb4d8ace859682ba6ac from git@git.assembla.com:cavium/WindRiver.linux.git If platform has more than one NIX/CPT block then return assigned block address for the given PF/VF. This patch also uses pcifunc to retrieve NIX block address wherever rvu_get_blkaddr is called. Change-Id: I3709499bb0a211e268609aaee8edc9311dfcdff9 Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27435 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
2020-06-16octeontx2-af: Initialize NIX1 blockRakesh Babu
commit 3d40dd6dc99187674b14dd1996c0250ca20c6ca0 from git@git.assembla.com:cavium/WindRiver.linux.git If platform has NIX1 block then initialize it. This patch modifies NIX init functions to operate with nix_hw context so that same functions can be used for both NIX0 and NIX1 blocks. Change-Id: Id894a737c1323863787ab2f73a2a0567a0731899 Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/kernel/linux/+/27434 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-25 08:11:16 +0000