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path: root/drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h
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2014-06-26i40e/i40evf: Big endian fixes for handling HMCPaul M Stillwell Jr
Fix HMC handling for big endian architectures. Change-ID: Id8c46fc341815d47bfe0af8b819f0ab9a1e9e515 Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2014-05-21i40evf: Fix the headers and update copyright year.Jesse Brandeburg
Adding the appropriate GNU General Public License header and update copyright year to 2014. Change-ID: I769dd2d37d70350afd0c8727ae2859c0fd340361 Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Catherine Sullivan <catherine.sullivan@intel.com> Tested-by: Sibai Li <sibai.li@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2014-04-21i40e/i40evf: unhide and enable to one prefena fieldJesse Brandeburg
The PREFENA field in the receive host memory cache (RX-HMC) must be visible in order to be set to 1 at driver init for best performance. Change-ID: I16b0bcd84cf56f4b6c938201ff5e954bee5a1992 Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Acked-by: Shannon Nelson <shannon.nelson@intel.com> Tested-by: Kavindya Deegala <kavindya.s.deegala@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2013-12-31i40evf: A0 silicon specificGreg Rose
A0 stepping silicon specific code Signed-off-by: Greg Rose <gregory.v.rose@intel.com> Tested-by: Sibai Li <sibai.li@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2013-12-31i40evf: init code and hardware supportGreg Rose
This patch implements the hardware specific init and management. Signed-off-by: Mitch Williams <mitch.a.williams@intel.com> Signed-off-by: Greg Rose <gregory.v.rose@intel.com> Tested-by: Sibai Li <sibai.li@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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