Age | Commit message (Expand) | Author |
---|---|---|
2019-12-16 | irqchip/sifive-plic: Skip contexts except supervisor in plic_init() | |
2019-11-25 | irqchip/sifive-plic: Switch to fasteoi flow | |
2019-10-05 | irqchip/sifive-plic: set max threshold for ignored handlers | |
2019-02-21 | irqchip/sifive-plic: Implement irq_set_affinity() for SMP host | |
2019-02-21 | irqchip/sifive-plic: Differentiate between PLIC handler and context | |
2019-02-21 | irqchip/sifive-plic: Add warning in plic_init() if handler already present | |
2019-02-21 | irqchip/sifive-plic: Pre-compute context hart base and enable base | |
2019-02-14 | irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid. | |
2018-10-22 | RISC-V: Use Linux logical CPU number instead of hartid | |
2018-10-22 | RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid | |
2018-08-13 | irqchip: add a SiFive PLIC driver |