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path: root/drivers/gpu/drm/i915/intel_pm.c
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2018-08-06drm/i915: Interactive RPS modeChris Wilson
RPS provides a feedback loop where we use the load during the previous evaluation interval to decide whether to up or down clock the GPU frequency. Our responsiveness is split into 3 regimes, a high and low plateau with the intent to keep the gpu clocked high to cover occasional stalls under high load, and low despite occasional glitches under steady low load, and inbetween. However, we run into situations like kodi where we want to stay at low power (video decoding is done efficiently inside the fixed function HW and doesn't need high clocks even for high bitrate streams), but just occasionally the pipeline is more complex than a video decode and we need a smidgen of extra GPU power to present on time. In the high power regime, we sample at sub frame intervals with a bias to upclocking, and conversely at low power we sample over a few frames worth to provide what we consider to be the right levels of responsiveness respectively. At low power, we more or less expect to be kicked out to high power at the start of a busy sequence by waitboosting. Prior to commit e9af4ea2b9e7 ("drm/i915: Avoid waitboosting on the active request") whenever we missed the frame or stalled, we would immediate go full throttle and upclock the GPU to max. But in commit e9af4ea2b9e7, we relaxed the waitboosting to only apply if the pipeline was deep to avoid over-committing resources for a near miss. Sadly though, a near miss is still a miss, and perceptible as jitter in the frame delivery. To try and prevent the near miss before having to resort to boosting after the fact, we use the pageflip queue as an indication that we are in an "interactive" regime and so should sample the load more frequently to provide power before the frame misses it vblank. This will make us more favorable to providing a small power increase (one or two bins) as required rather than going all the way to maximum and then having to work back down again. (We still keep the waitboosting mechanism around just in case a dramatic change in system load requires urgent uplocking, faster than we can provide in a few evaluation intervals.) v2: Reduce rps_set_interactive to a boolean parameter to avoid the confusion of what if they wanted a new power mode after pinning to a different mode (which to choose?) v3: Only reprogram RPS while the GT is awake, it will be set when we wake the GT, and while off warns about being used outside of rpm. v4: Fix deferred application of interactive mode v5: s/state/interactive/ v6: Group the mutex with its principle in a substruct Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107111 Fixes: e9af4ea2b9e7 ("drm/i915: Avoid waitboosting on the active request") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180731132629.3381-1-chris@chris-wilson.co.uk (cherry picked from commit 60548c554be2830d29d2533dad0ac8133347ee51) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-07-12drm/i915: Silence warning for no vlv powercontextChris Wilson
Along a module load error path, we may try to cleanup the powercontext even before we have allocated it. Reorganising GT powermanagement is an on going process, so for simplicity handle it. [ 522.733832] WARN_ON(!dev_priv->vlv_pctx) [ 522.733986] WARNING: CPU: 1 PID: 3856 at drivers/gpu/drm/i915/intel_pm.c:7350 intel_cleanup_gt_powersave+0x5f/0x70 [i915] [ 522.733991] Modules linked in: i915(+) vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic btusb btrtl btbcm btintel intel_powerclamp coretemp crct10dif_pclmul crc32_pclmul bluetooth snd_hda_codec ghash_clmulni_intel snd_hwdep snd_hda_core ecdh_generic lpc_ich r8169 snd_pcm mii i2c_hid prime_numbers [last unloaded: i915] [ 522.734105] CPU: 1 PID: 3856 Comm: drv_module_relo Tainted: G U 4.18.0-rc4-CI-CI_DRM_4474+ #1 [ 522.734110] Hardware name: \xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff \xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff/DN2820FYK, BIOS FYBYT10H.86A.0059.2017.0607.2130 06/07/2017 [ 522.734193] RIP: 0010:intel_cleanup_gt_powersave+0x5f/0x70 [i915] [ 522.734197] Code: 00 74 0d 48 c7 83 68 a6 00 00 00 00 00 00 eb c8 e8 36 6f 37 e1 eb ec 48 c7 c6 c5 7a 3d a0 48 c7 c7 b5 78 3d a0 e8 71 04 e0 e0 <0f> 0b eb aa 0f 1f 00 66 2e 0f 1f 84 00 00 00 00 00 f3 c3 0f 1f 40 [ 522.734445] RSP: 0018:ffffc900004f3af0 EFLAGS: 00010282 [ 522.734453] RAX: 0000000000000000 RBX: ffff880106360000 RCX: 0000000000000001 [ 522.734458] RDX: 0000000080000001 RSI: ffffffff820c65c4 RDI: 00000000ffffffff [ 522.734463] RBP: ffff880106360000 R08: 000000009f79baee R09: 0000000000000000 [ 522.734467] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88013b3133f8 [ 522.734472] R13: 00000000ffffffed R14: ffff880106360d58 R15: ffff88013b3133f8 [ 522.734477] FS: 00007f43f70af980(0000) GS:ffff88013fd00000(0000) knlGS:0000000000000000 [ 522.734481] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 522.734486] CR2: 000055a13a787580 CR3: 00000001325e6000 CR4: 00000000001006e0 [ 522.734490] Call Trace: [ 522.734595] intel_modeset_cleanup+0xcf/0x140 [i915] [ 522.734682] i915_driver_load+0xc85/0x10a0 [i915] [ 522.734694] ? _raw_spin_unlock_irqrestore+0x4c/0x60 [ 522.734703] ? trace_hardirqs_on_caller+0xe0/0x1b0 [ 522.734790] i915_pci_probe+0x29/0x90 [i915] [ 522.734801] pci_device_probe+0xa1/0x130 [ 522.734813] driver_probe_device+0x306/0x480 [ 522.734824] __driver_attach+0xdb/0x100 [ 522.734830] ? driver_probe_device+0x480/0x480 [ 522.734836] ? driver_probe_device+0x480/0x480 [ 522.734844] bus_for_each_dev+0x74/0xc0 [ 522.734855] bus_add_driver+0x15f/0x250 [ 522.734863] ? 0xffffffffa0793000 [ 522.734870] driver_register+0x56/0xe0 [ 522.734877] ? 0xffffffffa0793000 [ 522.734883] do_one_initcall+0x58/0x370 [ 522.734893] ? do_init_module+0x1d/0x1ea [ 522.734900] ? rcu_read_lock_sched_held+0x6f/0x80 [ 522.734906] ? kmem_cache_alloc_trace+0x282/0x2e0 [ 522.734918] do_init_module+0x56/0x1ea [ 522.734927] load_module+0x2435/0x2b20 [ 522.734965] ? __se_sys_finit_module+0xd3/0xf0 [ 522.734972] __se_sys_finit_module+0xd3/0xf0 [ 522.734995] do_syscall_64+0x55/0x190 [ 522.735003] entry_SYSCALL_64_after_hwframe+0x49/0xbe [ 522.735009] RIP: 0033:0x7f43f675d839 [ 522.735014] Code: 00 f3 c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 1f f6 2c 00 f7 d8 64 89 01 48 [ 522.735260] RSP: 002b:00007ffe69384238 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 [ 522.735269] RAX: ffffffffffffffda RBX: 000056100e387090 RCX: 00007f43f675d839 [ 522.735273] RDX: 0000000000000000 RSI: 000056100e37bff0 RDI: 0000000000000003 [ 522.735278] RBP: 000056100e37bff0 R08: 0000000000000000 R09: 0000000000000000 [ 522.735282] R10: 0000000000000003 R11: 0000000000000246 R12: 0000000000000000 [ 522.735286] R13: 000056100e37c890 R14: 0000000000000020 R15: 0000000000000027 [ 522.735309] irq event stamp: 1389594 [ 522.735316] hardirqs last enabled at (1389593): [<ffffffff810f896c>] console_unlock+0x3fc/0x600 [ 522.735323] hardirqs last disabled at (1389594): [<ffffffff81a0111c>] error_entry+0x7c/0x100 [ 522.735329] softirqs last enabled at (1389356): [<ffffffff81c0034f>] __do_softirq+0x34f/0x505 [ 522.735336] softirqs last disabled at (1389335): [<ffffffff8108c7b9>] irq_exit+0xa9/0xc0 [ 522.735432] WARNING: CPU: 1 PID: 3856 at drivers/gpu/drm/i915/intel_pm.c:7350 intel_cleanup_gt_powersave+0x5f/0x70 [i915] Testcase: igt/drv_module_reload/basic-reload-inject Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180712105454.16091-1-chris@chris-wilson.co.uk
2018-06-04drm/i915/icl: Don't update enabled dbuf slices struct until updated in hwMahesh Kumar
Do not update number of enabled dbuf slices in dev_priv struct until we actually enable/disable dbuf slice in hw. This is leading to never updating dbuf slices and resulting in DBuf slice mismatch warning. Fixes: aa9664ffe863 ("drm/i915/icl: Enable 2nd DBuf slice only when needed") Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180517132626.5885-1-mahesh1.kumar@intel.com
2018-05-11drm/i915/icl: Enable Sampler DFROscar Mateo
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler power by dynamically changing its clock frequency in low-throughput conditions. This patches enables it by default on Gen11. v2: Wrong operation to clear the bit (Praveen) v3: Rebased on top of the WA refactoring v4: Move to icl_init_clock_gating, since it's not a WA (Rodrigo) v5: C, not lisp (Chris) Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Cc: Praveen Paneri <praveen.paneri@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-3-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: Introduce initial Icelake WorkaroundsOscar Mateo
Inherit workarounds from previous platforms that are still valid for Icelake. v2: GEN7_ROW_CHICKEN2 is masked v3: - Since it has been fixed already in upstream, removed the TODO comment about WA_SET_BIT for WaInPlaceDecompressionHang. - Squashed with this patch: drm/i915/icl: add icelake_init_clock_gating() from Paulo Zanoni <paulo.r.zanoni@intel.com> - Squashed with this patch: drm/i915/icl: WaForceEnableNonCoherent from Oscar Mateo <oscar.mateo@intel.com> - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and applies to B0 as well. - WaPipeControlBefore3DStateSamplePattern WABB was being applied to ICL incorrectly. v4: - Wrap the commit message - s/dev_priv/p to please checkpatch v5: Rebased on top of the WA refactoring v6: Rebased on top of further whitelist registers refactoring (Michel) v7: Added WaRsForcewakeAddDelayForAck v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika) v9: - C, not lisp (Chris) - WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko) Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tomasz Lis <tomasz.lis@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-2-git-send-email-oscar.mateo@intel.com
2018-04-27drm/i915/icl: update ddb entry start/end mask during hw ddb readoutMahesh Kumar
Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to 11 bits. This patch make changes to use proper mask for ICL+ during hardware ddb value readout. Changes since V1: - Use _MASK & _SHIFT macro (James) Changes since V2: - use kernel type u8 instead of uint8_t Changes since V3: - Rebase Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180426142517.16643-4-mahesh1.kumar@intel.com
2018-04-27drm/i915/icl: Enable 2nd DBuf slice only when neededMahesh Kumar
ICL has two slices of DBuf, each slice of size 1024 blocks. We should not always enable slice-2. It should be enabled only if display total required BW is > 12GBps OR more than 1 pipes are enabled. Changes since V1: - typecast total_data_rate to u64 before multiplication to solve any possible overflow (Rodrigo) - fix where skl_wm_get_hw_state was memsetting ddb, resulting enabled_slices to become zero - Fix the logic of calculating ddb_size Changes since V2: - If no-crtc is part of commit required_slices will have value "0", don't try to disable DBuf slice. Changes since V3: - Create a generic helper to enable/disable slice - don't return early if total_data_rate is 0, it may be cursor only commit, or atomic modeset without any plane. Changes since V4: - Solve checkpatch warnings - use kernel types u8/u64 instead of uint8_t/uint64_t Changes since V5: - Rebase Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180426142517.16643-3-mahesh1.kumar@intel.com
2018-04-27drm/i915/icl: track dbuf slice-2 statusMahesh Kumar
This patch adds support to start tracking status of DBUF slices. This is foundation to introduce support for enabling/disabling second DBUF slice dynamically for ICL. Changes Since V1: - use kernel type u8 over uint8_t Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180426142517.16643-2-mahesh1.kumar@intel.com
2018-04-09drm/i915: Change use get_new_plane_state instead of existing plane stateMaarten Lankhorst
The get_existing macros are deprecated and should be replaced by get_old/new_state for clarity. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180409124656.39886-1-maarten.lankhorst@linux.intel.com [mlankhorst: Remove useless warn. (Ville)] Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2018-04-09drm/i915/skl: split skl_compute_ddb functionMahesh Kumar
This patch splits skl_compute_wm/ddb functions into two parts. One adds all affected pipes after the commit to atomic_state structure and second part does compute the DDB. v2: Added reviewed by tag from Shashank Sharma v3: Added reviewed by from Juha-Pekka Heikkila v4: Rebased the series v5: Fixed checkpatch error. Changed *changed = true to (*changed) = true; Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-10-git-send-email-vidya.srinivas@intel.com
2018-04-09drm/i915/skl+: nv12 workaround disable WM level 1-7Mahesh Kumar
Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A) Hardware sometimes fails to wake memory from pkg C states fetching the last few lines of planar YUV 420 (NV12) planes. This causes intermittent underflow and corruption. WA: Disable package C states or do not enable latency levels 1 through 7 (WM1 - WM7) on NV12 planes. v2: Addressed review comments by Maarten. v3: Adding reviewed by tag from Shashank Sharma v4: Added reviewed by from Juha-Pekka Heikkila v5: Rebased the series Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-9-git-send-email-vidya.srinivas@intel.com
2018-04-09drm/i915/skl+: make sure higher latency level has higher wm valueMahesh Kumar
DDB allocation optimization algorithm requires/assumes ddb allocation for any memory C-state level DDB value to be as high as level below the current level. Render decompression requires level WM to be as high as wm level-0. This patch fulfils both the requirements. v2: Changed plane_num to plane_id in skl_compute_wm_levels v3: Addressed review comments from Shashank Sharma Changed the commit message "statement can be more clear, "DDB value to be as high as level below " what is level below ?" v4: Added reviewed by tag from Shashank Sharma v5: Added reviewed by from Juha-Pekka Heikkila v6: Rebased the series Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-8-git-send-email-vidya.srinivas@intel.com
2018-04-09drm/i915/skl+: pass skl_wm_level struct to wm compute funcMahesh Kumar
This patch passes skl_wm_level structure itself to watermark computation function skl_compute_plane_wm function (instead of its internal parameters). It reduces number of arguments required to be passed. v2: Addressed review comments by Shashank Sharma v3: Adding reviewed by tag from Shashank Sharma v4: Added reviewed by from Juha-Pekka Heikkila v5: Rebased the series Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-7-git-send-email-vidya.srinivas@intel.com
2018-04-09drm/i915/skl+: NV12 related changes for WMMahesh Kumar
NV12 requires WM calculation for UV plane as well. UV plane WM should also fulfill all the WM related restrictions. v2: Addressed review comments from Shashank Sharma. v3: Addressed review comments from Shashank Sharma Changed plane_num to plane_id in skl_compute_plane_wm_params and skl_compute_plane_wm. Adding reviewed by tag from Shashank Sharma v4: Added reviewed by from Juha-Pekka Heikkila v5: Rebased the series Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-6-git-send-email-vidya.srinivas@intel.com
2018-04-09drm/i915/skl+: support verification of DDB HW state for NV12Mahesh Kumar
For YUV 420 Planar formats like NV12, buffer allocation is done for Y and UV surfaces separately. For NV12 plane formats, the UV buffer allocation must be programmed in the Plane Buffer Config register and the Y buffer allocation must be programmed in the Plane NV12 Buffer Config register. Both register values should be verified during verify_wm_state. v2: Addressed review comments by Maarten. v3: Addressed review comments by Shashank Sharma. v4: Adding reviewed by tag from Shashank Sharma v5: Added reviewed by from Juha-Pekka Heikkila v6: Rebased the series Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-5-git-send-email-vidya.srinivas@intel.com
2018-04-09drm/i915/skl+: refactor WM calculation for NV12Mahesh Kumar
Current code calculates DDB for planar formats in such a way that we store DDB of plane-0 in plane 1 & vice-versa. In order to make this clean this patch refactors WM/DDB calculation for NV12 planar formats. v2: Addressed review comments by Maarten v3: Rebased and addressed review comments by Maarten v4: Fixed a compilation issue of string replacement is_nv12 to is_planar v5: Added reviewed by from Juha-Pekka Heikkila v6: Rebased the series Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-3-git-send-email-vidya.srinivas@intel.com
2018-04-09drm/i915/skl+: rename skl_wm_values struct to skl_ddb_valuesMahesh Kumar
skl_wm_values struct contains values of pipe/plane DDB only. so rename it for better readability of code. Similarly skl_copy_wm_for_pipe copies DDB values. s/skl_wm_values/skl_ddb_values s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe Changes since V1: - also change name of skl_copy_wm_for_pipe v2: Added reviewed by from Juha-Pekka Heikkila v3: Rebased the series Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1523245273-30264-2-git-send-email-vidya.srinivas@intel.com
2018-04-06drm/i915/icl: Enable RC6 and RPS in Gen11Oscar Mateo
AFAICT, once the new interrupt is in place, the rest should behave the same as Gen10. v2: Update ring frequencies (Sagar) v3: Rebase. Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180405140052.10682-5-mika.kuoppala@linux.intel.com
2018-04-06drm/i915/icl: Handle RPS interrupts correctly for Gen11Oscar Mateo
Using the new hierarchical interrupt infrastructure. v2: Rebase v3: Rebase v4: use class/instance handler (Mika) Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180405140052.10682-3-mika.kuoppala@linux.intel.com
2018-03-23drm/i915: Avoid setting ring freq on invalid rps freqsMika Kuoppala
Looping through rps frequencies when both min and max are zero ends up into an endless loop. This can happen during hardware enablement. Bail out early if rps frequencies are not correctly set yet. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180320151734.11761-1-mika.kuoppala@linux.intel.com
2018-03-08drm/i915: Index the ring frequency table by HW frequency rangeChris Wilson
When reporting the frequency table stored in the punit, report the full range and not just the user restricted frequency range. In the process keep the code to set the frequency table and read it the same. v3: As we haven't separated the sb_lock from the pcu_lock yet, there's a cycle between the pcu_lock and intel_runtime_pm_get. References: f936ec34dea8 ("drm/i915/skl: Updated the i915_ring_freq_table debugfs function") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20180308142648.4016-2-chris@chris-wilson.co.uk
2018-03-07drm/i915/cnl: Add Wa_2201832410Rodrigo Vivi
"Clock gating bug in GWL may not clear barrier state when an EOT is received, causing a hang the next time that barrier is used." HSDES: 2201832410 Cc: Rafael Antognolli <rafael.antognolli@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180307220912.3681-1-rodrigo.vivi@intel.com
2018-03-06drm/i915/cnp: Document WaSouthDisplayDisablePWMCGEGatingRodrigo Vivi
No functional change since WA is already applied. But since it has different names on different databases, let's document it here to avoid future confusion. Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180306012812.19779-1-rodrigo.vivi@intel.com
2018-03-06drm/i915/cnl: document WaVFUnitClockGatingDisableRodrigo Vivi
No functional change. WA is already properly applied. but in different databases it has different names. Let's document all of them to avoid future confusion. Cc: Rafael Antognolli <rafael.antognolli@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180306012000.18928-1-rodrigo.vivi@intel.com
2018-03-01drm/i915/icl: Interrupt handlingMika Kuoppala
v2: Rebase. v3: * Remove DPF, it has been removed from SKL+. * Fix -internal rebase wrt. execlists interrupt handling. v4: Rebase. v5: * Updated for POR changes. (Daniele Ceraolo Spurio) * Merged with irq handling fixes by Daniele Ceraolo Spurio: * Simplify the code by using gen8_cs_irq_handler. * Fix interrupt handling for the upstream kernel. v6: * Remove early bringup debug messages (Tvrtko) * Add NB about arbitrary spin wait timeout (Tvrtko) v7 (from Paulo): * Don't try to write RO bits to registers. * Don't check for PCH types that don't exist. PCH interrupts are not here yet. v9: * squashed in selector and shared register handling (Daniele) * skip writing of irq if data is not valid (Daniele) * use time_after32 (Chris) * use I915_MAX_VCS and I915_MAX_VECS (Daniele) * remove fake pm interrupt handling for later patch (Mika) v10: * Direct processing of banks. clear banks early (Chris) * remove poll on valid bit, only clear valid bit (Mika) * use raw accessors, better naming (Chris) v11: * adapt to raw_reg_[read|write] * bring back polling the valid bit (Daniele) v12: * continue if unset intr_dw (Daniele) * comment the usage of gen8_de_irq_handler bits (Daniele) Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180228101153.7224-2-mika.kuoppala@linux.intel.com
2018-02-27drm/i915/cnl: Add WaRsDisableCoarsePowerGatingRodrigo Vivi
Old Wa added now forever on CNL all steppings. With CPU P states enabled along with RC6, dispatcher hangs can happen. Cc: Rafael Antognolli <rafael.antognolli@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180222200535.9290-1-rodrigo.vivi@intel.com
2018-02-21drm/i915: Rename drm_i915_gem_request to i915_requestChris Wilson
We want to de-emphasize the link between the request (dependency, execution and fence tracking) from GEM and so rename the struct from drm_i915_gem_request to i915_request. That is we may implement the GEM user interface on top of requests, but they are an abstraction for tracking execution rather than an implementation detail of GEM. (Since they are not tied to HW, we keep the i915 prefix as opposed to intel.) In short, the spatch: @@ @@ - struct drm_i915_gem_request + struct i915_request A corollary to contracting the type name, we also harmonise on using 'rq' shorthand for local variables where space if of the essence and repetition makes 'request' unwieldy. For globals and struct members, 'request' is still much preferred for its clarity. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180221095636.6649-1-chris@chris-wilson.co.uk Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2018-02-20drm/i915: Drop WaDoubleCursorLP3Latency:ivbVille Syrjälä
WaDoubleCursorLP3Latency was meant for pre-production hardware. Drop it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130203807.13721-6-ville.syrjala@linux.intel.com Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2018-02-19drm/i915/: Initialise trans_min for skl_compute_transition_wm()Chris Wilson
clang spots drivers/gpu/drm/i915/intel_pm.c:4655:6: warning: variable 'trans_min' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] if (INTEL_GEN(dev_priv) >= 10) but fortunately for us we skip the function unless on a gen10+ device. However, to keep the function generic in case we do want to re-enable it for gen9 again, initialise trans_min to 0. References: ca47667f523e ("drm/i915/gen10: Calculate and enable transition WM") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171115105036.1094-3-chris@chris-wilson.co.uk Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-02-14drm/i915: Fixup kerneldoc for intel_pm.cChris Wilson
drivers/gpu/drm/i915/intel_pm.c:750: warning: Function parameter or member 'fifo_size' not described in 'intel_calculate_wm' drivers/gpu/drm/i915/intel_pm.c:5900: warning: Function parameter or member 'crtc' not described in 'intel_update_watermarks' Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180214140303.1561-1-chris@chris-wilson.co.uk Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2018-02-13drm/i915: Handle RC6 counter wrapTvrtko Ursulin
We can implement limited RC6 counter wrap-around protection under the assumption that clients will be reading this value more frequently than the wrap period on a given platform. With the typical wrap-around period being ~90 minutes, even with the exception of Baytrail which wraps every 13 seconds, this sounds like a reasonable assumption. Implementation works by storing a 64-bit software copy of a hardware RC6 counter, along with the previous HW counter snapshot. This enables it to detect wrap is polled frequently enough and keep the software copy monotonically incrementing. v2: * Missed GEN6_GT_GFX_RC6_LOCKED when considering slot sizing and indexing. * Fixed off-by-one in wrap-around handling. (Chris Wilson) v3: * Simplify index checking by using unsigned int. (Chris Wilson) * Expand the comment to explain why indexing works. v4: * Use __int128 if supported. v5: * Use mul_u64_u32_div. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94852 Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v3 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180208160036.29919-1-tvrtko.ursulin@linux.intel.com Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2018-02-09drm/i915: Replace some negative Gen checksTvrtko Ursulin
Instead of INTEL_GEN != x use !IS_GENx for more optimisation opportunities. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180208130606.15556-16-tvrtko.ursulin@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180209215847.6660-2-chris@chris-wilson.co.uk
2018-02-09drm/i915: Use INTEL_GEN everywhereTvrtko Ursulin
Coccinelle patch: @@ identifier p; @@ -INTEL_INFO(p)->gen +INTEL_GEN(p) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180208130606.15556-12-tvrtko.ursulin@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180209215847.6660-1-chris@chris-wilson.co.uk
2018-02-08drm/i915: Remove superfluous worker wakeups when RPS is already boostedChris Wilson
We only need to wake up the RPS worker once when initially enabling the client boost, it remains in effect then until the last client no longer requires the boost. References: https://bugs.freedesktop.org/show_bug.cgi?id=102250 References: 7b92c1bd0540 ("drm/i915: Avoid keeping waitboost active for signaling threads") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180206143137.15509-1-chris@chris-wilson.co.uk
2018-02-07drm/i915: Ignore minimum lines for level 0 in skl_compute_plane_wm, v2.Maarten Lankhorst
According to bspec, result_lines > 31 is only a maximum for latency level 1 through 7. For level 0 the number of lines is ignored, so always write 0 there to prevent overflowing the 5 bits value. This is required to make NV12 work. Changes since v1: - Rebase on top of GEN11 wm changes. It seems to use res_lines for level 0 limit calculations, but still doesn't appear to program it. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20180205105841.31634-1-maarten.lankhorst@linux.intel.com
2018-02-01drm/i915/bxt, glk: Avoid long atomic poll during CDCLK changeImre Deak
There is no requirement for doing the PCODE request polling atomically, so do that only for a short time switching to sleeping poll afterwards. The specification requires a 150usec timeout for the change notification, so let's use that for the atomic poll. Do the extra 2ms poll - needed as a workaround on BXT/GLK - in sleeping mode. v2: - rebase on v2 of patchset dropping the sandybridge_pcode_read/write refactoring (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180130142939.17983-2-imre.deak@intel.com
2018-02-01drm/i915/bxt, glk: Increase PCODE timeouts during CDCLK freq changingImre Deak
Currently we see sporadic timeouts during CDCLK changing both on BXT and GLK as reported by the Bugzilla: ticket. It's easy to reproduce this by changing the frequency in a tight loop after blanking the display. The upper bound for the completion time is 800us based on my tests, so increase it from the current 500us to 2ms; with that I couldn't trigger the problem either on BXT or GLK. Note that timeouts happened during both the change notification and the voltage level setting PCODE request. (For the latter one BSpec doesn't require us to wait for completion before further HW programming.) This issue is similar to commit 2c7d0602c815 ("drm/i915/gen9: Fix PCODE polling during CDCLK change notification") but there the PCODE request does complete (as shown by the mbox busy flag), only the reply we get from PCODE indicates a failure. So there we keep resending the request until a success reply, here we just have to increase the timeout for the one PCODE request we send. v2: - s/snb_pcode_request/sandybridge_pcode_write_timeout/ (Ville) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: <stable@vger.kernel.org> # v4.4+ Acked-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103326 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130142939.17983-1-imre.deak@intel.com
2018-01-31drm/i915/gen11: fix the SAGV block time for gen11Paulo Zanoni
It's 10us for gen 11. Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130134918.32283-7-paulo.r.zanoni@intel.com
2018-01-31drm/i915/icl: NV12 y-plane ddb is not in same planeMahesh Kumar
We don't have planar pixel format support implemented for ICL yet. ICL require 2 display planes to be allocated for Planar formats unlike previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in NV12_BUF_CFG register and PLANE_NV12_BUF_CFG register is removed in ICL. This patch removes the PLANE_NV12_BUF_CFG write for ICL. Changes Since V1: - Improve commit message as per Paulo's comment Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130134918.32283-5-paulo.r.zanoni@intel.com
2018-01-31drm/i915/icl: Fail flip if ddb allocated are less than min display buffer neededMahesh Kumar
ICL require DDB allocation of plane to be more than "minimum display buffer needed" for each level in order to enable WM level. This patch implements and consider the same while allocating DDB and enabling WM. Changes Since V1: - rebase Changes Since V2: - Remove extra parentheses - Use FP16.16 only when absolutely necessary (Paulo) Changes Since V3: - Rebase Changes since v4 (from Paulo): - Coding style issue. Changes since v5 (from Paulo): - Do the final checks according to BSpec. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130134918.32283-4-paulo.r.zanoni@intel.com
2018-01-31drm/i915/icl: Do not fix dbuf block size to 512Mahesh Kumar
GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a fixed number anymore in GEN11, it varies according to bits per pixel and tiling. If 8bpp & Yf-tile surface, block size = 256 else block size = 512 This patch addresses the same. v2 (from Paulo): - Make it compile. - Fix a few coding style issues. v3: - Rebase on top of upstream patches v4 (from Paulo): - Bikeshed if statements (James). Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130134918.32283-3-paulo.r.zanoni@intel.com
2018-01-31drm/i915/icl: Don't allocate fixed bypass path blocks for ICLMahesh Kumar
GEN9 onwards bypass path allocation of 4 blocks was needed, as per hardware design. ICL doesn't require bypass path allocation of 4 DDB blocks, handling the same in this patch. v2 (from Paulo): - No need for a comment that says what the code already says. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180130134918.32283-2-paulo.r.zanoni@intel.com
2018-01-22drm/i915: Increase render/media power gating hysteresis for gen9+Chris Wilson
On gen9+, after an idle period the HW will disable the entire power well to conserve power (by preventing current leakage). It takes around a 100 microseconds to bring the power well back online afterwards. With the current hysteresis value of 25us (really 25 * 1280ns), we do not have sufficient time to respond to an interrupt and schedule the next execution before the HW powers itself down. (At present, we prevent this by grabbing the forcewake for prolonged periods of time, but that overkill fixed in the next patch.) The minimum we want to set the power gating hysteresis to is the length of time it takes us to service the GPU, which across a broad spectrum of machines is about 250us. (Note this also brings guc latency into the same ballpark as execlists.) v2: Include some notes on where I plucked the numbers from. Testcase: igt/gem_exec_nop/sequential Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Michal Winiarski <michal.winiarski@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180122135541.32222-1-chris@chris-wilson.co.uk
2017-12-19drm/i915: Implement WaDisableVFclkgate.Rafael Antognolli
This workaround supposedly fixes some hangs in the VF unit. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171216001117.14232-1-rafael.antognolli@intel.com
2017-12-12drm/i915: prefer resource_size_t for everything stolenMatthew Auld
Keeps things consistent now that we make use of struct resource. This should keep us covered in case we ever get huge amounts of stolen memory. v2: bunch of missing conversions (Chris) Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-10-matthew.auld@intel.com
2017-12-12drm/i915: make reserved struct resource centricMatthew Auld
Now that we are using struct resource to track the stolen region, it is more convenient if we track the reserved portion of that region in a resource as well. v2: s/<= end + 1/< end/ (Chris) v3: prefer DEFINE_RES_MEM Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-7-matthew.auld@intel.com
2017-12-12drm/i915: make dsm struct resource centricMatthew Auld
Now that we are using struct resource to track the stolen region, it is more convenient if we track dsm in a resource as well. v2: check range_overflow when writing to 32b registers (Chris) pepper in some comments (Chris) v3: refit i915_stolen_to_dma() v4: kill ggtt->stolen_size v5: some more polish Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171211151822.20953-6-matthew.auld@intel.com
2017-12-05drm/i915: add platform tag to WALucas De Marchi
v2: add more missing platform tags v3: change tag to cnp rather than using gen9,gen10 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171205190118.7088-2-lucas.demarchi@intel.com
2017-12-05drm/i915: follow single notation for workaround numberLucas De Marchi
v2: Allow to have or omit space before platform Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171205190118.7088-1-lucas.demarchi@intel.com
2017-12-01drm/i915: Remove unsafe i915.enable_rc6Chris Wilson
It has been many years since the last confirmed sighting (and fix) of an RC6 related bug (usually a system hang). Remove the parameter to stop users from setting dangerous values, as they often set it during triage and end up disabling the entire runtime pm instead (the option is not a fine scalpel!). Furthermore, it allows users to set known dangerous values which were intended for testing and not for production use. For testing, we can always patch in the required setting without having to expose ourselves to random abuse. v2: Fixup NEEDS_WaRsDisableCoarsePowerGating fumble, and document the lack of ilk support better. v3: Clear intel_info->rc6p if we don't support rc6 itself. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171201113030.18360-1-chris@chris-wilson.co.uk
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-22 10:53:52 +0000