summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_display.c
AgeCommit message (Expand)Author
2019-01-01Merge tag 'iommu-updates-v4.21' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds
2018-12-20Merge branches 'iommu/fixes', 'arm/renesas', 'arm/mediatek', 'arm/tegra', 'ar...Joerg Roedel
2018-12-04drm/i915/icl: fix transcoder state readoutJani Nikula
2018-12-03drm/i915: Move display device info capabilities to its own structJosé Roberto de Souza
2018-12-03drm/i915: Add HAS_DISPLAY() and use itJosé Roberto de Souza
2018-12-03drm/i915/icl: Get pipe timings for DSIMadhav Chauhan
2018-12-03drm/i915/icl: Consider DSI for getting transcoder stateMadhav Chauhan
2018-12-03drm/i915/icl: Calculate DPLL params for DSIMadhav Chauhan
2018-12-03drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooksJani Nikula
2018-11-29drm/i915/dp: Disable DSC in source by disabling DSS CTL bitsManasi Navare
2018-11-29drm/i915/dp: Compute DSC pipe config in atomic checkManasi Navare
2018-11-29drm/i915: Decouple SKL stride units from intel_fb_stride_alignment()Ville Syrjälä
2018-11-29drm/i915: Make sure fb gtt offsets stay within 32bitsVille Syrjälä
2018-11-28drm/i915: Commit skl+ planes in an order that avoids ddb overlapsVille Syrjälä
2018-11-28drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+Ville Syrjälä
2018-11-28drm/i915: Pass the new crtc_state to ->disable_plane()Ville Syrjälä
2018-11-28drm/i915: Introduce crtc_state->update_planes bitmaskVille Syrjälä
2018-11-28drm/i915: Reorganize plane register writes to make them more atomicVille Syrjälä
2018-11-22drm/i915: Eliminate the horrendous format check codeVille Syrjälä
2018-11-21drm/i915: Add rotation readout for plane initial configVille Syrjälä
2018-11-21drm/i915: Force a LUT update in intel_initial_commit()Ville Syrjälä
2018-11-21drm/i915: Add rotation readout for plane initial configVille Syrjälä
2018-11-21drm/i915: Force a LUT update in intel_initial_commit()Ville Syrjälä
2018-11-15drm/i915: Account for scale factor when calculating initial phaseVille Syrjälä
2018-11-13drm/i915: Move skip_intermediate_wm handling into ilk_compute_intermediate_wm()Ville Syrjälä
2018-11-13drm/i915: Account for scale factor when calculating initial phaseVille Syrjälä
2018-11-12iommu/vtd: Cleanup dma_remapping.h headerLu Baolu
2018-11-12drm/i915: Clean up the baseline bpp computationVille Syrjälä
2018-11-12drm/i915: Remove pointless goto failVille Syrjälä
2018-11-12drm/i915: Handle -EDEADLK from ironlake_check_fdi_lanes()Ville Syrjälä
2018-11-09drm/i915: Generalize skl_ddb_allocation_overlaps()Ville Syrjälä
2018-11-09drm/i915: Sanitize PCH port transcoder select on IBXVille Syrjälä
2018-11-08drm/i915: Keep overlay functions naming consistentJosé Roberto de Souza
2018-11-08drm/i915: Move FBC init and cleanup calls to modeset functionsJosé Roberto de Souza
2018-11-07drm/i915: Nuke posting reads from plane update/disable funcsVille Syrjälä
2018-11-06drm/i915: Fix ilk+ watermarks when disabling pipesVille Syrjälä
2018-11-06drm/i915: Fix error handling for the NV12 fb dimensions checkVille Syrjälä
2018-11-06drm/i915/icl: Enable Plane Input CSC for YUV to RGB ConversionUma Shankar
2018-11-05drm/i915: Fix ilk+ watermarks when disabling pipesVille Syrjälä
2018-11-02drm/i915: Allow "max bpc" property to limit pipe_bppRadhakrishna Sripada
2018-11-02drm/i915/icl+: Sanitize port to PLL mappingImre Deak
2018-11-02drm/i915: Enable AUX power earlierImre Deak
2018-11-02drm/i915: Use a helper to get the aux power domainImre Deak
2018-11-01drm/i915: Remove CNL from WA 827Rodrigo Vivi
2018-11-01drm/i915: Define WA 0870 and kill dead code.Rodrigo Vivi
2018-11-01drm/i915: Kill WA 0528Rodrigo Vivi
2018-11-01drm/i915/icl: Find DSI presence for ICLMadhav Chauhan
2018-10-31drm/i915: Fix error handling for the NV12 fb dimensions checkVille Syrjälä
2018-10-29drm/i915: Switch the order of function parametersDhinakaran Pandiyan
2018-10-29drm/i915: Add function to check for linear surfacesDhinakaran Pandiyan
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-23 02:32:11 +0000