| Age | Commit message (Collapse) | Author |
|---|
|
[ Upstream commit f34e4651ce66a754f41203284acf09b28b9dd955 ]
Contrary to previous SoCs, bcm2711 doesn't have a prescaler in the PLL
feedback loop. Bypass it by zeroing fb_prediv_mask when running on
bcm2711.
Note that, since the prediv configuration bits were re-purposed, this
was triggering miscalculations on all clocks hanging from the VPU clock,
notably the aux UART, making its output unintelligible.
Fixes: 42de9ad400af ("clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support")
Reported-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Link: https://lore.kernel.org/r/20200730182619.23246-1-nsaenzjulienne@suse.de
Tested-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
|
[ Upstream commit bd8548d0dcdab514e08e35a3451667486d879dae ]
CONFIG_IOMEM does not exist. The correct symbol to depend on is
CONFIG_HAS_IOMEM.
Fixes: 1e7468bd9d30a21e ("clk: Specify IOMEM dependency for HSDK pll driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200803084835.21838-1-geert+renesas@glider.be
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
|
[ Upstream commit 12b90b40854a8461a02ef19f6f4474cc88d64b66 ]
In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
Link: https://lore.kernel.org/r/20200713032143.21362-1-vulab@iscas.ac.cn
Acked-by: Barry Song <baohua@kernel.org>
Fixes: 7bf21bc81f28 ("clk: sirf: re-arch to make the codes support both prima2 and atlas6")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
|
[ Upstream commit 3386af51d3bcebcba3f7becdb1ef2e384abe90cf ]
Add missing halt_check, hwcg_reg and hwcg_bit properties.
These were likely omitted when porting the driver upstream.
Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200726111215.22361-9-konradybcio@gmail.com
Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
|
[ Upstream commit c8b9002f44e4a1d2771b2f59f6de900864b1f9d7 ]
0x44 isn't a register offset, it is the value that goes into CAL_L_VAL.
Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-3-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
|
[ Upstream commit 667f39b59b494d96ae70f4217637db2ebbee3df0 ]
Fix the parents and set BRANCH_HALT_SKIP. From the downstream driver it
should be a 500us delay and not skip, however this matches what was done
for other clocks that had 500us delay in downstream.
Fixes: f73a4230d5bb ("clk: qcom: gcc: Add GPU and NPU clocks for SM8150")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20200709135251.643-2-jonathan@marek.ca
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
|
[ Upstream commit f47ee279d25fb0e010cae5d6e758e39b40eb6378 ]
The h_clk clock in the Actions Semi S500 SoC clock driver has an
invalid parent. Replace with the correct one.
Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/c57e7ebabfa970014f073b92fe95b47d3e5a70b1.1593788312.git.cristian.ciocaltea@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
|
[ Upstream commit 9c3df2b1993da9ab1110702d7b2815d5cd8c02f3 ]
The display gpll0 branch clock inside GCC needs to always be enabled.
Otherwise the AHB clk (disp_cc_mdss_ahb_clk_src) for the display clk
controller (dispcc) will stop clocking while sourcing from gpll0 when
this branch inside GCC is turned off during unused clk disabling. We can
never turn this branch off because the AHB clk for the display subsystem
is needed to read/write any registers inside the display subsystem
including clk related ones. This makes this branch a really easy way to
turn off AHB access to the display subsystem and cause all sorts of
mayhem. Let's just make the clk ops keep the clk enabled forever and
ignore any attempts to disable this clk so that dispcc accesses keep
working.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reported-by: Evan Green <evgreen@chromium.org>
Link: https://lore.kernel.org/r/1594796050-14511-1-git-send-email-tdas@codeaurora.org
Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
[sboyd@kernel.org: Fill out commit text more]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
|
[ Upstream commit cf8030d7035bd3e89c9e66f7193a7fc8057a9b9a ]
In order to make the last clock available, maxbit has to be set to the
highest bit value plus 1.
Fixes: 1c099779c1e2 ("clk: add BCM63XX gated clock controller driver")
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Link: https://lore.kernel.org/r/20200609110846.4029620-1-noltari@gmail.com
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
|
[ Upstream commit fcd2e0deae50bce48450f14c8fc5611b08d7438c ]
Currently we are not initializing the scmi clock with discrete rates
correctly. We fetch the min_rate and max_rate value only for clocks with
ranges and ignore the ones with discrete rates. This will lead to wrong
initialization of rate range when clock supports discrete rate.
Fix this by using the first and the last rate in the sorted list of the
discrete clock rates while registering the clock.
Link: https://lore.kernel.org/r/20200709081705.46084-2-sudeep.holla@arm.com
Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI")
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reported-and-tested-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux into master
Pull clk fixes from Stephen Boyd:
"A couple build fixes for issues exposed this merge window and a fix
for the eMMC clk on AST2600 SoCs that fixes the rate that is
calculated by the clk framework"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: Specify IOMEM dependency for HSDK pll driver
clk: AST2600: Add mux for EMMC clock
clk: mvebu: ARMADA_AP_CPU_CLK needs to select ARMADA_AP_CP_HELPER
|
|
The HSDK pll driver uses the devm_ioremap_resource function, but does
not specify a dependency on IOMEM in Kconfig. This causes a build
failure on architectures without IOMEM, for example, UML (notably with
make allyesconfig).
Fix this by making CONFIG_CLK_HSDK depend on CONFIG_IOMEM.
Signed-off-by: David Gow <davidgow@google.com>
Link: https://lore.kernel.org/r/20200630043214.1080961-1-davidgow@google.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The EMMC clock can be derived from either the HPLL or the MPLL. Register
a clock mux so that the rate is calculated correctly based upon the
parent.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20200709195706.12741-2-eajames@linux.ibm.com
Acked-by: Joel Stanley <joel@jms.id.au>
Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
When building arm32 allmodconfig:
ld.lld: error: undefined symbol: ap_cp_unique_name
>>> referenced by ap-cpu-clk.c
>>> clk/mvebu/ap-cpu-clk.o:(ap_cpu_clock_probe) in archive drivers/built-in.a
ap_cp_unique_name is only compiled into the kernel image when
CONFIG_ARMADA_AP_CP_HELPER is selected (as it is not user selectable).
However, CONFIG_ARMADA_AP_CPU_CLK does not select it.
This has been a problem since the driver was added to the kernel but it
was not built before commit c318ea261749 ("cpufreq: ap806: fix cpufreq
driver needs ap cpu clk") so it was never noticed.
Fixes: f756e362d938 ("clk: mvebu: add CPU clock driver for Armada 7K/8K")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Link: https://lore.kernel.org/r/20200701201128.2448427-1-natechancellor@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The (struct __prci_data).hw_clks.hws is an array with dynamic elements.
Using struct_size(pd, hw_clks.hws, ARRAY_SIZE(__prci_init_clocks))
instead of sizeof(*pd) to get the correct memory size of
struct __prci_data for sifive/fu540-prci. After applying this
modifications, the kernel runs smoothly with CONFIG_SLAB_FREELIST_RANDOM
enabled on the HiFive unleashed board.
Fixes: 30b8e27e3b58 ("clk: sifive: add a driver for the SiFive FU540 PRCI IP block")
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
|
|
Since commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over
'---help---'"), the number of '---help---' has been gradually
decreasing, but there are still more than 2400 instances.
This commit finishes the conversion. While I touched the lines,
I also fixed the indentation.
There are a variety of indentation styles found.
a) 4 spaces + '---help---'
b) 7 spaces + '---help---'
c) 8 spaces + '---help---'
d) 1 space + 1 tab + '---help---'
e) 1 tab + '---help---' (correct indentation)
f) 1 tab + 1 space + '---help---'
g) 1 tab + 2 spaces + '---help---'
In order to convert all of them to 1 tab + 'help', I ran the
following commend:
$ find . -name 'Kconfig*' | xargs sed -i 's/^[[:space:]]*---help---/\thelp/'
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This time around we have four lines of diff in the core framework,
removing a function that isn't used anymore. Otherwise the main new
thing for the common clk framework is that it is selectable in the
Kconfig language now. Hopefully this will let clk drivers and clk
consumers be testable on more than the architectures that support the
clk framework. The goal is to introduce some Kunit tests for the
framework.
Outside of the core framework we have the usual set of various driver
updates and non-critical fixes. The dirstat shows that the new
Baikal-T1 driver is the largest addition this time around in terms of
lines of code. After that the x86 (Intel), Qualcomm, and Mediatek
drivers introduce many lines to support new or upcoming SoCs. After
that the dirstat shows the usual suspects working on their SoC support
by fixing minor bugs, correcting data and converting some of their DT
bindings to YAML.
Core:
- Allow the COMMON_CLK config to be selectable
New Drivers:
- Clk driver for Baikal-T1 SoCs
- Mediatek MT6765 clock support
- Support for Intel Agilex clks
- Add support for X1830 and X1000 Ingenic SoC clk controllers
- Add support for the new Renesas RZ/G1H (R8A7742) SoC
- Add support for Qualcomm's MSM8939 Generic Clock Controller
Updates:
- Support IDT VersaClock 5P49V5925
- Bunch of updates for HSDK clock generation unit (CGU) driver
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
- Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
- Enable supply regulators for GPU gdscs on Qualcomm SoCs
- Add support for Si5342, Si5344 and Si5345 chips
- Support custom flags in Xilinx zynq firmware
- Various small fixes to the Xilinx clk driver
- A single minor rounding fix for the legacy Allwinner clock support
- A few patches from Abel Vesa as preparation of adding audiomix
clock support on i.MX
- A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and
clk-pllv3 drivers
- Drop dependency on ARM64 for i.MX8M clock driver, to support
aarch32 mode on aarch64 hardware
- A series from Peng Fan to improve i.MX8M clock drivers, using
composite clock for core and bus clk slice
- Set a better parent clock for flexcan on i.MX6UL to support CiA102
defined bit rates
- A couple changes for EMC frequency scaling on Tegra210
- Support for CPU frequency scaling on Tegra20/Tegra30
- New clk gate for CSI test pattern generator on Tegra210
- Regression fixes for Samsung exynos542x and exynos5433 SoCs
- Use of fallthrough; attribute for Samsung s3c24xx
- Updates and fixup HDMI and video clocks on Meson8b
- Fixup reset polarity on Meson8b
- Fix GPU glitch free mux switch on Meson gx and g12
- A minor fix for the currently unused suspend/resume handling on
Renesas RZ/A1 and RZ/A2
- Two more conversions of Renesas DT bindings to json-schema
- Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits)
clk: mediatek: Remove ifr{0,1}_cfg_regs structures
clk: baikal-t1: remove redundant assignment to variable 'divider'
clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible"
dt-bindings: clock: Add a missing include to MMP Audio Clock binding
dt: Add bindings for IDT VersaClock 5P49V5925
clk: vc5: Add support for IDT VersaClock 5P49V6965
clk: Add Baikal-T1 CCU Dividers driver
clk: Add Baikal-T1 CCU PLLs driver
dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
clk: mediatek: assign the initial value to clk_init_data of mtk_mux
clk: mediatek: Add MT6765 clock support
clk: mediatek: add mt6765 clock IDs
dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC
CLK: HSDK: CGU: add support for 148.5MHz clock
CLK: HSDK: CGU: support PLL bypassing
CLK: HSDK: CGU: check if PLL is bypassed first
clk: clk-si5341: Add support for the Si5345 series
...
|
|
These aren't used and the macros that reference them aren't used either.
Remove the dead code to avoid compile warnings.
Cc: Owen Chen <owen.chen@mediatek.com>
Cc: Mars Cheng <mars.cheng@mediatek.com>
Cc: Macpaul Lin <macpaul.lin@mediatek.com>
Fixes: 1aca9939bf72 ("clk: mediatek: Add MT6765 clock support")
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200609211847.27366-1-sboyd@kernel.org
|
|
The variable divider is being initialized with a value that is never read
and it is being updated later with a new value. The initialization is
redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20200602172435.70282-1-colin.king@canonical.com
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
There is a spelling mistake in a pr_err error message. Fix it.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20200602121030.39132-1-colin.king@canonical.com
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver updates from Greg KH:
"Here is the large set of char/misc driver patches for 5.8-rc1
Included in here are:
- habanalabs driver updates, loads
- mhi bus driver updates
- extcon driver updates
- clk driver updates (approved by the clock maintainer)
- firmware driver updates
- fpga driver updates
- gnss driver updates
- coresight driver updates
- interconnect driver updates
- parport driver updates (it's still alive!)
- nvmem driver updates
- soundwire driver updates
- visorbus driver updates
- w1 driver updates
- various misc driver updates
In short, loads of different driver subsystem updates along with the
drivers as well.
All have been in linux-next for a while with no reported issues"
* tag 'char-misc-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (233 commits)
habanalabs: correctly cast u64 to void*
habanalabs: initialize variable to default value
extcon: arizona: Fix runtime PM imbalance on error
extcon: max14577: Add proper dt-compatible strings
extcon: adc-jack: Fix an error handling path in 'adc_jack_probe()'
extcon: remove redundant assignment to variable idx
w1: omap-hdq: print dev_err if irq flags are not cleared
w1: omap-hdq: fix interrupt handling which did show spurious timeouts
w1: omap-hdq: fix return value to be -1 if there is a timeout
w1: omap-hdq: cleanup to add missing newline for some dev_dbg
/dev/mem: Revoke mappings when a driver claims the region
misc: xilinx-sdfec: convert get_user_pages() --> pin_user_pages()
misc: xilinx-sdfec: cleanup return value in xsdfec_table_write()
misc: xilinx-sdfec: improve get_user_pages_fast() error handling
nvmem: qfprom: remove incorrect write support
habanalabs: handle MMU cache invalidation timeout
habanalabs: don't allow hard reset with open processes
habanalabs: GAUDI does not support soft-reset
habanalabs: add print for soft reset due to event
habanalabs: improve MMU cache invalidation code
...
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM/SoC driver updates from Arnd Bergmann:
"These are updates to SoC specific drivers that did not have another
subsystem maintainer tree to go through for some reason:
- Some bus and memory drivers for the MIPS P5600 based Baikal-T1 SoC
that is getting added through the MIPS tree.
- There are new soc_device identification drivers for TI K3, Qualcomm
MSM8939
- New reset controller drivers for NXP i.MX8MP, Renesas RZ/G1H, and
Hisilicon hi6220
- The SCMI firmware interface can now work across ARM SMC/HVC as a
transport.
- Mediatek platforms now use a new driver for their "MMSYS" hardware
block that controls clocks and some other aspects in behalf of the
media and gpu drivers.
- Some Tegra processors have improved power management support,
including getting woken up by the PMIC and cluster power down
during idle.
- A new v4l staging driver for Tegra is added.
- Cleanups and minor bugfixes for TI, NXP, Hisilicon, Mediatek, and
Tegra"
* tag 'arm-drivers-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (155 commits)
clk: sprd: fix compile-testing
bus: bt1-axi: Build the driver into the kernel
bus: bt1-apb: Build the driver into the kernel
bus: bt1-axi: Use sysfs_streq instead of strncmp
bus: bt1-axi: Optimize the return points in the driver
bus: bt1-apb: Use sysfs_streq instead of strncmp
bus: bt1-apb: Use PTR_ERR_OR_ZERO to return from request-regs method
bus: bt1-apb: Fix show/store callback identations
bus: bt1-apb: Include linux/io.h
dt-bindings: memory: Add Baikal-T1 L2-cache Control Block binding
memory: Add Baikal-T1 L2-cache Control Block driver
bus: Add Baikal-T1 APB-bus driver
bus: Add Baikal-T1 AXI-bus driver
dt-bindings: bus: Add Baikal-T1 APB-bus binding
dt-bindings: bus: Add Baikal-T1 AXI-bus binding
staging: tegra-video: fix V4L2 dependency
tee: fix crypto select
drivers: soc: ti: knav_qmss_queue: Make knav_gp_range_ops static
soc: ti: add k3 platforms chipid module driver
dt-bindings: soc: ti: add binding for k3 platforms chipid module
...
|
|
Pull ARM SoC updates from Arnd Bergmann:
"One new platform gets added, the Realtek RTD1195, which is an older
Cortex-a7 based relative of the RTD12xx chips that are already
supported in arch/arm64. The platform may also be extended to support
running 32-bit kernels on those 64-bit chips for memory-constrained
machines.
In the Renesas shmobile platform, we gain support for "RZ/G1H" or
R8A7742, an eight-core chip based on Cortex-A15 and Cortex-A7 cores,
originally released in 2016 as one of the last high-end 32-bit
designs.
There is ongoing cleanup for the integrator, tegra, imx, and omap2
platforms, with integrator getting very close to the goal of having
zero code in arch/arm/, and omap2 moving more of the chip specifics
from old board code into device tree files.
The Versatile Express platform is made more modular, with built-in
drivers now becoming loadable modules. This is part of a greater
effort for the Android OS to have a common kernel binary for all
platforms and any platform specific code in loadable modules.
The PXA platform drops support for Compulab's pxa2xx boards that had
rather unusual flash and PCI drivers but no known users remaining. All
device drivers specific to those boards can now get removed as well.
Across platforms, there is ongoing cleanup, with Geert and Rob
revisiting some a lot of Kconfig options"
* tag 'arm-soc-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (94 commits)
ARM: omap2: fix omap5_realtime_timer_init definition
ARM: zynq: Don't select CONFIG_ICST
ARM: OMAP2+: Fix regression for using local timer on non-SMP SoCs
clk: versatile: Fix kconfig dependency on COMMON_CLK_VERSATILE
ARM: davinci: fix build failure without I2C
power: reset: vexpress: fix build issue
power: vexpress: cleanup: use builtin_platform_driver
power: vexpress: add suppress_bind_attrs to true
Revert "ARM: vexpress: Don't select VEXPRESS_CONFIG"
MAINTAINERS: pxa: remove Compulab arm/pxa support
ARM: pxa: remove Compulab pxa2xx boards
bus: arm-integrator-lm: Fix return value check in integrator_ap_lm_probe()
soc: imx: move cpu code to drivers/soc/imx
ARM: imx: move cpu definitions into a header
ARM: imx: use device_initcall for imx_soc_device_init
ARM: imx: pcm037: make pcm970_sja1000_platform_data static
bus: ti-sysc: Timers no longer need legacy quirk handling
ARM: OMAP2+: Drop old timer code for dmtimer and 32k counter
ARM: dts: Configure system timers for omap2
ARM: dts: Configure system timers for ti81xx
...
|
|
I got a build failure with CONFIG_ARCH_SPRD=m when the
main portion of the clock driver failed to get linked into
the kernel:
ERROR: modpost: "sprd_pll_sc_gate_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined!
ERROR: modpost: "sprd_pll_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined!
ERROR: modpost: "sprd_div_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined!
ERROR: modpost: "sprd_comp_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined!
ERROR: modpost: "sprd_mux_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined!
ERROR: modpost: "sprd_gate_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined!
ERROR: modpost: "sprd_sc_gate_ops" [drivers/clk/sprd/sc9863a-clk.ko] undefined!
ERROR: modpost: "sprd_clk_probe" [drivers/clk/sprd/sc9863a-clk.ko] undefined!
ERROR: modpost: "sprd_clk_regmap_init" [drivers/clk/sprd/sc9863a-clk.ko] undefined!
ERROR: modpost: "sprd_pll_ops" [drivers/clk/sprd/sc9860-clk.ko] undefined!
ERROR: modpost: "sprd_div_ops" [drivers/clk/sprd/sc9860-clk.ko] undefined!
ERROR: modpost: "sprd_mux_ops" [drivers/clk/sprd/sc9860-clk.ko] undefined!
This is a combination of two trivial bugs:
- A platform should not be 'tristate', it should be a 'bool' symbol
like the other platforms, if only for consistency, and to avoid
surprises like this one.
- The clk Makefile does not traverse into the sprd subdirectory
if the platform is disabled but the drivers are enabled for
compile-testing.
Fixing either of the two would be sufficient to address the link failure,
but for correctness, both need to be changed.
Fixes: 2b1b799d7630 ("arm64: change ARCH_SPRD Kconfig to tristate")
Fixes: d41f59fd92f2 ("clk: sprd: Add common infrastructure")
Acked-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull power management updates from Rafael Wysocki:
"These rework the system-wide PM driver flags, make runtime switching
of cpuidle governors easier, improve the user space hibernation
interface code, add intel-speed-select interface documentation, add
more debug messages to the ACPI code handling suspend to idle, update
the cpufreq core and drivers, fix a minor issue in the cpuidle core
and update two cpuidle drivers, improve the PM-runtime framework,
update the Intel RAPL power capping driver, update devfreq core and
drivers, and clean up the cpupower utility.
Specifics:
- Rework the system-wide PM driver flags to make them easier to
understand and use and update their documentation (Rafael Wysocki,
Alan Stern).
- Allow cpuidle governors to be switched at run time regardless of
the kernel configuration and update the related documentation
accordingly (Hanjun Guo).
- Improve the resume device handling in the user space hibernarion
interface code (Domenico Andreoli).
- Document the intel-speed-select sysfs interface (Srinivas
Pandruvada).
- Make the ACPI code handing suspend to idle print more debug
messages to help diagnose issues with it (Rafael Wysocki).
- Fix a helper routine in the cpufreq core and correct a typo in the
struct cpufreq_driver kerneldoc comment (Rafael Wysocki, Wang
Wenhu).
- Update cpufreq drivers:
- Make the intel_pstate driver start in the passive mode by
default on systems without HWP (Rafael Wysocki).
- Add i.MX7ULP support to the imx-cpufreq-dt driver and add
i.MX7ULP to the cpufreq-dt-platdev blacklist (Peng Fan).
- Convert the qoriq cpufreq driver to a platform one, make the
platform code create a suitable device object for it and add
platform dependencies to it (Mian Yousaf Kaukab, Geert
Uytterhoeven).
- Fix wrong compatible binding in the qcom driver (Ansuel Smith).
- Build the omap driver by default for ARCH_OMAP2PLUS (Anders
Roxell).
- Add r8a7742 SoC support to the dt cpufreq driver (Lad
Prabhakar).
- Update cpuidle core and drivers:
- Fix three reference count leaks in error code paths in the
cpuidle core (Qiushi Wu).
- Convert Qualcomm SPM to a generic cpuidle driver (Stephan
Gerhold).
- Fix up the execution order when entering a domain idle state in
the PSCI driver (Ulf Hansson).
- Fix a reference counting issue related to clock management and
clean up two oddities in the PM-runtime framework (Rafael Wysocki,
Andy Shevchenko).
- Add ElkhartLake support to the Intel RAPL power capping driver and
remove an unused local MSR definition from it (Jacob Pan, Sumeet
Pawnikar).
- Update devfreq core and drivers:
- Replace strncpy() with strscpy() in the devfreq core and use
lockdep asserts instead of manual checks for a locked mutex in
it (Dmitry Osipenko, Krzysztof Kozlowski).
- Add a generic imx bus scaling driver and make it register an
interconnect device (Leonard Crestez, Gustavo A. R. Silva).
- Make the cpufreq notifier in the tegra30 driver take boosting
into account and delete an unuseful error message from that
driver (Dmitry Osipenko, Markus Elfring).
- Remove unneeded semicolon from the cpupower code (Zou Wei)"
* tag 'pm-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (51 commits)
cpuidle: Fix three reference count leaks
PM: runtime: Replace pm_runtime_callbacks_present()
PM / devfreq: Use lockdep asserts instead of manual checks for locked mutex
PM / devfreq: imx-bus: Fix inconsistent IS_ERR and PTR_ERR
PM / devfreq: Replace strncpy with strscpy
PM / devfreq: imx: Register interconnect device
PM / devfreq: Add generic imx bus scaling driver
PM / devfreq: tegra30: Delete an error message in tegra_devfreq_probe()
PM / devfreq: tegra30: Make CPUFreq notifier to take into account boosting
PM: hibernate: Restrict writes to the resume device
PM: runtime: clk: Fix clk_pm_runtime_get() error path
cpuidle: Convert Qualcomm SPM driver to a generic CPUidle driver
ACPI: EC: PM: s2idle: Extend GPE dispatching debug message
ACPI: PM: s2idle: Print type of wakeup debug messages
powercap: RAPL: remove unused local MSR define
PM: runtime: Make clear what we do when conditions are wrong in rpm_suspend()
Documentation: admin-guide: pm: Document intel-speed-select
PM: hibernate: Split off snapshot dev option
PM: hibernate: Incorporate concurrency handling
Documentation: ABI: make current_governer_ro as a candidate for removal
...
|
|
clk-next
- Support IDT VersaClock 5P49V5925
- Bunch of updates for HSDK clock generation unit (CGU) driver
- New clk driver for Baikal-T1 SoCs
* clk-vc5:
dt: Add bindings for IDT VersaClock 5P49V5925
clk: vc5: Add support for IDT VersaClock 5P49V6965
* clk-hsdk:
CLK: HSDK: CGU: add support for 148.5MHz clock
CLK: HSDK: CGU: support PLL bypassing
CLK: HSDK: CGU: check if PLL is bypassed first
* clk-mediatek:
clk: mediatek: assign the initial value to clk_init_data of mtk_mux
clk: mediatek: Add MT6765 clock support
clk: mediatek: add mt6765 clock IDs
dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC
* clk-baikal:
clk: Add Baikal-T1 CCU Dividers driver
clk: Add Baikal-T1 CCU PLLs driver
dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
|
|
'clk-silabs' into clk-next
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
- Add support for X1830 and X1000 Ingenic SoC clk controllers
- Add support for Qualcomm's MSM8939 Generic Clock Controller
- Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
- Enable supply regulators for GPU gdscs on Qualcomm SoCs
- Add support for Si5342, Si5344 and Si5345 chips
* clk-mmp:
clk: mmp2: Add audio clock controller driver
dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding
clk: mmp2: Add support for power islands
dt-bindings: marvell,mmp2: Add ids for the power domains
dt-bindings: clock: Make marvell,mmp2-clock a power controller
clk: mmp2: Add the audio clock
clk: mmp2: Add the I2S clocks
clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init()
clk: mmp2: Move thermal register defines up a bit
dt-bindings: marvell,mmp2: Add clock id for the Audio clock
dt-bindings: marvell,mmp2: Add clock id for the I2S clocks
clk: mmp: frac: Allow setting bits other than the numerator/denominator
clk: mmp: frac: Do not lose last 4 digits of precision
* clk-intel:
clk: intel: remove redundant initialization of variable rate64
clk: intel: Add CGU clock driver for a new SoC
dt-bindings: clk: intel: Add bindings document & header file for CGU
* clk-ingenic:
clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused
clk: X1000: Add FIXDIV for SSI clock of X1000.
dt-bindings: clock: Add and reorder ABI for X1000.
clk: Ingenic: Add CGU driver for X1830.
dt-bindings: clock: Add X1830 clock bindings.
clk: Ingenic: Adjust cgu code to make it compatible with X1830.
clk: Ingenic: Remove unnecessary spinlock when reading registers.
* clk-qcom:
clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src
dt-bindings: clock: Add YAML schemas for QCOM A53 PLL
clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller
clk: qcom: gcc: Add support for Secure control source clock
dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID
clk: qcom: gcc: Add support for a new frequency for SC7180
clk: qcom: Add DT bindings for MSM8939 GCC
clk: qcom: gcc: Add missing UFS clocks for SM8150
clk: qcom: gcc: Add GPU and NPU clocks for SM8150
clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc
clk: qcom: gdsc: Handle GDSC regulator supplies
clk: qcom: msm8916: Fix the address location of pll->config_reg
* clk-silabs:
clk: clk-si5341: Add support for the Si5345 series
|
|
'clk-ast2600' into clk-next
* clk-unisoc:
clk: sprd: add mipi_csi_xx gate clocks
clk: sprd: add dt-bindings include for mipi_csi_xx clocks
dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A
clk: sprd: check its parent status before reading gate clock
clk: sprd: return correct type of value for _sprd_pll_recalc_rate
clk: sprd: mark the local clock symbols static
* clk-trivial:
clk: versatile: remove redundant assignment to pointer clk
clk: clk-xgene: Fix a typo in Kconfig
clk: Remove unused inline function clk_debug_reparent
* clk-bcm:
clk: bcm2835: Constify struct debugfs_reg32
clk: bcm2835: Remove casting to bcm2835_clk_register
clk: bcm2835: Fix return type of bcm2835_register_gate
* clk-st:
clk: clk-flexgen: fix clock-critical handling
* clk-ast2600:
clk: ast2600: Fix AHB clock divider for A1
|
|
and 'clk-ti' into clk-next
- Support custom flags in Xilinx zynq firmware
- Various small fixes to the Xilinx clk driver
- Support for Intel Agilex clks
* clk-tegra:
clk: tegra: Add Tegra210 CSI TPG clock gate
clk: tegra30: Use custom CCLK implementation
clk: tegra20: Use custom CCLK implementation
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: Add custom CCLK implementation
clk: tegra: Remove the old emc_mux clock for Tegra210
clk: tegra: Implement Tegra210 EMC clock
clk: tegra: Export functions for EMC clock scaling
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
clk: tegra: Rename Tegra124 EMC clock source file
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
* clk-imx:
clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
clk: imx: add imx8m_clk_hw_composite_bus
clk: imx: add mux ops for i.MX8M composite clk
clk: imx8m: migrate A53 clk root to use composite core
clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
clk: imx8mp: Define gates for pll1/2 fixed dividers
clk: imx: imx8mp: fix pll mux bit
clk: imx8m: drop clk_hw_set_parent for A53
dt-bindings: clocks: imx8mp: Add ids for audiomix clocks
clk: imx: Add helpers for passing the device as argument
clk: imx: pll14xx: Add the device as argument when registering
clk: imx: gate2: Allow single bit gating clock
clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait
clk: imx: clk-sscg-pll: Remove unnecessary blank lines
clk: imx: drop the dependency on ARM64 for i.MX8M
clk: imx7ulp: make it easy to change ARM core clk
clk: imx: imx6ul: change flexcan clock to support CiA bitrates
* clk-zynq:
clk: zynqmp: Make zynqmp_clk_get_max_divisor static
clk: zynqmp: Update fraction clock check from custom type flags
clk: zynqmp: Add support for custom type flags
clk: zynqmp: fix memory leak in zynqmp_register_clocks
clk: zynqmp: Fix invalid clock name queries
clk: zynqmp: Fix divider2 calculation
clk: zynqmp: Limit bestdiv with maxdiv
* clk-socfpga:
clk: socfpga: agilex: add clock driver for the Agilex platform
dt-bindings: documentation: add clock bindings information for Agilex
clk: socfpga: add const to _ops data structures
clk: socfpga: remove clk_ops enable/disable methods
clk: socfpga: stratix10: use new parent data scheme
* clk-at91:
clk: at91: allow setting all PMC clock parents via DT
clk: at91: allow setting PCKx parent via DT
clk: at91: optimize pmc data allocation
clk: at91: pmc: decrement node's refcount
clk: at91: pmc: do not continue if compatible not located
clk: at91: Add peripheral clock for PTC
* clk-ti:
clk: ti: dra7: remove two unused symbols
clk: ti: dra7xx: fix RNG clock parent
clk: ti: dra7xx: mark MCAN clock as DRA76x only
clk: ti: dra7xx: fix gpu clkctrl parent
clk: ti: omap5: Add proper parent clocks for l4-secure clocks
clk: ti: omap4: Add proper parent clocks for l4-secure clocks
clk: ti: composite: fix memory leak
|
|
and 'clk-allwinner' into clk-next
- Allow the COMMON_CLK config to be selectable
* clk-selectable:
clk: Move HAVE_CLK config out of architecture layer
MIPS: Loongson64: Drop asm/clock.h include
ARM: mmp: Remove legacy clk code
clk: Allow the common clk framework to be selectable
mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF
MIPS: Remove redundant CLKDEV_LOOKUP selects
h8300: Remove redundant CLKDEV_LOOKUP selects
arm64: tegra: Remove redundant CLKDEV_LOOKUP selects
ARM: Remove redundant CLKDEV_LOOKUP selects
ARM: Remove redundant COMMON_CLK selects
* clk-amlogic:
clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
clk: meson: meson8b: Fix the polarity of the RESET_N lines
clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
clk: meson: g12a: Prepare the GPU clock tree to change at runtime
clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
clk: meson: meson8b: make the hdmi_sys clock tree mutable
clk: meson8b: export the HDMI system clock
* clk-renesas:
dt-bindings: clock: renesas: mstp: Convert to json-schema
dt-bindings: clock: renesas: div6: Convert to json-schema
clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects
clk: renesas: cpg-mssr: Add R8A7742 support
dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
clk: renesas: Add r8a7742 CPG Core Clock Definitions
dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
MAINTAINERS: Add DT Bindings for Renesas Clock Generators
clk: renesas: r9a06g032: Fix some typo in comments
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support
* clk-samsung:
clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;
clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical
* clk-allwinner:
clk: sunxi: Fix incorrect usage of round_down()
|
|
* pm-cpufreq:
cpufreq: Fix up cpufreq_boost_set_sw()
cpufreq: fix minor typo in struct cpufreq_driver doc comment
cpufreq: qoriq: Add platform dependencies
clk: qoriq: add cpufreq platform device
cpufreq: qoriq: convert to a platform driver
cpufreq: qcom: fix wrong compatible binding
cpufreq: imx-cpufreq-dt: support i.MX7ULP
cpufreq: dt: Add support for r8a7742
cpufreq: Add i.MX7ULP to cpufreq-dt-platdev blacklist
cpufreq: omap: Build driver by default for ARCH_OMAP2PLUS
cpufreq: intel_pstate: Use passive mode by default without HWP
|
|
Update IDT VersaClock 5 driver to support 5P49V6965.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20200404161537.2312297-1-aford173@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Nearly each Baikal-T1 IP-core is supposed to have a clock source
of particular frequency. But since there are greater than five
IP-blocks embedded into the SoC, the CCU PLLs can't fulfill all the
needs. Baikal-T1 CCU provides a set of fixed and configurable clock
dividers in order to generate a necessary signal for each chip
sub-block.
This driver creates the of-based hardware clocks for each divider
available in Baikal-T1 CCU. The same way as for PLLs we split the
functionality up into the clocks operations (gate, ungate, set rate,
etc) and hardware clocks declaration/registration procedures.
In accordance with the CCU documentation all its dividers are distributed
into two CCU sub-blocks: AXI-bus and system devices reference clocks.
The former sub-block is used to supply the clocks for AXI-bus interfaces
(AXI clock domains) and the later one provides the SoC IP-cores reference
clocks. Each sub-block is represented by a dedicated DT node, so they
have different compatible strings to distinguish one from another.
For some reason CCU provides the dividers of different types. Some
dividers can be gateable some can't, some are fixed while the others
are variable, some have special divider' limitations, some've got a
non-standard register layout and so on. In order to cover all of these
cases the hardware clocks driver is designed with an info-descriptor
pattern. So there are special static descriptors declared for the
dividers of each type with additional flags describing the block
peculiarity. These descriptors are then used to create hardware clocks
with proper operations.
Some CCU dividers provide a way to reset a domain they generate
a clock for. So the CCU AXI-bus and CCU system devices clock
drivers also perform the reset controller registration.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20200526222056.18072-5-Sergey.Semin@baikalelectronics.ru
[sboyd@kernel.org: Drop return from void function, silence sparse
warnings about initializing structs with NULL vs. integer]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Baikal-T1 is supposed to be supplied with a high-frequency external
oscillator. But in order to create signals suitable for each IP-block
embedded into the SoC the oscillator output is primarily connected to
a set of CCU PLLs. There are five of them to create clocks for the MIPS
P5600 cores, an embedded DDR controller, SATA, Ethernet and PCIe domains.
The last three domains though named by the biggest system interfaces in
fact include nearly all of the rest SoC peripherals. Each of the PLLs is
based on True Circuits TSMC CLN28HPM IP-core with an interface wrapper
(so called safe PLL' clocks switcher) to simplify the PLL configuration
procedure.
This driver creates the of-based hardware clocks to use them then in
the corresponding subsystems. In order to simplify the driver code we
split the functionality up into the PLLs clocks operations and hardware
clocks declaration/registration procedures.
Even though the PLLs are based on the same IP-core, they may have some
differences. In particular, some CCU PLLs support the output clock change
without gating them (like CPU or PCIe PLLs), while the others don't, some
CCU PLLs are critical and aren't supposed to be gated. In order to cover
all of these cases the hardware clocks driver is designed with an
info-descriptor pattern. So there are special static descriptors declared
for each PLL, which is then used to create a hardware clock with proper
operations. Additionally debugfs-files are provided for each PLL' field
to make sure the implemented rate-PLLs-dividers calculation algorithm is
correct.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20200526222056.18072-4-Sergey.Semin@baikalelectronics.ru
[sboyd@kernel.org: Silence sparse warning about initializing structs
with NULL vs. integer]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
CONFIG_ICST is for ARM Ltd reference platforms and isn't used by Zynq
platform, so remove selecting it. It appears to be a copy-n-paste error.
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Rob Herring <robh@kernel.org>
[arnd: remove the versatile clk driver change I added previously]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
When some new clock supports are introduced, e.g. [1]
it might lead to an error although it should be NULL because
clk_init_data is on the stack and it might have random values
if using without initialization.
Add the missing initial value to clk_init_data.
[1] https://android-review.googlesource.com/c/kernel/common/+/1278046
Fixes: a3ae549917f1 ("clk: mediatek: Add new clkmux register API")
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/1590560749-29136-1-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Add MT6765 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Link: https://lore.kernel.org/r/1582278742-1626-6-git-send-email-macpaul.lin@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Add support for 148.5MHz clock for HDMI PLL
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lkml.kernel.org/r/20200311134115.13257-4-Eugeniy.Paltsev@synopsys.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Support setting PLL to bypass mode to support output frequency
equal to input one.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lkml.kernel.org/r/20200311134115.13257-3-Eugeniy.Paltsev@synopsys.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
If PLL is bypassed the EN (enable) bit has no effect on
output clock.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lkml.kernel.org/r/20200311134115.13257-2-Eugeniy.Paltsev@synopsys.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Add support for the Si5342, Si5344 and Si5345 chips. These are equivalent
to the Si5341 family, but with more clock input options (which are not
supported yet by this driver).
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Link: https://lkml.kernel.org/r/20200507061544.11388-1-mike.looijmans@topic.nl
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
ufs_unipro_core_clk_src is required to allow UFS to clock scale for power
savings.
Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lkml.kernel.org/r/20200528142205.44003-1-jeffrey.l.hugo@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
This device id table is passed to of_match_node() later on in probe, but
on CONFIG_OF=n builds of_match_node() doesn't do anything with the
arguments. Lets just mark the table unused so that the compiler doesn't
complain about this.
drivers/clk/ingenic/tcu.c:326:34: warning: unused variable 'ingenic_tcu_of_match' [-Wunused-const-variable]
static const struct of_device_id ingenic_tcu_of_match[] __initconst = {
^
1 warning generated.
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20200528233837.70269-1-sboyd@kernel.org
|
|
1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not
directly derived from the output of SSIPLL, but from the clock
obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2"
is added for this purpose, and ensure that it initialized before
"X1000_CLK_SSIMUX" when initializing the clocks.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU, and gates of CPU, PCLK
are also added.
3.Use "CLK_OF_DECLARE_DRIVER" like the other CGU drivers.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20200528031549.13846-8-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
Add support for the clocks provided by the CGU in the Ingenic X1830
SoC, making use of the cgu code to do the heavy lifting.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20200528031549.13846-6-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The PLL of X1830 Soc from Ingenic has been greatly changed,
the bypass control is placed in another register, so now two
registers may needed to control the PLL. To this end, a new
"bypass_reg" was introduced. In addition, when calculating
rate, the PLL of X1830 introduced an extra 2x multiplier,
so a new "rate_multiplier" was introduced. And adjust the
code in jz47xx-cgu.c and x1000-cgu.c, make it to be
compatible with the new cgu code.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
It is not necessary to use spinlock when reading registers,
so remove it from cgu.c.
Suggested-by: Paul Cercueil <paul@crapouillou.net>
Suggested-by: Paul Burton <paulburton@kernel.org>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20200528031549.13846-2-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
The variable rate64 is being initialized with a value that is never read
and it is being updated later with a new value. The initialization is
redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lkml.kernel.org/r/20200528221219.535804-1-colin.king@canonical.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
|
If COMPILE_TEST is enabled, then COMMON_CLK_VERSATILE can be disabled
when dependent options like ICST are selected resulting in kconfig
warnings:
WARNING: unmet direct dependencies detected for ICST
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_VERSATILE [=n]
Selected by [y]:
- ARCH_REALVIEW [=y] && (ARCH_MULTI_V5 [=n] || ARCH_MULTI_V6 [=n] || ARCH_MULTI_V7 [=y])
- ARCH_VEXPRESS [=y] && ARCH_MULTI_V7 [=y]
- ARCH_ZYNQ [=y] && ARCH_MULTI_V7 [=y]
WARNING: unmet direct dependencies detected for CLK_SP810
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_VERSATILE [=n]
Selected by [y]:
- ARCH_REALVIEW [=y] && (ARCH_MULTI_V5 [=n] || ARCH_MULTI_V6 [=n] || ARCH_MULTI_V7 [=y])
Fix this by dropping COMMON_CLK_VERSATILE and just using 'menu' instead
of 'menuconfig'.
[arnd: add ZYNQ to the dependency list]
Link: https://lore.kernel.org/r/20200527181307.2482167-1-robh@kernel.org
Fixes: 81134fb541d4 ("clk: versatile: Rework kconfig structure")
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-clk@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
This is a driver for a block that generates master and bit clocks for
the I2S interface. It's separate from the PMUs that generate clocks for
the peripherals.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200519224151.2074597-14-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
Nicolas Saenz Julienne
Geert Uytterhoeven
Xu Wang
Konrad Dybcio
Jonathan Marek
Cristian Ciocaltea
Taniya Das
Álvaro Fernández Rojas
Sudeep Holla
Linus Torvalds
David Gow
Eddie James
Nathan Chancellor
Vincent Chen
Masahiro Yamada
Stephen Boyd
Colin Ian King
Arnd Bergmann
Rafael J. Wysocki
Adam Ford
Serge Semin
Rob Herring
Weiyi Lu
Owen Chen
Eugeniy Paltsev
Mike Looijmans
Jeffrey Hugo
周琰杰 (Zhou Yanjie)
Lubomir Rintel