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path: root/drivers/clk/sunxi-ng
AgeCommit message (Expand)Author
2021-03-04clk: sunxi-ng: h6: Fix clock divider range on some clocksAndre Przywara
2021-03-04clk: sunxi-ng: h6: Fix CEC clockAndre Przywara
2020-12-30clk: sunxi-ng: Make sure divider tables have sentinelJernej Skrabec
2020-02-24clk: sunxi-ng: add mux and pll notifiers for A64 CPU clockIcenowy Zheng
2020-02-05clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent orderSamuel Holland
2020-01-27clk: sunxi-ng: v3s: add the missing PLL_DDR1Icenowy Zheng
2020-01-27clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate registerOndrej Jirman
2020-01-27clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai
2019-12-13clk: sunxi-ng: h3/h5: Fix CSI_MCLK parentChen-Yu Tsai
2019-12-13clk: sunxi-ng: a64: Fix gate bit of DSI DPHYJagan Teki
2019-12-05clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18Colin Ian King
2019-12-01clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clockIcenowy Zheng
2019-11-20clk: sunxi-ng: h6: fix PWM gate/reset offsetRongyi Chen
2019-10-07clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocksIcenowy Zheng
2019-05-25clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0)Jernej Skrabec
2019-03-23clk: sunxi: A31: Fix wrong AHB gate numberAndre Przywara
2019-03-23clk: sunxi-ng: v3s: Fix TCON reset de-assert bitPaul Kocialkowski
2019-02-12clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocksChen-Yu Tsai
2019-01-09clk: sunxi-ng: Use u64 for calculation of NM rateJernej Skrabec
2018-11-21clk: sunxi-ng: h6: fix bus clocks' divider positionIcenowy Zheng
2018-09-07clk: sunxi-ng: sun4i: Set VCO and PLL bias current to lowest settingChen-Yu Tsai
2018-08-15Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2018-06-27clk: sunxi-ng: add A64 compatible stringIcenowy Zheng
2018-06-27clk: sunxi-ng: r40: Export video PLLsJernej Skrabec
2018-06-27clk: sunxi-ng: r40: Allow setting parent rate to display related clocksJernej Skrabec
2018-06-27clk: sunxi-ng: r40: Add minimal rate for video PLLsJernej Skrabec
2018-06-21clk: sunxi-ng: replace lib-y with obj-yMasahiro Yamada
2018-05-17clk: sunxi-ng: r40: export a regmap to access the GMAC registerIcenowy Zheng
2018-05-17clk: sunxi-ng: r40: rewrite init code to a platform driverIcenowy Zheng
2018-05-04clk: sunxi-ng: add support for H6 PRCM CCUIcenowy Zheng
2018-04-13Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds
2018-03-21clk: sunxi-ng: add missing hdmi-slow clock for H6 CCUIcenowy Zheng
2018-03-18clk: sunxi-ng: add support for the Allwinner H6 CCUIcenowy Zheng
2018-03-18clk: sunxi-ng: Support fixed post-dividers on NKMP style clocksIcenowy Zheng
2018-03-02clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEOJernej Skrabec
2018-03-02clk: sunxi-ng: h3: h5: Allow some clocks to set parent rateJernej Skrabec
2018-03-02clk: sunxi-ng: h3: h5: Add minimal rate for video PLLJernej Skrabec
2018-03-02clk: sunxi-ng: Add check for minimal rate to NM PLLsJernej Skrabec
2018-02-19clk: sunxi-ng: a31: Fix CLK_OUT_* clock opsChen-Yu Tsai
2018-02-15clk: sunxi-ng: Use u64 for calculation of nkmp rateJernej Skrabec
2018-02-15clk: sunxi-ng: Mask nkmp factors when setting registerJernej Skrabec
2018-02-13clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig nameCorentin Labbe
2018-01-26Merge branches 'clk-aspeed', 'clk-lock-UP', 'clk-mediatek' and 'clk-allwinner...Stephen Boyd
2018-01-26Merge branch 'clk-divider-container' into clk-nextStephen Boyd
2018-01-03clk: sunxi-ng: a83t: Add M divider to TCON1 clockJernej Škrabec
2017-12-29clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCUIcenowy Zheng
2017-12-29clk: sunxi-ng: add support for Allwinner H3 DE2 CCUIcenowy Zheng
2017-12-28clk: divider: fix incorrect usage of container_ofJerome Brunet
2017-12-21clk: move clock common macros out from vendor directoriesChunyan Zhang
2017-12-08clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLLChen-Yu Tsai