| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-04-16 | clk: renesas: r8a77980: Correct parent clock of PCIEC0 |   Geert Uytterhoeven | |
| According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of December 22, 2017, the parent clock of the PCIe module clock on R-Car V3H is S2D2. Fixes: ce15783c510a9905 ("clk: renesas: cpg-mssr: add R8A77980 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> | |||
| 2018-02-20 | clk: renesas: cpg-mssr: add R8A77980 support |   Sergei Shtylyov | |
| Add R-Car V3H (R8A77980) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 code. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> | |||
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