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2024-02-07clk: qcom: dispcc-*: switch to module_platform_driverDmitry Baryshkov
There is no need to register display clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240206-clk-module-platform-driver-v1-2-db799bd2feeb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: camcc-*: switch to module_platform_driverDmitry Baryshkov
There is no need to register camera clock controllers during subsys init calls. Use module_platform_driver() instead. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240206-clk-module-platform-driver-v1-1-db799bd2feeb@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: videocc-sm8550: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value for SM8550 is known and extracted from the msm-5.15 driver. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-18-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: videocc-sm8450: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8450, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-17-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: videocc-sm8350: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8350, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-16-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: videocc-sm8250: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-15-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: videocc-sm8150: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-14-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm8650: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The Venus hw on 8650 is similar to the one on 8550, follow its requirements. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-13-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm8550: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value for SM8550 is known and extracted from the msm-5.15 driver. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-12-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm8450: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8450, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-11-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm8350: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value is known for SM8350, see [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-10-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm8250: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-9-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm7150: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.14/19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-8-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sm4450: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 4450 being somewhat close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-7-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sc8280xp: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8280 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-6-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sc8180x: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained by referencing the msm-4.19 driver, which uses a single value for all platforms [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-5-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: gcc-sa8775p: Set delay for Venus CLK resetsKonrad Dybcio
Some Venus resets may require more time when toggling. Describe that. The value was obtained on a best-guess basis: msm-5.4 being the base kernel for this SoC and 8775 being generally close to 8350 which is known to require a higher delay [1]. [1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-4-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-07clk: qcom: reset: Ensure write completion on reset de/assertionKonrad Dybcio
Trying to toggle the resets in a rapid fashion can lead to the changes not actually arriving at the clock controller block when we expect them to. This was observed at least on SM8250. Read back the value after regmap_update_bits to ensure write completion. Fixes: b36ba30c8ac6 ("clk: qcom: Add reset controller support") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-3-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: reset: Commonize the de/assert functionsKonrad Dybcio
They do the same thing, except the last argument of the last function call differs. Commonize them. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-2-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: reset: Increase max reset delayKonrad Dybcio
u8 limits us to 255 microseconds of delay. Promote the delay variable to u16 to hold bigger values. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-1-c37eba13b5ce@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add camcc clock driver for x1e80100Rajendra Nayak
Add the camcc clock driver for x1e80100 Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-10-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add TCSR clock driver for x1e80100Abel Vesa
The TCSR clock controller found on X1E80100 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-9-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add GPU clock driver for x1e80100Rajendra Nayak
Add Graphics Clock Controller (GPUCC) support for X1E80100 platform. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-8-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: Add dispcc clock driver for x1e80100Rajendra Nayak
Add the dispcc clock driver for x1e80100. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-7-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-02-06clk: qcom: clk-alpha-pll: Add support for zonda ole pll configureRajendra Nayak
Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add support for it. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240202-x1e80100-clock-controllers-v4-6-7fb08c861c7c@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30clk: qcom: gpucc-sc8280xp: Add external supply for GX gdscBjorn Andersson
On SA8295P and SA8540P the GFX rail is powered by a dedicated external regulator, instead of the rpmh-controlled "gfx.lvl". Define the "vdd-gfx" as the supply regulator for the GDSC, to cause the gdsc logic to look for, and control, this external power supply. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-3-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-30clk: qcom: gdsc: Enable supply reglator in GPU GX handlerBjorn Andersson
The GX GDSC is modelled to aid the GMU in powering down the GPU in the event that the GPU crashes, so that it can be restarted again. But in the event that the power-domain is supplied through a dedicated regulator (in contrast to being a subdomin of another power-domain), something needs to turn that regulator on, both to make sure things are powered and to match the operation in gdsc_disable(). Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-2-7011c2a63037@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28clk: qcom: gcc-sm8150: Add gcc video resets for sm8150Satya Priya Kakitapalli
Add gcc video axic, axi0 and axi1 resets for the global clock controller on sm8150. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240111-sm8150-dfs-support-v2-3-6edb44c83d3b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-28clk: qcom: gcc-sm8150: Register QUPv3 RCGs for DFS on SM8150Satya Priya Kakitapalli
QUPv3 clocks support DFS and thus register the RCGs which require support for the same. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240111-sm8150-dfs-support-v2-1-6edb44c83d3b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-23clk: qcom: gcc-sdm845: Add soft dependency on rpmhpdAmit Pundir
With the addition of RPMh power domain to the GCC node in device tree, we noticed a significant delay in getting the UFS driver probed on AOSP which futher led to mount failures because Android do not support rootwait. So adding a soft dependency on RPMh power domain which informs modprobe to load rpmhpd module before gcc-sdm845. Cc: stable@vger.kernel.org # v5.4+ Fixes: 4b6ea15c0a11 ("arm64: dts: qcom: sdm845: Add missing RPMh power domain to GCC") Suggested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240123062814.2555649-1-amit.pundir@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-23clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi operationMantas Pucka
Without it system hangs upon wifi firmware load. It should be enabled by remoteproc/wifi driver. Bindings already exist for it, so add it based on vendor code. Signed-off-by: Mantas Pucka <mantas@8devices.com> Link: https://lore.kernel.org/r/1706001970-26032-1-git-send-email-mantas@8devices.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-01-19clk: qcom: gcc-x1e80100: Replace of_device.h with explicit includesStephen Rothwell
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. of_device.h isn't needed, but mod_devicetable.h and platform_device.h were implicitly included. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20231211160510.0aef871b@canb.auug.org.au [robh: Redo commit msg] Signed-off-by: Rob Herring <robh@kernel.org>
2024-01-12Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Only a couple new SoCs have support added this time, primarily for Qualcomm SM8650 based on the diffstat. Otherwise this is a collection of non-critical fixes and cleanups to various clk drivers and their DT bindings. Nothing is changed in the core clk framework this time, although there's a patch to fix a basic clk type initialization function. In general, this pile looks to be on the smaller side. New Drivers: - Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Mediatek MT7988 SoC clocks Updates: - Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP - Support for stm32mp25 clks - Add glitch free PLL setting support to si5351 clk driver - Add DSI clocks on Amlogic g12/sm1 - Add CSI and ISP clocks on Amlogic g12/sm1 - Document bindings for i.MX93 ANATOP clock driver - Free clk_node in i.MX SCU driver for resource with different owner - Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15 - Fix the name of the fvco in i.MX pll14xx by renaming it to fout - Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs - Reuse reset functionality in the Renesas RZ/G2L clock driver - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 - Cleanup variable init in Allwinner nkm module - Convert various DT bindings to YAML - A few kernel-doc fixes for Samsung SoC clock controllers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings ...
2023-12-19clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL configKonrad Dybcio
These values were missing. Add them. Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231219-topic-8650_clks-v1-2-5672bfa0eb05@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL configKonrad Dybcio
These values were missing. Add them. Fixes: 8676fd4f3874 ("clk: qcom: add the SM8650 GPU Clock Controller driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231219-topic-8650_clks-v1-1-5672bfa0eb05@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: dispcc-sm8550: Use the correct PLL configuration functionKonrad Dybcio
To ensure that all fields (particularly CAL_L and CAL_L_RINGOSC) are filled properly, use the correct prepare function for OLE PLLs. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-9-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: dispcc-sm8550: Update disp PLL settingsKonrad Dybcio
The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-8-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gpucc-sm8550: Update GPU PLL settingsKonrad Dybcio
The settings in the driver seem to have been taken from an older release. Update them to match the latest values. Fixes: bfae40744b33 ("clk: qcom: gpucc-sm8550: Add support for graphics clock controller") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-7-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: Mark RCGs shared where applicableKonrad Dybcio
The vast majority of shared RCGs were not marked as such. Fix it. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-6-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCsKonrad Dybcio
The PCIe GDSCs can be shared with other masters and should use the APCS collapse-vote register when updating the power state. This is specifically also needed to be able to disable power domains that have been enabled by boot firmware using the vote register. Following other recent Qualcomm platforms, describe this register and the corresponding mask for the PCIe (and _phy) GDSCs. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-5-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votableKonrad Dybcio
The PCIe GDSCs on most Qualcomm platforms expect the OS to always consider collapse requests as successful. This also concerns SM8550. Add the VOTABLE flag to the GDSCs in question to comply with these expectations. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-4-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-19clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flagKonrad Dybcio
All of the 8550's GCC GDSCs can and should use the retain registers so as not to lose their state when entering lower power modes. Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-3-ce1272d77540@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15clk: qcom: camcc-sc8280xp: Prevent error pointer dereferenceDan Carpenter
If "regmap" is an error pointer then calling regmap_update_bits() will crash. We only need to call regmap_update_bits() if we had written to it earlier. Fixes: ff93872a9c61 ("clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/210d48ce-6ebc-4a6b-b30f-866d10d41a16@moroto.mountain Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15clk: qcom: videocc-sm8150: Add runtime PM supportSatya Priya Kakitapalli
Add runtime PM support to ensure the supply rails are enabled when necessary. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-4-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15clk: qcom: videocc-sm8150: Add missing PLL config propertySatya Priya Kakitapalli
When the driver was ported upstream, PLL test_ctl_hi1 register value was omitted. Add it to ensure the PLLs are fully configured. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-3-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-15clk: qcom: videocc-sm8150: Update the videocc resetsSatya Priya Kakitapalli
Add all the available resets for the video clock controller on sm8150. Fixes: 5658e8cf1a8a ("clk: qcom: add video clock controller driver for SM8150") Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231201-videocc-8150-v3-2-56bec3a5e443@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: rpmh: Add support for X1E80100 rpmh clocksRajendra Nayak
Adds the RPMH clocks present in X1E80100 SoC Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-5-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: Add Global Clock controller (GCC) driver for X1E80100Rajendra Nayak
Add support for the global clock controller found on X1E80100 based devices. Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20231205061002.30759-3-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000Imran Shaik
Add ECPRI Clock Controller (ECPRICC) support for QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231123064735.2979802-4-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07clk: qcom: branch: Add mem ops support for branch2 clocksTaniya Das
Add the support for mem ops implementation to handle the sequence of enable/disable of the memories in ethernet PHY, prior to enable/disable of the respective clocks, which helps retain the respecive block's register contents. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231123064735.2979802-3-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-07-04 20:15:51 +0000