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2020-02-24clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl
[ Upstream commit 8daeaea99caabe24a0929fac17977ebfb882fa86 ] The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. This fixes a potential hang when changing the GPU frequency at runtime. Fixes: 74e1f2521f16ff ("clk: meson: meson8b: add the GPU clock tree") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-02-24clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel
[ Upstream commit d8488a41800d9f5c80bc0d17b9cc2c91b4841464 ] Some meson pll registers can be initialized with 0 as N value, introducing the following division by 0 when computing rate : UBSAN: Undefined behaviour in drivers/clk/meson/clk-pll.c:75:9 division by zero CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc3-608075-g86c9af8630e1-dirty #400 Call trace: dump_backtrace+0x0/0x1c0 show_stack+0x14/0x20 dump_stack+0xc4/0x100 ubsan_epilogue+0x14/0x68 __ubsan_handle_divrem_overflow+0x98/0xb8 __pll_params_to_rate+0xdc/0x140 meson_clk_pll_recalc_rate+0x278/0x3a0 __clk_register+0x7c8/0xbb0 devm_clk_hw_register+0x54/0xc0 meson_eeclkc_probe+0xf4/0x1a0 platform_drv_probe+0x54/0xd8 really_probe+0x16c/0x438 driver_probe_device+0xb0/0xf0 device_driver_attach+0x94/0xa0 __driver_attach+0x70/0x108 bus_for_each_dev+0xd8/0x128 driver_attach+0x30/0x40 bus_add_driver+0x1b0/0x2d8 driver_register+0xbc/0x1d0 __platform_driver_register+0x78/0x88 axg_driver_init+0x18/0x20 do_one_initcall+0xc8/0x24c kernel_init_freeable+0x2b0/0x344 kernel_init+0x10/0x128 ret_from_fork+0x10/0x18 This checks if N is null before doing the division. Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller") Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Remi Pommarel <repk@triplefau.lt> [jbrunet@baylibre.com: update the comment in above the fix] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-02-14clk: meson: g12a: fix missing uart2 in regmap tableJerome Brunet
commit b1b3f0622a9d52ac19a63619911823c89a4d85a4 upstream. UART2 peripheral is missing from the regmap fixup table of the g12a family clock controller. As it is, any access to this clock would Oops, which is not great. Add the clock to the table to fix the problem. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Reported-by: Dmitry Shmidt <dimitrysh@google.com> Tested-by: Dmitry Shmidt <dimitrysh@google.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-17clk: meson: axg-audio: fix regmap last registerJerome Brunet
commit 255cab9d27d78703f7450d720859ee146d0ee6e1 upstream. Since the addition of the g12a, the last register is AUDIO_CLK_SPDIFOUT_B_CTRL. Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support") Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-10-01clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxesNeil Armstrong
When setting the 100MHz, 500MHz, 666MHz and 1GHz rate for CPU clocks, CCF will use the SYS_PLL to handle these frequencies, but: - using FIXED_PLL derived FCLK_DIV2/DIV3 clocks is more precise - the Amlogic G12A/G12B/SM1 Suspend handling in firmware doesn't handle entering suspend using SYS_PLL for these frequencies Adding CLK_MUX_ROUND_CLOSEST on all the muxes of the non-SYS_PLL cpu clock tree helps CCF always selecting the FCLK_DIV2/DIV3 as source for these frequencies. Fixes: ffae8475b90c ("clk: meson: g12a: add notifiers to handle cpu clock change") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-01clk: meson: g12a: fix cpu clock rate settingNeil Armstrong
CLK_SET_RATE_NO_REPARENT is wrongly set on the g12a cpu premux0 clocks flags, and CLK_SET_RATE_PARENT is required for the g12a cpu premux0 clock and the g12b cpub premux0 clock, otherwise CCF always selects the SYS_PLL clock to feed the cpu cluster. Fixes: ffae8475b90c ("clk: meson: g12a: add notifiers to handle cpu clock change") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-01clk: meson: gxbb: let sar_adc_clk_div set the parent clock rateMartin Blumenstingl
The meson-saradc driver manually sets the input clock for sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB, GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up to sar_adc_clk_sel which will let the common clock framework select the best matching parent clock if we want that. This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk drivers, which both also specify CLK_SET_RATE_PARENT. Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-09-19Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' ↵Stephen Boyd
into clk-next - Set clk_init_data pointer inside clk_hw to NULL after registration * clk-init-destroy: clk: Overwrite clk_hw::init with NULL during clk_register() clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered clk: ti: Don't reference clk_init_data after registration clk: qcom: Remove error prints from DFS registration rtc: sun6i: Don't reference clk_init_data after registration clk: zx296718: Don't reference clk_init_data after registration clk: milbeaut: Don't reference clk_init_data after registration clk: socfpga: deindent code to proper indentation phy: ti: am654-serdes: Don't reference clk_init_data after registration clk: sprd: Don't reference clk_init_data after registration clk: socfpga: Don't reference clk_init_data after registration clk: sirf: Don't reference clk_init_data after registration clk: qcom: Don't reference clk_init_data after registration clk: meson: axg-audio: Don't reference clk_init_data after registration clk: lochnagar: Don't reference clk_init_data after registration clk: actions: Don't reference clk_init_data after registration * clk-doc: clk: remove extra ---help--- tags in Kconfig clk: add include guard to clk-conf.h clk: Document of_parse_clkspec() some more clk: Remove extraneous 'for' word in comments * clk-imx: (32 commits) clk: imx: imx8mn: fix pll mux bit clk: imx: imx8mm: fix pll mux bit clk: imx: clk-pll14xx: unbypass PLL by default clk: imx: pll14xx: avoid glitch when set rate clk: imx: imx8mn: fix audio pll setting clk: imx8mn: Add necessary frequency support for ARM PLL table clk: imx8mn: Add missing rate_count assignment for each PLL structure clk: imx8mn: fix int pll clk gate clk: imx8mn: Add GIC clock clk: imx8mn: Fix incorrect parents clk: imx8mm: Fix incorrect parents clk: imx8mq: Fix sys3 pll references clk: imx8mq: Unregister clks when of_clk_add_provider failed clk: imx8mm: Unregister clks when of_clk_add_provider failed clk: imx8mq: Mark AHB clock as critical clk: imx8mn: Keep uart clocks on for early console clk: imx: Remove unused function statement clk: imx7ulp: Make sure earlycon's clock is enabled clk: imx8mm: Switch to platform driver clk: imx: imx8mm: fix audio pll setting ... * clk-allwinner: clk: sunxi-ng: h6: Allow I2S to change parent rate clk: sunxi-ng: v3s: add Allwinner V3 support clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU clk: sunxi-ng: v3s: add the missing PLL_DDR1
2019-08-26clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocksNeil Armstrong
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by having a dedicate tree for each core similar to the CPU0 tree. Like the DSU tree, a supplementaty mux has been added to use the CPU0 frequency instead. But since the cluster only has a single power rail and shares a single PLL, it's not worth adding 3 unsused clock tree, so we add only the mux to select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores. They are set read-only because the early boot stages sets them to select the CPU0 input clock. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clockNeil Armstrong
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to the CPU clock tree with a supplementaty mux to select the CPU0 clock instead. Leave this as read-only since it's set up by the early boot stages. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26clk: meson: g12a: add support for SM1 GP1 PLLNeil Armstrong
Add the new GP1 PLL for the Amlogic SM1 SoC, used to feed the new DynamIQ Shared Unit of the ARM Cores Complex. This also adds a dedicated set of clock and compatible for SM1. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-20clk: meson: axg-audio: add g12a reset supportJerome Brunet
On the g12a, the register space dedicated to the audio clock also provides some resets. Let the clock controller register a reset provider as well for this SoC family. the axg SoC family does not appear to provide this feature. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-16clk: meson: axg-audio: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-4-sboyd@kernel.org Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-09Merge branch 'v5.4/dt' into v5.4/driversJerome Brunet
2019-08-09clk: meson: g12a: expose CPUB clock ID for G12BNeil Armstrong
Expose the CPUB clock id to add DVFS to the second CPU cluster of the Amlogic G12B SoC. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-09clk: meson: g12a: add notifiers to handle cpu clock changeNeil Armstrong
In order to implement clock switching for the CLKID_CPU_CLK and CLKID_CPUB_CLK, notifiers are added on specific points of the clock tree : cpu_clk / cpub_clk | \- cpu_clk_dyn | | \- cpu_clk_premux0 | | |- cpu_clk_postmux0 | | | |- cpu_clk_dyn0_div | | | \- xtal/fclk_div2/fclk_div3 | | \- xtal/fclk_div2/fclk_div3 | \- cpu_clk_premux1 | |- cpu_clk_postmux1 | | |- cpu_clk_dyn1_div | | \- xtal/fclk_div2/fclk_div3 | \- xtal/fclk_div2/fclk_div3 \ sys_pll / sys1_pll This for each cluster, a single one for G12A, two for G12B. Each cpu_clk_premux1 tree is marked as read-only and CLK_SET_RATE_NO_REPARENT, to be used as "parking" clock in a safe clock frequency. A notifier is added on each cpu_clk_premux0 to detech when CCF want to change the frequency of the cpu_clk_dyn tree. In this notifier, the cpu_clk_premux1 tree is configured to use the xtal clock and then the cpu_clk_dyn is switch to cpu_clk_premux1 while CCF updates the cpu_clk_premux0 tree. A notifier is added on each sys_pll/sys1_pll to detect when CCF wants to change the PLL clock source of the cpu_clk. In this notifier, the cpu_clk is switched to cpu_clk_dyn while CCF updates the sys_pll/sys1_pll frequency. A third small notifier is added on each cpu_clk / cpub_clk and cpu_clk_dyn, add a small delay at PRE_RATE_CHANGE/POST_RATE_CHANGE to let the other notofiers change propagate before changing the cpu_clk_premux0 and sys_pll clock trees. This notifier set permits switching the cpu_clk / cpub_clk without any glitches and using a safe parking clock while switching between sub-GHz clocks using the cpu_clk_dyn tree. This setup has been tested and validated on the Amlogic G12A and G12B SoCs running the arm64 cpuburn at [1] and cycling between all the possible cpufreq translations of each cluster and checking the final frequency using the clock-measurer, script at [2]. [1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S [2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-09clk: meson: add g12a cpu dynamic divider driverNeil Armstrong
Add a clock driver for the cpu dynamic divider, this divider needs to have a flag set before setting the divider value then removed while writing the new value to the register. This drivers implements this behavior and will be used essentially on the Amlogic G12A and G12B SoCs for cpu clock trees. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: remove clk input helperAlexandre Mergnat
The clk input function which allows clock controllers to register a bypass clock from a clock producer is no longer needed anymore since meson clock controllers have migrated to a new parent allocation method. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: remove ee input bypass clocksAlexandre Mergnat
During probe, bypass clocks (i.e. ee-in-xtal) are made from device-tree inputs to provide input clocks which can be access through global name. The cons of this method are the duplicated clocks, means more string comparison. Specify parent directly with device-tree clock name. Remove the bypass clock registration from the ee probe function. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: clk-regmap: migrate to new parent description methodAlexandre Mergnat
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (ie. when all clocks are local to the controller) and use .parent_data otherwise. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: meson8b: migrate to the new parent description methodAlexandre Mergnat
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (ie. when all clocks are local to the controller) and use .parent_data otherwise. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: axg: migrate to the new parent description methodAlexandre Mergnat
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (ie. when all clocks are local to the controller) and use .parent_data otherwise. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: gxbb: migrate to the new parent description methodAlexandre Mergnat
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (ie. when all clocks are local to the controller) and use .parent_data otherwise. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: g12a: migrate to the new parent description methodAlexandre Mergnat
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (ie. when all clocks are local to the controller) and use .parent_data otherwise. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: remove ao input bypass clocksAlexandre Mergnat
During probe, bypass clocks (i.e. ao-in-xtal) are made from device-tree inputs to provide input clocks which can be access through global name. The cons of this method are the duplicated clocks, means more string comparison. Specify parent directly with device-tree clock name. Function to regiter bypass clocks is removed. Input parameters from meson aoclk data structure are deprecated and then deleted since all aoclk files are migrated. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: axg-aoclk: migrate to the new parent description methodAlexandre Mergnat
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (when parent clocks are localy declared in the controller) and use .parent_data otherwise. Remove clk input helper and all bypass clocks (declared in probe function) which are no longer used since we are able to use device-tree clock name directly. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: gxbb-aoclk: migrate to the new parent description methodAlexandre Mergnat
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (when parent clocks are localy declared in the controller) and use .parent_data otherwise. Remove clk input helper and all bypass clocks (declared in probe function) which are no longer used since we are able to use device-tree clock name directly. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: g12a-aoclk: migrate to the new parent description methodAlexandre Mergnat
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (when parent clocks are localy declared in the controller) and use .parent_data otherwise. Remove clk input helper and all bypass clocks (declared in probe function) which are no longer used since we are able to use device-tree clock name directly. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: axg-audio: migrate to the new parent description methodAlexandre Mergnat
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. A recent patch [0] allows parents to be specified without string names or with device-tree clock name by using a new assignment structure. Migrate to the new way by using .parent_hws where possible (when parent clocks are localy declared in the controller) and use .parent_data otherwise. Remove clk input helper and all bypass clocks (declared in probe function) which are no longer used since we are able to use device-tree clock name directly. [0] commit fc0c209c147f ("clk: Allow parents to be specified without string names") Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> [jbrunet@baylibre.com: remove CLK_SET_RATE_PARENT from mst muxes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-25clk: meson: g12a: fix hifi typo in mali parent_namesAlexandre Mergnat
Replace hihi by hifi in the mali parent_names of the g12a SoC family. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-17Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This round of clk driver and framework updates is heavy on the driver update side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits) clk: consoldiate the __clk_get_hw() declarations clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK clk: Add Si5341/Si5340 driver dt-bindings: clock: Add silabs,si5341 clk: clk-si544: Implement small frequency change support clk: add BCM63XX gated clock controller driver devicetree: document the BCM63XX gated clock bindings clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: at91: sckc: add support for SAM9X60 ...
2019-06-28Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A handful of clk driver fixes and one core framework fix - Do a DT/firmware lookup in clk_core_get() even when the DT index is a nonsensical value - Fix some clk data typos in the Amlogic DT headers/code - Avoid returning junk in the TI clk driver when an invalid clk is looked for - Fix dividers for the emac clks on Stratix10 SoCs - Fix default HDA rates on Tegra210 to correct distorted audio" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: socfpga: stratix10: fix divider entry for the emac clocks clk: Do a DT parent lookup even when index < 0 clk: tegra210: Fix default rates for HDA clocks clk: ti: clkctrl: Fix returning uninitialized data clk: meson: meson8b: fix a typo in the VPU parent names array variable clk: meson: fix MPLL 50M binding id typo
2019-06-11clk: meson: g12a: mark fclk_div3 as criticalNeil Armstrong
On Amlogic Meson G12b platform, the fclk_div3 seems to be necessary for the system to operate correctly. Disabling it cause the entire system to freeze, including peripherals. Let's mark this clock as critical, fixing boot on G12b platforms. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11clk: meson: g12a: Add support for G12B CPUB clocksNeil Armstrong
Update the Meson G12A Clock driver to support the Amlogic G12B SoC. G12B clock driver is very close, the main differences are : - the clock tree is duplicated for the both clusters, and the SYS_PLL are swapped between the clusters - G12B has additional clocks like for CSI an other components Here only the cpu clock tree is handled. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11clk: meson-g12a: add temperature sensor clocksGuillaume La Roque
Add the TS clocks used by two temperature sensors Reviewed-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com> Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [fixed commit description]
2019-06-11clk: meson: meson8b: add the cts_i958 clockMartin Blumenstingl
Add the cts_i958 clock to control the clock source of the spdif output block. It is used to select whether the clock source of the spdif output is cts_amclk (when data are taken from i2s buffer) or the cts_mclk_i958 (when data are taken from the spdif buffer). The setup for this clock is identical to GXBB, so this ports commit 7eaa44f6207fb6 ("clk: meson: gxbb: add cts_i958 clock") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11clk: meson: meson8b: add the cts_mclk_i958 clocksMartin Blumenstingl
Add the SPDIF master clock also referred as cts_mclk_i958. The setup for this clock is identical to GXBB, so this ports commit 3c277c247eabeb ("clk: meson: gxbb: add cts_mclk_i958") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11clk: meson: meson8b: add the cts_amclk clocksMartin Blumenstingl
Add the I2S master clock also referred as cts_amclk. The setup for this clock is identical to GXBB, so this ports commit 4087bd4b21702d ("clk: meson: gxbb: add cts_amclk") to the Meson8/Meson8b/Meson8m2 clock driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-20clk: meson: g12a: add controller register initJerome Brunet
Add the MPLL common register initial setting Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-20clk: meson: eeclk: add init regsJerome Brunet
Like the PLL and MPLL, the controller may require some magic setting to be applied on startup. This is needed when the initial setting is not applied by the boot ROM. The controller need to do it when the setting applies to several clock, like all the MPLLs in the case of g12a. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-20clk: meson: g12a: add mpll register init sequencesJerome Brunet
Add the required init of each MPLL of the g12a. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-20clk: meson: mpll: add init callback and regsJerome Brunet
Until now (gx and axg), the mpll setting on boot (whatever the bootloader) was good enough to generate a clean fractional division. It is not the case on the g12a. While moving away from the vendor u-boot, it was noticed the fractional part of the divider was no longer applied. Like on the pll, some magic settings need to applied on the mpll register. This change adds the ability to do that on the mpll driver. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-20clk: meson: axg: spread spectrum is on mpll2Jerome Brunet
After testing, it appears that the SSEN bit controls the spread spectrum function on MPLL2, not MPLL0. Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-20clk: meson: gxbb: no spread spectrum on mpll0Jerome Brunet
The documentation says there is an SSEN bit on mpll0 but, after testing it, no spread spectrum function appears to be enabled by this bit on any of the MPLLs. Let's remove it until we know more Fixes: 1f737ffa13ef ("clk: meson: mpll: fix mpll0 fractional part ignored") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-20clk: meson: mpll: properly handle spread spectrumJerome Brunet
The bit 'SSEN' available on some MPLL DSS outputs is not related to the fractional part of the divider but to the function called 'Spread Spectrum'. This function might be used to solve EM issues by adding a jitter on clock signal. This widens the signal spectrum and weakens the peaks in it. While spread spectrum might be useful for some application, it is problematic for others, such as audio. This patch introduce a new flag to the MPLL driver to enable (or not) the spread spectrum function. Fixes: 1f737ffa13ef ("clk: meson: mpll: fix mpll0 fractional part ignored") Tested-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-20clk: meson: meson8b: fix a typo in the VPU parent names array variableMartin Blumenstingl
The variable which holds the parent names for the VPU clocks has a typo in it. Fix this typo to make the variable naming in the driver consistent. No functional changes. Fixes: 41785ce562491d ("clk: meson: meson8b: add the VPU clock trees") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-20clk: meson: fix MPLL 50M binding id typoJerome Brunet
MPLL_5OM (the capital letter o) should indeed be MPLL_50M (the number) Fix this before it gets used. Fixes: 25db146aa726 ("dt-bindings: clk: meson: add g12a periph clock controller bindings") Reported-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-07Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and ↵Stephen Boyd
'clk-basic-be' into clk-next - Remove clk_readl() and introduce BE versions of basic clk types * clk-doc: clk: Drop duplicate clk_register() documentation clk: Document and simplify clk_core_get_rate_nolock() clk: Remove 'flags' member of struct clk_fixed_rate clk: nxp: Drop 'flags' on fixed_rate clk macro clk: Document __clk_mux_determine_rate() clk: Document CLK_MUX_READ_ONLY mux flag clk: Document deprecated things clk: Collapse gpio clk kerneldoc * clk-more-critical: clk: highbank: Convert to CLK_IS_CRITICAL * clk-meson: (21 commits) clk: meson: axg-audio: add g12a support clk: meson: axg-audio: don't register inputs in the onecell data clk: meson: axg_audio: replace prefix axg by aud dt-bindings: clk: axg-audio: add g12a support clk: meson: meson8b: add the video decoder clock trees clk: meson: meson8b: add the VPU clock trees clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2 clk: meson: meson8b: use a separate clock table for Meson8m2 dt-bindings: clock: meson8b: export the video decoder clocks clk: meson-g12a: add video decoder clocks dt-bindings: clock: meson8b: export the VPU clock clk: meson-g12a: add PCIE PLL clocks dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL dt-bindings: clock: meson8b: drop the "ABP" clock definition clk: meson: g12a: add cpu clocks dt-bindings: clk: g12a-clkc: add VDEC clock IDs dt-bindings: clock: axg-audio: unexpose controller inputs dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id ... * clk-basic-be: clk: core: replace clk_{readl,writel} with {readl,writel} clk: core: remove powerpc special handling powerpc/512x: mark clocks as big endian clk: mux: add explicit big endian support clk: multiplier: add explicit big endian support clk: gate: add explicit big endian support clk: fractional-divider: add explicit big endian support clk: divider: add explicit big endian support
2019-04-08clk: meson: axg-audio: add g12a supportMaxime Jourdan
The g12a audio clock controller is largely similar to the existing axg controller, with the addition of the spdif output B and TDM pad clocks. This commit extends the existing axg audio clock controller driver to work with multiple compatibles and add the g12a specific clocks Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190329160649.31603-5-jbrunet@baylibre.com
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-06-28 01:59:06 +0000