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AgeCommit message (Expand)Author
2022-05-25riscv: dts: sifive: fu540-c000: align dma node name with dtschemaKrzysztof Kozlowski
2022-05-09riscv: patch_text: Fixup last cpu should be masterGuo Ren
2022-04-08riscv module: remove (NOLOAD)Fangrui Song
2022-04-08uaccess: fix type mismatch warnings from access_ok()Arnd Bergmann
2022-04-08riscv: Increase stack size under KASANDmitry Vyukov
2022-04-08riscv: Fix fill_callchain return valueNikita Shubin
2022-03-16riscv: Fix auipc+jalr relocation range checksEmil Renner Berthing
2022-03-08riscv: Fix config KASAN && DEBUG_VIRTUALAlexandre Ghiti
2022-03-08riscv: Fix config KASAN && SPARSEMEM && !SPARSE_VMEMMAPAlexandre Ghiti
2022-03-02riscv: fix oops caused by irqsoff latency tracerChangbin Du
2022-02-16riscv: fix build with binutils 2.38Aurelien Jarno
2022-01-20perf: Protect perf_guest_cbs with RCUSean Christopherson
2021-11-02riscv: Fix asan-stack clang buildAlexandre Ghiti
2021-11-02riscv: fix misalgned trap vector base addressChen Lu
2021-11-02riscv, bpf: Fix potential NULL dereferenceBjörn Töpel
2021-10-13RISC-V: Include clone3() on rv32Palmer Dabbelt
2021-10-13riscv/vdso: make arch_setup_additional_pages wait for mmap_sem for write kill...Tong Tiangen
2021-10-13riscv: Flush current cpu icache before other cpusAlexandre Ghiti
2021-09-26drivers: base: cacheinfo: Get rid of DEFINE_SMP_CALL_CACHE_FUNCTION()Thomas Gleixner
2021-09-03riscv: Fixup patch_text panic in ftraceGuo Ren
2021-09-03riscv: Fixup wrong ftrace remove cflagGuo Ren
2021-09-03riscv: Ensure the value of FP registers in the core dump file is up to dateVincent Chen
2021-08-04bpf: Introduce BPF nospec instruction for mitigating Spectre v4Daniel Borkmann
2021-07-14sched/core: Initialize the idle task with preemption disabledValentin Schneider
2021-06-30riscv32: Use medany C model for modulesKhem Raj
2021-06-18riscv: Use -mno-relax when using lld linkerKhem Raj
2021-06-10riscv: vdso: fix and clean-up MakefileJisheng Zhang
2021-05-22riscv: Workaround mcount name prior to clang-13Nathan Chancellor
2021-05-22riscv: Use $(LD) instead of $(CC) to link vDSONathan Chancellor
2021-05-19RISC-V: Fix error code returned by riscv_hartid_to_cpuid()Anup Patel
2021-04-21riscv: Fix spelling mistake "SPARSEMEM" to "SPARSMEM"Kefeng Wang
2021-04-16riscv,entry: fix misaligned base for excp_vect_tableZihao Yu
2021-04-07riscv: evaluate put_user() arg before enabling user accessBen Dooks
2021-03-25RISC-V: correct enum sbi_ext_rfence_fidHeinrich Schuchardt
2021-03-25riscv: Correct SPARSEMEM configurationKefeng Wang
2021-03-07riscv: Get rid of MAX_EARLY_MAPPING_SIZEAlexandre Ghiti
2021-03-04riscv: Disable KSAN_SANITIZE for vDSOTobias Klauser
2021-02-17riscv: virt_addr_valid must check the address belongs to linear mappingAlexandre Ghiti
2021-02-17Revert "dts: phy: add GPIO number and active state used for phy reset"Palmer Dabbelt
2021-02-10RISC-V: Define MAXPHYSMEM_1GB only for RV32Atish Patra
2021-01-27RISC-V: Fix maximum allowed phsyical memory for RV32Atish Patra
2021-01-27RISC-V: Set current memblock limitAtish Patra
2021-01-27riscv: defconfig: enable gpio support for HiFive UnleashedSagar Shrikant Kadam
2021-01-27dts: phy: add GPIO number and active state used for phy resetSagar Shrikant Kadam
2021-01-27dts: phy: fix missing mdio device and probe failure of vsc8541-01 deviceSagar Shrikant Kadam
2021-01-27riscv: cacheinfo: Fix using smp_processor_id() in preemptibleKefeng Wang
2021-01-27riscv: Enable interrupts during syscalls with M-ModeDamien Le Moal
2021-01-27riscv: Fix kernel time_init()Damien Le Moal
2021-01-19riscv: Trace irq on only interrupt is enabledAtish Patra
2021-01-19riscv: Fix KASAN memory mapping.Nick Hu