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2017-02-13MIPS: Fix cacheinfo overflowJames Hogan
The recently added MIPS cacheinfo support used a macro populate_cache() to populate the cacheinfo structures depending on which caches are present. However the macro contains multiple statements without enclosing them in a do {} while (0) loop, so the L2 and L3 cache conditionals in populate_cache_leaves() only conditionalised the first statement in the macro. This overflows the buffer allocated by detect_cache_attributes(), resulting in boot failures under QEMU where neither the L2 or L2 caches are present. Enclose the macro statements in a do {} while (0) block to keep the whole macro inside the conditionals. Fixes: ef462f3b64e9 ("MIPS: Add cacheinfo support") Reported-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: James Hogan <james.hogan@imgtec.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Justin Chen <justin.chen@broadcom.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: bcm-kernel-feedback-list@broadcom.com Patchwork: https://patchwork.linux-mips.org/patch/15276/
2017-01-03MIPS: Add cacheinfo supportJustin Chen
Add cacheinfo support for MIPS architectures. Use information from the cpuinfo_mips struct to populate the cacheinfo struct. This allows an architecture agnostic approach, however this also means if cache information is not properly populated within the cpuinfo_mips struct, there is nothing we can do. (I.E. c-r3k.c) Signed-off-by: Justin Chen <justin.chen@broadcom.com> Cc: f.fainelli@gmail.com Cc: linux-mips@linux-mips.org Cc: bcm-kernel-feedback-list@broadcom.com Patchwork: https://patchwork.linux-mips.org/patch/14650/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>