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2018-06-19arm64: dts: freescale: Update to use SPDX identifiersLi Yang
Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guideline Documentation/process/license-rules.rst. Note that some of the files mentioned X11 license previously but the license text actually matches MIT license. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: ls1012a: add eSDHC nodesYangbo Lu
There are two eSDHC controllers in LS1012A. This patch is to add eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: freescale: update the copyright claimsLi Yang
Update the copyright claims to comply with company policy. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-03-14arm64: dts: updated sata node on ls1012a platformYuantian Tang
Updated sata node to add ecc register address and dma coherence property. Enable sata on ls1012a platforms as well. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-01-10arm64: dts: Add support for FSL's LS1012A SoCHarninder Rai
LS1012A features an advanced 64-bit ARM v8 CortexA53 processor with 32 KB of parity protected L1-I cache, 32 KB of ECC protected L1-D cache, as well as 256 KB of ECC protected L2 cache. Features summary One 64-bit ARM-v8 Cortex-A53 core with the following capabilities - Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC protection - Speed up to 800 MHz - Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache - Neon SIMD engine - ARM v8 cryptography extensions One 16-bit DDR3L SDRAM memory controller ARM core-link CCI-400 cache coherent interconnect Cryptography acceleration (SEC) One Configurable x3 SerDes One PCI Express Gen2 controller, supporting x1 operation One serial ATA (SATA Gen 3.0) controller One USB 3.0/2.0 controller with integrated PHY Following levels of DTSI/DTS files have been created for the LS1012A SoC family: - fsl-ls1012a.dtsi: DTS-Include file for FSL LS1012A SoC. - fsl-ls1012a-frdm.dts: DTS file for FSL LS1012A FRDM board. - fsl-ls1012a-qds.dts: DTS file for FSL LS1012A QDS board. - fsl-ls1012a-rdb.dts: DTS file for FSL LS1012A RDB board. Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>