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2017-08-16ARM: dts: dra72-evm: Add pinmux configuration for MMCKishon Vijay Abraham I
Include dra72x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra72 SoC and use it in the pinctrl properties of MMC devicetree nodes present in dra72-evm.dts. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-06-19ARM: dts: dra72-evm: Add vqmmc supply to mmc1Kishon Vijay Abraham I
Add vqmmc-supply property to mmc1 dt node and populate it with ldo1_reg to reflect ldo1_out is connected to mmc1 IO lines. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2017-06-19ARM: dts: dra72-evm-common: Correct vmmc-supply for mmc2Kishon Vijay Abraham I
On dra72/dra71 evms, mmc2 vdd/ios are connected to a common 1.8V supply not 3.3V. Also the regulator that supplies 1.8V is different on dra71-evm so move the supply property from common dtsi to evm specific dts files. Fixes: a4240d3af677 ("ARM: dts: Add support for dra72-evm rev C (SR2.0)") Signed-off-by: Ravikumar Kattekola <rk@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-11-09ARM: dts: dra72: Add separate dtsi for tps65917Lokesh Vutla
dra72-evm-common.dtsi consolidates dra72-evm.dts and dra72-evm-revc.dts which also include tps65917 pmic support as both the evms uses the same pmic. But, dra71-evm has mostly similar features with a different pmic. In order to exploit dra72-evm-common.dtsi, creating a separate dtsi for tps65915 support and including it in respective board files. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-08-31ARM: dts: dra7: Add missing unit name to memory nodesJavier Martinez Canillas
This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-14ARM: dts: Add support for dra72-evm rev C (SR2.0)Nishanth Menon
DRA72-EVM now has an upgrade to Rev C with SR2.0 silicon. As part of this change, a few updates were factored in that were software incompatible with previous board in few areas: - We now use DP83867 ethernet phy instead of older DP838865 which fails in certain use cases. - Two Ethernet ports now instead of the single one in rev B. - polarities changed for certain pcf gpios - Due to SoC phy current requirements, VDDA supplies are split between ldo3 and ldo2 (ldo2 was previously unused). NOTE: DSS (VDDA_VIDEO) is still supplied by ldo5, HDMI is now supplied by LDO2 instead of using LDO3. NOTE: It does not make much sense to spin off a new board compatible flag since there is no real benefit for the same. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12ARM: dts: dra7x-evm: Provide NAND ready pinRoger Quadros
On these boards NAND ready pin status is avilable over GPMC_WAIT0 pin. Read speed increases from 13768 KiB/ to 17246 KiB/s. Write speed was unchanged at 7123 KiB/s. Measured using mtd_speedtest.ko. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-12ARM: dts: dra7xx: Fix compatible string for PCF8575 chipBen Hutchings
The binding definition for the PCF857x GPIO expanders doesn't mention a "ti,pcf8575" compatible string. This is apparently because TI is only a second source - there is no functional difference between PCF8575 chips manufactured by TI and NXP, and the same board might be populated with either depending on availability. This is not a problem in practice because the I2C core uses of_modalias_node() before matching drivers and this strips the manufacturer name. Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11ARM: dts: dra72-evm: Enable AFIFO use for McASP3Peter Ujfalusi
Since we switched to use eDMA we can now safely enable the FIFO in McASP. This will reduce the chance of McASP level under/overflow. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-04-11ARM: dts: omap: remove unneeded unit name for sound nodesJavier Martinez Canillas
This patch fixes the following DTC warning: "sound@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-02-29ARM: dts: DRA7: change address-cells and size-cellsLokesh Vutla
DRA7 SoC has the capability to support DDR memory upto 4GB. In order to represent this in memory dt node, the address-cells and size cells should be 2. So, changing the address-cells and size-cells to 2 and updating the memory nodes accordingly. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-02-26ARM: dts: dra7: Remove redundant nand propertyRoger Quadros
wait pin monitoring is not used for nand so it is pointless to have the gpmc,wait-monitoring-ns property. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-02-26ARM: dts: dra7: Fix NAND device nodesRoger Quadros
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-12-18ARM: dts: DRA72-EVM: Add regulator-allow-bypass property for ldo1 and ldo2Keerthy
Add regulator-allow-bypass property for ldo1 and ldo2. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-12-01ARM: dts: dra72-evm: Mark uart1 rxd as wakeup capableVignesh R
Uart1 rxd is wakeup capable on DRA72 EVM. Hence, mark rxd line as wakeup capable. This is similar to commit 66b0436977e2c ("ARM: dts: dra7-evm: Mark uart1 rxd as wakeup capable") for DRA74 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-11-30ARM: dts: dra72-evm: Use DRA7XX_CORE_IOPAD pinmux macroJavier Martinez Canillas
Use the pinmux IOPAD macro to define the register absolute physical address instead of the offset from the padconf base address. This makes the DTS easier to read since matches the addresses listed in the Technical Reference Manual. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-10-20ARM: dts: dra72-evm: remove cpsw gpio hogging and add mode-gpiosMugunthan V N
With the current implementation of GPIO hogging and with gpio-pcf857x is built as module, ethernet doesn't work on boot and doesn't throw any error/warning to user. Ethernet becomes operational when inserting gpio-pcf857x module, even this time there is no error/warning logs to user that ethernet is operational. When using with NFS rootfs and gpio-pcf857x as module, board doesn't boot as it doesn't get any ip address and doesn't throw any error/warning. To over come this, now cpsw driver tries to get mode-gpios. When gpio-pcf857x is built as module it will throw error, so that user can decide either to built in gpio-pcf857x to continue with nfs boot or choose alternate rootfs filesystem like sd/ramdisk. When using mmc/ramdisk as root fs, cpsw will probe defer and re-probes again when gpio-pcf857x module is inserted and ethernet becomes operational. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-10-12ARM: dts: dra7xx: am57xx: fix cd-gpios definition as per hardware design and ↵Mugunthan V N
dt binding docs As per mmc device tree binding documentation card detect gpio has to be active low signal. When a hardware is designed with active high card detect, gpio polarity has to be changed with cd-inverted dt property. In DRA74x, DRA72x and AM57xx EVMs the card detect gpio is designed as active low gpio. So correcting the dt card detect gpio definition. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-10-12ARM: dts: dra72-evm: Enable the system mailboxes 5 and 6Suman Anna
Enable the System Mailboxes 5 and 6 and the corresponding child sub-mailbox (IPC 3.x) nodes for the DRA72 EVM board. This is needed to enable communication with the respective remote processors IPU1, IPU2, and DSP1 from the MPU. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-10-12ARM: dts: dra72-evm: Audio supportPeter Ujfalusi
The board uses tlv320aic3106 codec connected to McASP3. The master clock for the codec and McASP3 is coming from ATL2. McASP3 is the master on the I2S bus. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-10-12ARM: dts: dra72-evm: Add gpio hog for vin6_sel_s0 to select audioPeter Ujfalusi
The GPIO expander's p1 on i2c5 bus 0x26 address is used for selecting between audio and VIN6 functionality. For VIN6 use an add on card is needed while audio is present on the board itself. Select the audio functionality over the VIN6 in the dts file. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-10-12ARM: dts: dra72-evm: Add fixed regulator representing DVDD supply for aic3106Peter Ujfalusi
The DVDD is supplied via TPS77018DBVT fixed regulator from evm_3v3 Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Darren Etheridge <detheridge@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-09-01Merge tag 'armsoc-dt' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
2015-08-05ARM: dts: dra72-evm: Fix spurious card insert/removal interruptKishon Vijay Abraham I
ldo1_reg in addition to being connected to the io lines is also connected to the card detect line. On card removal, omap_hsmmc driver does a regulator_disable causing card detect line to be pulled down. This raises a card insertion interrupt and once the MMC core detects there is no card inserted, it does a regulator disable which again raises a card insertion interrupt. This happens in a loop causing infinite MMC interrupts. Fix it by making ldo1_reg as always_on. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-08-05ARM: dts: dra72-evm: Set max clock frequency of MMC1 and MMC2Kishon Vijay Abraham I
MMC1 supports SDR104 and MMC2 supports HS200 both of which requires 192MHz clock. Set the maximum operating clock frequency to 192 MHz. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-08-05ARM: dts: dra72-evm: add evm_3v3_sd regulatorKishon Vijay Abraham I
Add a node for evm_3v3_sd using pcf which feeds on to mmc vdd. Update mapping for vmmc-supply and vmmc_aux-supply. evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-07-14ARM: dts: DRA72: switch to cpsw slave0 for ethernetVignesh R
On DRA72 EVM, cpsw slave1 is muxed with VIN2A, hence switch to cpsw slave0 for ethernet. Add gpio hog entry to pcf_gpio_21 in order to select cpsw slave0. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-07-12ARM: dts: dra7x-evm: Prevent glitch on DCAN1 pinmuxRoger Quadros
Driver core sets "default" pinmux on on probe and CAN driver sets "sleep" pinmux during register. This causes a small window where the CAN pins are in "default" state with the DCAN module being disabled. Change the "default" state to be like sleep so this glitch is avoided. Add a new "active" state that is used by the driver when CAN is actually active. Signed-off-by: Roger Quadros <rogerq@ti.com> Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2015-06-04arm/dts: dra72-evm.dts: add HDMITomi Valkeinen
DRA72 EVM has a HDMI output. This patch adds the device tree nodes required for HDMI. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: devicetree@vger.kernel.org Acked-by: Tony Lindgren <tony@atomide.com>
2015-04-22Merge tag 'armsoc-dt' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As always, this tends to be one of our bigger branches. There are lots of updates this release, but not that many jumps out as something that needs more detailed coverage. Some of the highlights are: - DTs for the new Annapurna Labs Alpine platform - more graphics DT pieces falling into place on Exynos, bridges, clocks. - plenty of DT updates for Qualcomm platforms for various IP blocks - some churn on Tegra due to switch-over to tool-generated pinctrl data - misc fixes and updates for Atmel at91 platforms - various DT updates to add IP block support on Broadcom's Cygnus platforms - more updates for Renesas platforms as DT support is added for various IP blocks (IPMMU, display, audio, etc)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (231 commits) ARM: dts: alpine: add internal pci Revert "ARM: dts: mt8135: Add pinctrl/GPIO/EINT node for mt8135." ARM: mvebu: use 0xf1000000 as internal registers on Armada 370 DB ARM: dts: qcom: Add idle state device nodes for 8064 ARM: dts: qcom: Add idle states device nodes for 8084 ARM: dts: qcom: Add idle states device nodes for 8974/8074 ARM: dts: qcom: Update power-controller device node for 8064 Krait CPUs ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs devicetree: bindings: Document qcom,idle-states devicetree: bindings: Update qcom,saw2 node bindings dt-bindings: Add #defines for MSM8916 clocks and resets arm: dts: qcom: Add LPASS Audio HW to IPQ8064 device tree arm: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes arm: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes arm: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974 arm: dts: qcom: Add LCC nodes arm: dts: qcom: Add TCSR support for MSM8960 arm: dts: qcom: Add TCSR support for MSM8660 arm: dts: qcom: Add TCSR support for IPQ8064 ...
2015-04-11Merge tag 'irqchip-core-4.1-3' of ↵Thomas Gleixner
git://git.infradead.org/users/jcooper/linux into irq/core irqchip core change for v4.1 (round 3) from Jason Cooper Purge the gic_arch_extn hacks and abuse by using the new stacked domains NOTE: Due to the nature of these changes, patches crossing subsystems have been kept together in their own branches. - tegra - Handle the LIC properly - omap - Convert crossbar to stacked domains - kill arm,routable-irqs in GIC binding - exynos - Convert PMU wakeup to stacked domains - shmobile, ux500, zynq (irq_set_wake branch) - Switch from abusing gic_arch_extn to using gic_set_irqchip_flags
2015-04-03Merge tag 'omap-for-v4.1/wl12xx-dt' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Merge "wireless wl12xx and omap device tree changes for v4.1" from Tony Lindgren: Wireless and omap changes to make wl12xx driver to use device tree data instead of platform data from Eliad Peller <eliad@wizery.com>: - Add device-tree support to the wlcore (wl12xx/wl18xx) driver. - Update the current users to use the bindings instead of pdata-quirks. - Finally, remove the deprecated wl12xx_platform_data struct Note that da850 board file code that still uses the platform data, but we have da850.dtsi that can be used instead. So it was decided that we should try to remove the wl12xx support from the da850 board file as suggested by Sekhar Nori <nsekhar@ti.com>. As it's the last patch in the series, the last patch can be simply reverted if needed. As this series touches quite a bit of arch code, it was suggested by Kalle Valo <kvalo@codeaurora.org> that the whole series should be merged via the arm-soc tree. * tag 'omap-for-v4.1/wl12xx-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: wlcore: remove wl12xx_platform_data ARM: dts: add wl12xx/wl18xx bindings wlcore: add device-tree support dt: bindings: add TI's wilink wireless device wl12xx: use frequency instead of enumerations for pdata clocks wlcore: set irq_trigger in board files instead of hiding behind a quirk + Linux 4.0-rc4 Signed-off-by: Olof Johansson <olof@lixom.net>
2015-03-17ARM: dts: dra7x-evm: beagle-x15: Fix USB PeripheralRoger Quadros
Now that we have EXTCON_USB_GPIO queued for v4.1, revert commit addfcde7c485 ("ARM: dts: dra7x-evm: beagle-x15: Fix USB Host") On these EVMs, the USB cable state has to be determined via the ID pin tied to a GPIO line. We use the gpio-usb-extcon driver to read the ID pin and the extcon framework to forward the USB cable state information to the USB driver so the controller can be configured in the right mode (host/peripheral). Gets USB peripheral mode to work on this EVM. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
2015-03-15irqchip: crossbar: Convert dra7 crossbar to stacked domainsMarc Zyngier
Support for the TI crossbar used on the DRA7 family of chips is implemented as an ugly hack on the side of the GIC. Converting it to stacked domains makes it slightly more palatable, as it results in a cleanup. Unfortunately, as the DT bindings failed to acknowledge the fact that this is actually yet another interrupt controller (the third, actually), we have yet another breakage. Oh well. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088629-15377-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-03-06ARM: dts: dra7x-evm: avoid possible contention while muxing on CAN linesRoger Quadros
DCAN1 RX and TX lines are internally pulled high according to [1]. While muxing between DCAN mode and SAFE mode we make sure that the same pull direction is set to minimize opposite pull contention during the switching window. [1] in DRA7 data manual, Ball characteristics table 4-2, DSIS colum shows the state driven to the peripheral input while in the deselcted mode. DSIS - De-Selected Input State. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-03-06ARM: dts: dra7x-evm: Don't use dcan1_rx.gpio1_15 in DCAN pinctrlRoger Quadros
Rev.F onwards ball G19 (dcan1_rx) is used as a GPIO for some other function so don't include it in DCAN pinctrl node. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-02-24ARM: dts: dra7x-evm: beagle-x15: Fix USB HostRoger Quadros
In commit 87517d26d888 ("ARM: dts: dra7-evm: Add extcon nodes for USB") we enabled Extcon USB gpio to tackle the USB ID pin and get peripheral mode to work. But the extcon-gpio-usb driver [1] didn't make it into v4.0 and this makes the USB driver defer probe indefinitely breaking USB Host functionality. As a temporary fix we remove the extcon handle from the USB controller and add it back when the extcon driver merges in v4.1. [1] - https://lkml.org/lkml/2015/2/2/187 Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-01-30ARM: dts: dra72-evm: Add extcon nodes for USBRoger Quadros
On this EVM, the USB cable state has to be determined via the ID pin tied to a GPIO line. We use the gpio-usb-extcon driver to read the ID pin and the extcon framework to forward the USB cable state information to the USB driver so the controller can be configured in the right mode (host/peripheral). Gets USB peripheral mode to work on this EVM. Signed-off-by: Roger Quadros <rogerq@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-01-20ARM: dts: dra72-evm: Add qspi deviceMugunthan V N
These add device tree entry for qspi device on dra72-evm. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-12-10ARM: dts: dra7-evm: Update SMPS7 (VDD_CORE) max voltage to match DMRavikumar Kattekola
As per the latest Data Manual, for newer samples, the nominal voltage required for VDD_CORE at OPP_NOM can be upto 1.06V which was 1.03V earlier. Update the regulator max voltage constraint for SMPS7, connected to VDD_CORE, to meet this requirement. Document reference: DRA74 Data Manual, SPRS857M - Dec 2012, Revised Oct 2014. DRA72 Data Manual, SPRS906G - Dec 2012, revised Oct 2014. Signed-off-by: Ravikumar Kattekola <rk@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-24ARM: dts: dra72-evm: Add CAN supportRoger Quadros
The board has 2 CAN ports but only the first one can be used. Enable the first CAN port. WAKEUP0 pin doesn't have INPUT enable bit so we just disable weak PULLs. The second CAN port cannot be used without hardware modification so we don't enable the second port. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-10ARM: dts: dra72x-evm: Enable CPSW and MDIOMugunthan V N
Adding CPSW phy-id, CPSW and MDIO pinmux configuration for active and sleep states and enable them in board evm dts file. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-10ARM: dts: dra72-evm: Add MMC nodesNishanth Menon
Add MMC1 and 2 nodes. MMC1 is SDcard and MMC2 is eMMC. NOTE on MMC1 card detect: Ideally, we should be using in-built SDCD support, but we dont have it yet. So, use the fact that control module of DRA7 is setup such that no matter what mode one configures it, GPIO option is always hardwired in - use GPIO mode for SDcard detection. [peter.ujfalusi@ti.com] The power line feeding the SD card is also used by other devices on the EVM. Use generic name instead of mmc2_3v3 so when other devices want to use the same regulator it will look a bit better. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-10ARM: dts: dra72-evm: Add power button nodeNishanth Menon
With Commit adff5962fdd2 ("Input: introduce palmas-pwrbutton"), we can now support tps power button as a event source - This is SW7 (PB/WAKE) on the J6-evm. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-10ARM: dts: dra72-evm: Provide explicit pinmux for TPS PMICNishanth Menon
Even thought sys_nirq1 is hardwired on the SoC for the pin, it is better to configure the pin to the required mux configuration. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-10ARM: dts: dra72-evm: Add regulator information to USB2 PHYsRoger Quadros
The ldo4_reg regulator provides power to the USB1 and USB2 High Speed PHYs. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-10ARM: dts: dra72-evm: Enable USB support for dra72-evm.George Cherian
Add USB data and pinctrl for USB. Signed-off-by: George Cherian <george.cherian@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-10ARM: dts: dra72-evm: Add NAND supportRoger Quadros
DRA72-evm has a 256MB 16-bit wide NAND chip. Add pinmux and NAND node. The NAND chips 'Chip select' and 'Write protect' can be controlled using DIP Switch SW5. To use NAND, the switch must be configured like so: SW5.1 (NAND_SELn) = ON (LOW) SW5.9 (GPMC_WPN) = OFF (HIGH) Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-08ARM: dts: dra72-evm: Add tps65917 PMIC nodeKeerthy J
DRA72x-evm uses TPS65917 PMIC. Add the node. NOTE: LDO2 is actually unused, but the usage if any is expected to be between 1.8 to 3.3v IO voltage. So define the node. NOTE: Interrupt used is crossbar number based. Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-09-08ARM: dts: dra72-evm: Enable I2C1 nodeKeerthy J
I2C1 bus is used for the following peripherals P8 connector (MLB) TLV320AIC3106 Audio codec J15 LCD header 24WC256 eeprom TMP102AIDRLT temperature sensor PCF8575 GPIO expander PCA9306 i2c voltage translator -> Goes to P9 for comm interface P2 expansion connector TPS65917 PMIC The slowest speed of all the peripherals seems to be 400KHz. Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-20 01:47:29 +0000