diff options
Diffstat (limited to 'include')
53 files changed, 2742 insertions, 20 deletions
diff --git a/include/crypto/if_alg.h b/include/crypto/if_alg.h index c1a8d4a41bb1..a3d6d09fbb55 100644 --- a/include/crypto/if_alg.h +++ b/include/crypto/if_alg.h @@ -46,6 +46,8 @@ struct af_alg_type { void *(*bind)(const char *name, u32 type, u32 mask); void (*release)(void *private); int (*setkey)(void *private, const u8 *key, unsigned int keylen); + int (*setkeytype)(void *private, const u8 *keytype, + unsigned int keylen); int (*accept)(void *private, struct sock *sk); int (*accept_nokey)(void *private, struct sock *sk); int (*setauthsize)(void *private, unsigned int authsize); diff --git a/include/crypto/skcipher.h b/include/crypto/skcipher.h index 26be16cc46e3..341673b478d0 100644 --- a/include/crypto/skcipher.h +++ b/include/crypto/skcipher.h @@ -37,6 +37,8 @@ struct skcipher_request { struct crypto_skcipher { int (*setkey)(struct crypto_skcipher *tfm, const u8 *key, unsigned int keylen); + int (*setkeytype)(struct crypto_skcipher *tfm, const u8 *key, + unsigned int keylen); int (*encrypt)(struct skcipher_request *req); int (*decrypt)(struct skcipher_request *req); @@ -409,6 +411,12 @@ static inline int crypto_sync_skcipher_setkey(struct crypto_sync_skcipher *tfm, return crypto_skcipher_setkey(&tfm->base, key, keylen); } +static inline int crypto_skcipher_setkeytype(struct crypto_skcipher *tfm, + const u8 *key, unsigned int keylen) +{ + return tfm->setkeytype(tfm, key, keylen); +} + static inline unsigned int crypto_skcipher_default_keysize( struct crypto_skcipher *tfm) { diff --git a/include/drm/drm_encoder_slave.h b/include/drm/drm_encoder_slave.h index a09864f6d684..4059e4486f84 100644 --- a/include/drm/drm_encoder_slave.h +++ b/include/drm/drm_encoder_slave.h @@ -27,6 +27,7 @@ #ifndef __DRM_ENCODER_SLAVE_H__ #define __DRM_ENCODER_SLAVE_H__ +#include <drm/drmP.h> #include <drm/drm_crtc.h> #include <drm/drm_encoder.h> @@ -159,6 +160,29 @@ static inline void drm_i2c_encoder_unregister(struct drm_i2c_encoder_driver *dri void drm_i2c_encoder_destroy(struct drm_encoder *encoder); +/** + * struct drm_platform_encoder_driver + * @platform_driver: platform device driver + * @encoder_init: callback to initialize the slave encoder + * + * Describes a device driver for an encoder connected to + * through a platform bus. In addition to the entry points in @platform_driver + * an @encoder_init function should be provided. It will be called to + * give the driver an opportunity to allocate any per-encoder data + * structures and to initialize the @slave_funcs and (optionally) + * @slave_priv members of @encoder. + */ +struct drm_platform_encoder_driver { + struct platform_driver platform_driver; + + int (*encoder_init)(struct platform_device *pdev, + struct drm_device *dev, + struct drm_encoder_slave *encoder); + +}; +#define to_drm_platform_encoder_driver(x) container_of((x), \ + struct drm_platform_encoder_driver, \ + platform_driver) /* * Wrapper fxns which can be plugged in to drm_encoder_helper_funcs: diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index b3d9d88ab290..4d66ba6be06d 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -122,7 +122,23 @@ struct drm_format_info { * drm_format_info_block_height() */ u8 block_h[3]; - + /** + * @pixels_per_macropixel: + * Number of pixels per macro-pixel (per plane). A macro-pixel is + * composed of multiple pixels, and there can be extra bits between + * pixels. This must be used along with @bytes_per_macropixel, only + * when single pixel size is not byte-aligned. In this case, @cpp + * is not valid and should be 0. + */ + u8 pixels_per_macropixel[3]; + /** + * @bytes_per_macropixel: + * Number of bytes per macro-pixel (per plane). A macro-pixel is + * composed of multiple pixels. The size of single macro-pixel should + * be byte-aligned. This should be used with @pixels_per_macropixel, + * and @cpp should be 0. + */ + u8 bytes_per_macropixel[3]; /** @hsub: Horizontal chroma subsampling factor */ u8 hsub; /** @vsub: Vertical chroma subsampling factor */ @@ -280,6 +296,8 @@ unsigned int drm_format_info_block_height(const struct drm_format_info *info, int plane); uint64_t drm_format_info_min_pitch(const struct drm_format_info *info, int plane, unsigned int buffer_width); +int drm_format_plane_width_bytes(const struct drm_format_info *info, + int plane, int width); const char *drm_get_format_name(uint32_t format, struct drm_format_name_buf *buf); #endif /* __DRM_FOURCC_H__ */ diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h new file mode 100644 index 000000000000..264d634d226e --- /dev/null +++ b/include/dt-bindings/clock/xlnx-versal-clk.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Xilinx Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_VERSAL_H +#define _DT_BINDINGS_CLK_VERSAL_H + +#define PMC_PLL 1 +#define APU_PLL 2 +#define RPU_PLL 3 +#define CPM_PLL 4 +#define NOC_PLL 5 +#define PLL_MAX 6 +#define PMC_PRESRC 7 +#define PMC_POSTCLK 8 +#define PMC_PLL_OUT 9 +#define PPLL 10 +#define NOC_PRESRC 11 +#define NOC_POSTCLK 12 +#define NOC_PLL_OUT 13 +#define NPLL 14 +#define APU_PRESRC 15 +#define APU_POSTCLK 16 +#define APU_PLL_OUT 17 +#define APLL 18 +#define RPU_PRESRC 19 +#define RPU_POSTCLK 20 +#define RPU_PLL_OUT 21 +#define RPLL 22 +#define CPM_PRESRC 23 +#define CPM_POSTCLK 24 +#define CPM_PLL_OUT 25 +#define CPLL 26 +#define PPLL_TO_XPD 27 +#define NPLL_TO_XPD 28 +#define APLL_TO_XPD 29 +#define RPLL_TO_XPD 30 +#define EFUSE_REF 31 +#define SYSMON_REF 32 +#define IRO_SUSPEND_REF 33 +#define USB_SUSPEND 34 +#define SWITCH_TIMEOUT 35 +#define RCLK_PMC 36 +#define RCLK_LPD 37 +#define WDT 38 +#define TTC0 39 +#define TTC1 40 +#define TTC2 41 +#define TTC3 42 +#define GEM_TSU 43 +#define GEM_TSU_LB 44 +#define MUXED_IRO_DIV2 45 +#define MUXED_IRO_DIV4 46 +#define PSM_REF 47 +#define GEM0_RX 48 +#define GEM0_TX 49 +#define GEM1_RX 50 +#define GEM1_TX 51 +#define CPM_CORE_REF 52 +#define CPM_LSBUS_REF 53 +#define CPM_DBG_REF 54 +#define CPM_AUX0_REF 55 +#define CPM_AUX1_REF 56 +#define QSPI_REF 57 +#define OSPI_REF 58 +#define SDIO0_REF 59 +#define SDIO1_REF 60 +#define PMC_LSBUS_REF 61 +#define I2C_REF 62 +#define TEST_PATTERN_REF 63 +#define DFT_OSC_REF 64 +#define PMC_PL0_REF 65 +#define PMC_PL1_REF 66 +#define PMC_PL2_REF 67 +#define PMC_PL3_REF 68 +#define CFU_REF 69 +#define SPARE_REF 70 +#define NPI_REF 71 +#define HSM0_REF 72 +#define HSM1_REF 73 +#define SD_DLL_REF 74 +#define FPD_TOP_SWITCH 75 +#define FPD_LSBUS 76 +#define ACPU 77 +#define DBG_TRACE 78 +#define DBG_FPD 79 +#define LPD_TOP_SWITCH 80 +#define ADMA 81 +#define LPD_LSBUS 82 +#define CPU_R5 83 +#define CPU_R5_CORE 84 +#define CPU_R5_OCM 85 +#define CPU_R5_OCM2 86 +#define IOU_SWITCH 87 +#define GEM0_REF 88 +#define GEM1_REF 89 +#define GEM_TSU_REF 90 +#define USB0_BUS_REF 91 +#define UART0_REF 92 +#define UART1_REF 93 +#define SPI0_REF 94 +#define SPI1_REF 95 +#define CAN0_REF 96 +#define CAN1_REF 97 +#define I2C0_REF 98 +#define I2C1_REF 99 +#define DBG_LPD 100 +#define TIMESTAMP_REF 101 +#define DBG_TSTMP 102 +#define CPM_TOPSW_REF 103 +#define USB3_DUAL_REF 104 +#define OUTCLK_MAX 105 +#define REF_CLK 106 +#define PL_ALT_REF_CLK 107 +#define MUXED_IRO 108 +#define PL_EXT 109 +#define PL_LB 110 +#define MIO_50_OR_51 111 +#define MIO_24_OR_25 112 + +#endif diff --git a/include/dt-bindings/drm/mipi-dsi.h b/include/dt-bindings/drm/mipi-dsi.h new file mode 100644 index 000000000000..c6f37ec661fe --- /dev/null +++ b/include/dt-bindings/drm/mipi-dsi.h @@ -0,0 +1,11 @@ +#ifndef __DT_BINDINGS_DRM__ +#define __DT_BINDINGS_DRM__ +/* + * MIPI DSI pixel formats as defined in the include/drm/drm_mipi_dsi.h" + */ +#define MIPI_DSI_FMT_RGB888 0 +#define MIPI_DSI_FMT_RGB666 1 +#define MIPI_DSI_FMT_RGB666_PACKED 2 +#define MIPI_DSI_FMT_RGB565 3 + +#endif /* _DT_BINDINGS_DRM__ */ diff --git a/include/dt-bindings/media/xilinx-vip.h b/include/dt-bindings/media/xilinx-vip.h index 94ed3edfcc70..beb50a7483bc 100644 --- a/include/dt-bindings/media/xilinx-vip.h +++ b/include/dt-bindings/media/xilinx-vip.h @@ -32,5 +32,11 @@ #define XVIP_VF_CUSTOM2 13 #define XVIP_VF_CUSTOM3 14 #define XVIP_VF_CUSTOM4 15 +#define XVIP_VF_VUY_422 16 +#define XVIP_VF_BGRX 17 +#define XVIP_VF_YUVX 18 +#define XVIP_VF_XBGR 19 +#define XVIP_VF_Y_GREY 20 +#define XVIP_VF_XRGB 21 #endif /* __DT_BINDINGS_MEDIA_XILINX_VIP_H__ */ diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index b6a1eaf1b339..f6bc83b66ae9 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -16,5 +16,7 @@ #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 +#define PHY_TYPE_DP 6 +#define PHY_TYPE_SGMII 7 #endif /* _DT_BINDINGS_PHY */ diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h new file mode 100644 index 000000000000..65522a1f032d --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -0,0 +1,36 @@ +/* + * MIO pin configuration defines for Xilinx ZynqMP + * + * Copyright (C) 2017 Xilinx, Inc. + * Author: Chirag Parekh <chirag.parekh@xilinx.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H +#define _DT_BINDINGS_PINCTRL_ZYNQMP_H + +/* Bit value for IO standards */ +#define IO_STANDARD_LVCMOS33 0 +#define IO_STANDARD_LVCMOS18 1 + +/* Bit values for Slew Rates */ +#define SLEW_RATE_FAST 0 +#define SLEW_RATE_SLOW 1 + +/* Bit values for Pin inputs */ +#define PIN_INPUT_TYPE_CMOS 0 +#define PIN_INPUT_TYPE_SCHMITT 1 + +/* Bit values for drive control*/ +#define DRIVE_STRENGTH_2MA 2 +#define DRIVE_STRENGTH_4MA 4 +#define DRIVE_STRENGTH_8MA 8 +#define DRIVE_STRENGTH_12MA 12 + +#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ diff --git a/include/dt-bindings/power/xlnx-versal-power.h b/include/dt-bindings/power/xlnx-versal-power.h new file mode 100644 index 000000000000..5ad85a1ef140 --- /dev/null +++ b/include/dt-bindings/power/xlnx-versal-power.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_VERSAL_POWER_H +#define _DT_BINDINGS_VERSAL_POWER_H + +#define PD_SWDT_FPD 0x18224029 +#define PD_USB_0 0x18224018 +#define PD_GEM_0 0x18224019 +#define PD_GEM_1 0x1822401a +#define PD_SPI_0 0x1822401b +#define PD_SPI_1 0x1822401c +#define PD_I2C_0 0x1822401d +#define PD_I2C_1 0x1822401e +#define PD_CAN_FD_0 0x1822401f +#define PD_CAN_FD_1 0x18224020 +#define PD_UART_0 0x18224021 +#define PD_UART_1 0x18224022 +#define PD_GPIO 0x18224023 +#define PD_TTC_0 0x18224024 +#define PD_TTC_1 0x18224025 +#define PD_TTC_2 0x18224026 +#define PD_TTC_3 0x18224027 +#define PD_OSPI 0x1822402a +#define PD_QSPI 0x1822402b +#define PD_SDIO_0 0x1822402e +#define PD_SDIO_1 0x1822402f +#define PD_RTC 0x18224034 +#define PD_ADMA_0 0x18224035 +#define PD_ADMA_1 0x18224036 +#define PD_ADMA_2 0x18224037 +#define PD_ADMA_3 0x18224038 +#define PD_ADMA_4 0x18224039 +#define PD_ADMA_5 0x1822403a +#define PD_ADMA_6 0x1822403b +#define PD_ADMA_7 0x1822403c + +#endif diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index bb6118f79784..f6525ba73eef 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -819,6 +819,7 @@ unsigned long clk_hw_get_flags(const struct clk_hw *hw); #define clk_hw_can_set_rate_parent(hw) \ (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT) +unsigned int clk_get_children(char *name); bool clk_hw_is_prepared(const struct clk_hw *hw); bool clk_hw_rate_is_protected(const struct clk_hw *hw); bool clk_hw_is_enabled(const struct clk_hw *hw); diff --git a/include/linux/clk/zynq.h b/include/linux/clk/zynq.h index a198dd9255a4..d1135756aedf 100644 --- a/include/linux/clk/zynq.h +++ b/include/linux/clk/zynq.h @@ -9,6 +9,10 @@ #include <linux/spinlock.h> +int zynq_clk_suspend_early(void); +void zynq_clk_resume_late(void); +void zynq_clk_topswitch_enable(void); +void zynq_clk_topswitch_disable(void); void zynq_clock_init(void); struct clk *clk_register_zynq_pll(const char *name, const char *parent, diff --git a/include/linux/crypto.h b/include/linux/crypto.h index 9cf8f3ce0e50..b630c97ac705 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -255,6 +255,8 @@ struct ablkcipher_alg { struct blkcipher_alg { int (*setkey)(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen); + int (*setkeytype)(struct crypto_tfm *tfm, const u8 *keytype, + unsigned int keylen); int (*encrypt)(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes); @@ -721,6 +723,8 @@ struct blkcipher_tfm { void *iv; int (*setkey)(struct crypto_tfm *tfm, const u8 *key, unsigned int keylen); + int (*setkeytype)(struct crypto_tfm *tfm, const u8 *key, + unsigned int keylen); int (*encrypt)(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes); int (*decrypt)(struct blkcipher_desc *desc, struct scatterlist *dst, @@ -1453,6 +1457,14 @@ static inline int crypto_blkcipher_setkey(struct crypto_blkcipher *tfm, key, keylen); } +static inline int crypto_blkcipher_setkeytype(struct crypto_blkcipher *tfm, + const u8 *key, + unsigned int keylen) +{ + return crypto_blkcipher_crt(tfm)->setkeytype(crypto_blkcipher_tfm(tfm), + key, keylen); +} + /** * crypto_blkcipher_encrypt() - encrypt plaintext * @desc: reference to the block cipher handle with meta data diff --git a/include/linux/dma/xilinx_frmbuf.h b/include/linux/dma/xilinx_frmbuf.h new file mode 100644 index 000000000000..a62b653ff87f --- /dev/null +++ b/include/linux/dma/xilinx_frmbuf.h @@ -0,0 +1,204 @@ +/* + * Xilinx Framebuffer DMA support header file + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __XILINX_FRMBUF_DMA_H +#define __XILINX_FRMBUF_DMA_H + +#include <linux/dmaengine.h> + +/* Modes to enable early callback */ +#define EARLY_CALLBACK BIT(1) /* To avoid first frame delay */ +#define EARLY_CALLBACK_LOW_LATENCY BIT(2) /* Low latency mode */ + +/** + * enum vid_frmwork_type - Linux video framework type + * @XDMA_DRM: fourcc is of type DRM + * @XDMA_V4L2: fourcc is of type V4L2 + */ +enum vid_frmwork_type { + XDMA_DRM = 0, + XDMA_V4L2, +}; + +/** + * enum operation_mode - FB IP control register field settings to select mode + * @DEFAULT : Use default mode, No explicit bit field settings required. + * @AUTO_RESTART : Use auto-restart mode by setting BIT(7) of control register. + */ +enum operation_mode { + DEFAULT = 0x0, + AUTO_RESTART = BIT(7), +}; + +#if IS_ENABLED(CONFIG_XILINX_FRMBUF) +/** + * xilinx_xdma_set_mode - Set operation mode for framebuffer IP + * @chan: dma channel instance + * @mode: Famebuffer IP operation mode. + * This routine is used when utilizing "video format aware" Xilinx DMA IP + * (such as Video Framebuffer Read or Video Framebuffer Write). This call + * must be made prior to dma_async_issue_pending(). This routine should be + * called by client driver to set the operation mode for framebuffer IP based + * upon the use-case, for e.g. for non-streaming usecases (like MEM2MEM) it's + * more appropriate to use default mode unlike streaming usecases where + * auto-restart mode is more suitable. + * + * auto-restart or free running mode. + */ +void xilinx_xdma_set_mode(struct dma_chan *chan, enum operation_mode mode); + +/** + * xilinx_xdma_drm_config - configure video format in video aware DMA + * @chan: dma channel instance + * @drm_fourcc: DRM fourcc code describing the memory layout of video data + * + * This routine is used when utilizing "video format aware" Xilinx DMA IP + * (such as Video Framebuffer Read or Video Framebuffer Write). This call + * must be made prior to dma_async_issue_pending() to establish the video + * data memory format within the hardware DMA. + */ +void xilinx_xdma_drm_config(struct dma_chan *chan, u32 drm_fourcc); + +/** + * xilinx_xdma_v4l2_config - configure video format in video aware DMA + * @chan: dma channel instance + * @v4l2_fourcc: V4L2 fourcc code describing the memory layout of video data + * + * This routine is used when utilizing "video format aware" Xilinx DMA IP + * (such as Video Framebuffer Read or Video Framebuffer Write). This call + * must be made prior to dma_async_issue_pending() to establish the video + * data memory format within the hardware DMA. + */ +void xilinx_xdma_v4l2_config(struct dma_chan *chan, u32 v4l2_fourcc); + +/** + * xilinx_xdma_get_drm_vid_fmts - obtain list of supported DRM mem formats + * @chan: dma channel instance + * @fmt_cnt: Output param - total count of supported DRM fourcc codes + * @fmts: Output param - pointer to array of DRM fourcc codes (not a copy) + * + * Return: a reference to an array of DRM fourcc codes supported by this + * instance of the Video Framebuffer Driver + */ +int xilinx_xdma_get_drm_vid_fmts(struct dma_chan *chan, u32 *fmt_cnt, + u32 **fmts); + +/** + * xilinx_xdma_get_v4l2_vid_fmts - obtain list of supported V4L2 mem formats + * @chan: dma channel instance + * @fmt_cnt: Output param - total count of supported V4L2 fourcc codes + * @fmts: Output param - pointer to array of V4L2 fourcc codes (not a copy) + * + * Return: a reference to an array of V4L2 fourcc codes supported by this + * instance of the Video Framebuffer Driver + */ +int xilinx_xdma_get_v4l2_vid_fmts(struct dma_chan *chan, u32 *fmt_cnt, + u32 **fmts); + +/** + * xilinx_xdma_get_fid - Get the Field ID of the buffer received. + * This function should be called from the callback function registered + * per descriptor in prep_interleaved. + * + * @chan: dma channel instance + * @async_tx: descriptor whose parent structure contains fid. + * @fid: Output param - Field ID of the buffer. 0 - even, 1 - odd. + * + * Return: 0 on success, -EINVAL in case of invalid chan + */ +int xilinx_xdma_get_fid(struct dma_chan *chan, + struct dma_async_tx_descriptor *async_tx, u32 *fid); + +/** + * xilinx_xdma_set_fid - Set the Field ID of the buffer to be transmitted + * @chan: dma channel instance + * @async_tx: dma async tx descriptor for the buffer + * @fid: Field ID of the buffer. 0 - even, 1 - odd. + * + * Return: 0 on success, -EINVAL in case of invalid chan + */ +int xilinx_xdma_set_fid(struct dma_chan *chan, + struct dma_async_tx_descriptor *async_tx, u32 fid); + +/** + * xilinx_xdma_get_earlycb - Get info if early callback has been enabled. + * + * @chan: dma channel instance + * @async_tx: descriptor whose parent structure contains fid. + * @earlycb: Output param - Early callback mode + * + * Return: 0 on success, -EINVAL in case of invalid chan + */ +int xilinx_xdma_get_earlycb(struct dma_chan *chan, + struct dma_async_tx_descriptor *async_tx, + u32 *earlycb); + +/** + * xilinx_xdma_set_earlycb - Enable/Disable early callback + * @chan: dma channel instance + * @async_tx: dma async tx descriptor for the buffer + * @earlycb: Enable early callback mode for descriptor + * + * Return: 0 on success, -EINVAL in case of invalid chan + */ +int xilinx_xdma_set_earlycb(struct dma_chan *chan, + struct dma_async_tx_descriptor *async_tx, + u32 earlycb); +#else +static inline void xilinx_xdma_drm_config(struct dma_chan *chan, u32 drm_fourcc) +{ } + +static inline void xilinx_xdma_v4l2_config(struct dma_chan *chan, + u32 v4l2_fourcc) +{ } + +static int xilinx_xdma_get_drm_vid_fmts(struct dma_chan *chan, u32 *fmt_cnt, + u32 **fmts) +{ + return -ENODEV; +} + +static int xilinx_xdma_get_v4l2_vid_fmts(struct dma_chan *chan, u32 *fmt_cnt, + u32 **fmts) +{ + return -ENODEV; +} + +static inline int xilinx_xdma_get_fid(struct dma_chan *chan, + struct dma_async_tx_descriptor *async_tx, + u32 *fid) +{ + return -ENODEV; +} + +static inline int xilinx_xdma_set_fid(struct dma_chan *chan, + struct dma_async_tx_descriptor *async_tx, + u32 fid) +{ + return -ENODEV; +} + +static inline int xilinx_xdma_get_earlycb(struct dma_chan *chan, + struct dma_async_tx_descriptor *atx, + u32 *earlycb) +{ + return -ENODEV; +} + +static inline int xilinx_xdma_set_earlycb(struct dma_chan *chan, + struct dma_async_tx_descriptor *atx, + u32 earlycb) +{ + return -ENODEV; +} +#endif + +#endif /*__XILINX_FRMBUF_DMA_H*/ diff --git a/include/linux/dma/xilinx_ps_pcie_dma.h b/include/linux/dma/xilinx_ps_pcie_dma.h new file mode 100644 index 000000000000..7c9912bd490e --- /dev/null +++ b/include/linux/dma/xilinx_ps_pcie_dma.h @@ -0,0 +1,69 @@ +/* + * Xilinx PS PCIe DMA Engine support header file + * + * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation + */ + +#ifndef __DMA_XILINX_PS_PCIE_H +#define __DMA_XILINX_PS_PCIE_H + +#include <linux/dma-mapping.h> +#include <linux/dmaengine.h> + +#define XLNX_PLATFORM_DRIVER_NAME "xlnx-platform-dma-driver" + +#define ZYNQMP_DMA_DEVID (0xD024) +#define ZYNQMP_RC_DMA_DEVID (0xD021) + +#define MAX_ALLOWED_CHANNELS_IN_HW 4 + +#define MAX_NUMBER_OF_CHANNELS MAX_ALLOWED_CHANNELS_IN_HW + +#define DEFAULT_DMA_QUEUES 4 +#define TWO_DMA_QUEUES 2 + +#define NUMBER_OF_BUFFER_DESCRIPTORS 1999 +#define MAX_DESCRIPTORS 65536 + +#define CHANNEL_COAELSE_COUNT 0 + +#define CHANNEL_POLL_TIMER_FREQUENCY 1000 /* in milli seconds */ + +#define PCIE_AXI_DIRECTION DMA_TO_DEVICE +#define AXI_PCIE_DIRECTION DMA_FROM_DEVICE + +/** + * struct BAR_PARAMS - PCIe Bar Parameters + * @BAR_PHYS_ADDR: PCIe BAR Physical address + * @BAR_LENGTH: Length of PCIe BAR + * @BAR_VIRT_ADDR: Virtual Address to access PCIe BAR + */ +struct BAR_PARAMS { + dma_addr_t BAR_PHYS_ADDR; /**< Base physical address of BAR memory */ + unsigned long BAR_LENGTH; /**< Length of BAR memory window */ + void *BAR_VIRT_ADDR; /**< Virtual Address of mapped BAR memory */ +}; + +/** + * struct ps_pcie_dma_channel_match - Match structure for dma clients + * @pci_vendorid: PCIe Vendor id of PS PCIe DMA device + * @pci_deviceid: PCIe Device id of PS PCIe DMA device + * @board_number: Unique id to identify individual device in a system + * @channel_number: Unique channel number of the device + * @direction: DMA channel direction + * @bar_params: Pointer to BAR_PARAMS for accessing application specific data + */ +struct ps_pcie_dma_channel_match { + u16 pci_vendorid; + u16 pci_deviceid; + u16 board_number; + u16 channel_number; + enum dma_data_direction direction; + struct BAR_PARAMS *bar_params; +}; + +#endif diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index fa3e8f91b3f5..a187671f695d 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -56,6 +56,7 @@ enum dma_transaction_type { DMA_MEMSET, DMA_MEMSET_SG, DMA_INTERRUPT, + DMA_SG, DMA_PRIVATE, DMA_ASYNC_TX, DMA_SLAVE, @@ -775,6 +776,11 @@ struct dma_device { unsigned int nents, int value, unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( struct dma_chan *chan, unsigned long flags); + struct dma_async_tx_descriptor *(*device_prep_dma_sg)( + struct dma_chan *chan, + struct scatterlist *dst_sg, unsigned int dst_nents, + struct scatterlist *src_sg, unsigned int src_nents, + unsigned long flags); struct dma_async_tx_descriptor *(*device_prep_slave_sg)( struct dma_chan *chan, struct scatterlist *sgl, @@ -904,6 +910,19 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy( len, flags); } +static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg( + struct dma_chan *chan, + struct scatterlist *dst_sg, unsigned int dst_nents, + struct scatterlist *src_sg, unsigned int src_nents, + unsigned long flags) +{ + if (!chan || !chan->device || !chan->device->device_prep_dma_sg) + return NULL; + + return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents, + src_sg, src_nents, flags); +} + /** * dmaengine_terminate_all() - Terminate all active DMA transfers * @chan: The channel for which to terminate the transfers diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 1262ea6a1f4b..578c28ac5d20 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -13,6 +13,8 @@ #ifndef __FIRMWARE_ZYNQMP_H__ #define __FIRMWARE_ZYNQMP_H__ +#include <linux/device.h> + #define ZYNQMP_PM_VERSION_MAJOR 1 #define ZYNQMP_PM_VERSION_MINOR 0 @@ -27,20 +29,35 @@ /* SMC SIP service Call Function Identifier Prefix */ #define PM_SIP_SVC 0xC2000000 + +/* ATF only commands */ #define PM_GET_TRUSTZONE_VERSION 0xa03 #define PM_SET_SUSPEND_MODE 0xa02 #define GET_CALLBACK_DATA 0xa01 +/* Loader commands */ +#define PM_LOAD_PDI 0x701 + /* Number of 32bits values in payload */ #define PAYLOAD_ARG_CNT 4U /* Number of arguments for a callback */ -#define CB_ARG_CNT 4 +#define CB_ARG_CNT 4 /* Payload size (consists of callback API ID + arguments) */ -#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1) +#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1) -#define ZYNQMP_PM_MAX_QOS 100U +#define ZYNQMP_PM_MAX_LATENCY (~0U) +#define ZYNQMP_PM_MAX_QOS 100U + +/* Usage status, returned by PmGetNodeStatus */ +#define PM_USAGE_NO_MASTER 0x0U +#define PM_USAGE_CURRENT_MASTER 0x1U +#define PM_USAGE_OTHER_MASTER 0x2U +#define PM_USAGE_BOTH_MASTERS (PM_USAGE_CURRENT_MASTER | \ + PM_USAGE_OTHER_MASTER) + +#define GSS_NUM_REGS (4) /* Node capabilities */ #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U @@ -56,19 +73,54 @@ #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) +/* Feature check status */ +#define PM_FEATURE_INVALID -1 +#define PM_FEATURE_UNCHECKED 0 + enum pm_api_id { PM_GET_API_VERSION = 1, - PM_REQUEST_NODE = 13, + PM_SET_CONFIGURATION, + PM_GET_NODE_STATUS, + PM_GET_OPERATING_CHARACTERISTIC, + PM_REGISTER_NOTIFIER, + /* API for suspending of PUs: */ + PM_REQUEST_SUSPEND, + PM_SELF_SUSPEND, + PM_FORCE_POWERDOWN, + PM_ABORT_SUSPEND, + PM_REQUEST_WAKEUP, + PM_SET_WAKEUP_SOURCE, + PM_SYSTEM_SHUTDOWN, + /* API for managing PM slaves: */ + PM_REQUEST_NODE, PM_RELEASE_NODE, PM_SET_REQUIREMENT, - PM_RESET_ASSERT = 17, + PM_SET_MAX_LATENCY, + /* Direct control API functions: */ + PM_RESET_ASSERT, PM_RESET_GET_STATUS, - PM_PM_INIT_FINALIZE = 21, + PM_MMIO_WRITE, + PM_MMIO_READ, + PM_PM_INIT_FINALIZE, PM_FPGA_LOAD, PM_FPGA_GET_STATUS, PM_GET_CHIPID = 24, - PM_IOCTL = 34, + /* ID 25 is been used by U-boot to process secure boot images */ + /* Secure library generic API functions */ + PM_SECURE_SHA = 26, + PM_SECURE_RSA, + /* Pin control API functions */ + PM_PINCTRL_REQUEST, + PM_PINCTRL_RELEASE, + PM_PINCTRL_GET_FUNCTION, + PM_PINCTRL_SET_FUNCTION, + PM_PINCTRL_CONFIG_PARAM_GET, + PM_PINCTRL_CONFIG_PARAM_SET, + /* PM IOCTL API */ + PM_IOCTL, + /* API to query information from firmware */ PM_QUERY_DATA, + /* Clock control API functions */ PM_CLOCK_ENABLE, PM_CLOCK_DISABLE, PM_CLOCK_GETSTATE, @@ -78,24 +130,52 @@ enum pm_api_id { PM_CLOCK_GETRATE, PM_CLOCK_SETPARENT, PM_CLOCK_GETPARENT, + PM_SECURE_IMAGE, + PM_FPGA_READ = 46, + PM_SECURE_AES, + /* PM_REGISTER_ACCESS API */ + PM_REGISTER_ACCESS = 52, + PM_EFUSE_ACCESS, + PM_FEATURE_CHECK = 63, + PM_API_MAX, }; /* PMU-FW return status codes */ enum pm_ret_status { XST_PM_SUCCESS = 0, + XST_PM_NO_FEATURE = 19, XST_PM_INTERNAL = 2000, XST_PM_CONFLICT, XST_PM_NO_ACCESS, XST_PM_INVALID_NODE, XST_PM_DOUBLE_REQ, XST_PM_ABORT_SUSPEND, + XST_PM_MULT_USER = 2008, }; enum pm_ioctl_id { - IOCTL_SET_PLL_FRAC_MODE = 8, + IOCTL_GET_RPU_OPER_MODE, + IOCTL_SET_RPU_OPER_MODE, + IOCTL_RPU_BOOT_ADDR_CONFIG, + IOCTL_TCM_COMB_CONFIG, + IOCTL_SET_TAPDELAY_BYPASS, + IOCTL_SET_SGMII_MODE, + IOCTL_SD_DLL_RESET, + IOCTL_SET_SD_TAPDELAY, + /* Ioctl for clock driver */ + IOCTL_SET_PLL_FRAC_MODE, IOCTL_GET_PLL_FRAC_MODE, IOCTL_SET_PLL_FRAC_DATA, IOCTL_GET_PLL_FRAC_DATA, + IOCTL_WRITE_GGS, + IOCTL_READ_GGS, + IOCTL_WRITE_PGGS, + IOCTL_READ_PGGS, + /* IOCTL for ULPI reset */ + IOCTL_ULPI_RESET, + /* Set healthy bit value*/ + IOCTL_SET_BOOT_HEALTH_STATUS, + IOCTL_AFI, }; enum pm_query_id { @@ -105,7 +185,14 @@ enum pm_query_id { PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS, PM_QID_CLOCK_GET_PARENTS, PM_QID_CLOCK_GET_ATTRIBUTES, - PM_QID_CLOCK_GET_NUM_CLOCKS = 12, + PM_QID_PINCTRL_GET_NUM_PINS, + PM_QID_PINCTRL_GET_NUM_FUNCTIONS, + PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS, + PM_QID_PINCTRL_GET_FUNCTION_NAME, + PM_QID_PINCTRL_GET_FUNCTION_GROUPS, + PM_QID_PINCTRL_GET_PIN_GROUPS, + PM_QID_CLOCK_GET_NUM_CLOCKS, + PM_QID_CLOCK_GET_MAX_DIVISOR, }; enum zynqmp_pm_reset_action { @@ -239,6 +326,13 @@ enum zynqmp_pm_reset { ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 }; +enum zynqmp_pm_abort_reason { + ZYNQMP_PM_ABORT_REASON_WAKEUP_EVENT = 100, + ZYNQMP_PM_ABORT_REASON_POWER_UNIT_BUSY, + ZYNQMP_PM_ABORT_REASON_NO_POWERDOWN, + ZYNQMP_PM_ABORT_REASON_UNKNOWN, +}; + enum zynqmp_pm_suspend_reason { SUSPEND_POWER_REQUEST = 201, SUSPEND_ALERT, @@ -251,6 +345,191 @@ enum zynqmp_pm_request_ack { ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING, }; +enum zynqmp_pm_opchar_type { + ZYNQMP_PM_OPERATING_CHARACTERISTIC_POWER = 1, + ZYNQMP_PM_OPERATING_CHARACTERISTIC_ENERGY, + ZYNQMP_PM_OPERATING_CHARACTERISTIC_TEMPERATURE, +}; + +enum zynqmp_pm_shutdown_type { + ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN, + ZYNQMP_PM_SHUTDOWN_TYPE_RESET, + ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY, +}; + +enum zynqmp_pm_shutdown_subtype { + ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM, + ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY, + ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM, +}; + +enum pm_node_id { + NODE_UNKNOWN = 0, + NODE_APU, + NODE_APU_0, + NODE_APU_1, + NODE_APU_2, + NODE_APU_3, + NODE_RPU, + NODE_RPU_0, + NODE_RPU_1, + NODE_PLD, + NODE_FPD, + NODE_OCM_BANK_0, + NODE_OCM_BANK_1, + NODE_OCM_BANK_2, + NODE_OCM_BANK_3, + NODE_TCM_0_A, + NODE_TCM_0_B, + NODE_TCM_1_A, + NODE_TCM_1_B, + NODE_L2, + NODE_GPU_PP_0, + NODE_GPU_PP_1, + NODE_USB_0, + NODE_USB_1, + NODE_TTC_0, + NODE_TTC_1, + NODE_TTC_2, + NODE_TTC_3, + NODE_SATA, + NODE_ETH_0, + NODE_ETH_1, + NODE_ETH_2, + NODE_ETH_3, + NODE_UART_0, + NODE_UART_1, + NODE_SPI_0, + NODE_SPI_1, + NODE_I2C_0, + NODE_I2C_1, + NODE_SD_0, + NODE_SD_1, + NODE_DP, + NODE_GDMA, + NODE_ADMA, + NODE_NAND, + NODE_QSPI, + NODE_GPIO, + NODE_CAN_0, + NODE_CAN_1, + NODE_EXTERN, + NODE_APLL, + NODE_VPLL, + NODE_DPLL, + NODE_RPLL, + NODE_IOPLL, + NODE_DDR, + NODE_IPI_APU, + NODE_IPI_RPU_0, + NODE_GPU, + NODE_PCIE, + NODE_PCAP, + NODE_RTC, + NODE_LPD, + NODE_VCU, + NODE_IPI_RPU_1, + NODE_IPI_PL_0, + NODE_IPI_PL_1, + NODE_IPI_PL_2, + NODE_IPI_PL_3, + NODE_PL, + NODE_GEM_TSU, + NODE_SWDT_0, + NODE_SWDT_1, + NODE_CSU, + NODE_PJTAG, + NODE_TRACE, + NODE_TESTSCAN, + NODE_PMU, + NODE_MAX, +}; + +enum pm_pinctrl_config_param { + PM_PINCTRL_CONFIG_SLEW_RATE, + PM_PINCTRL_CONFIG_BIAS_STATUS, + PM_PINCTRL_CONFIG_PULL_CTRL, + PM_PINCTRL_CONFIG_SCHMITT_CMOS, + PM_PINCTRL_CONFIG_DRIVE_STRENGTH, + PM_PINCTRL_CONFIG_VOLTAGE_STATUS, + PM_PINCTRL_CONFIG_MAX, +}; + +enum pm_pinctrl_slew_rate { + PM_PINCTRL_SLEW_RATE_FAST, + PM_PINCTRL_SLEW_RATE_SLOW, +}; + +enum pm_pinctrl_bias_status { + PM_PINCTRL_BIAS_DISABLE, + PM_PINCTRL_BIAS_ENABLE, +}; + +enum pm_pinctrl_pull_ctrl { + PM_PINCTRL_BIAS_PULL_DOWN, + PM_PINCTRL_BIAS_PULL_UP, +}; + +enum pm_pinctrl_schmitt_cmos { + PM_PINCTRL_INPUT_TYPE_CMOS, + PM_PINCTRL_INPUT_TYPE_SCHMITT, +}; + +enum pm_pinctrl_drive_strength { + PM_PINCTRL_DRIVE_STRENGTH_2MA, + PM_PINCTRL_DRIVE_STRENGTH_4MA, + PM_PINCTRL_DRIVE_STRENGTH_8MA, + PM_PINCTRL_DRIVE_STRENGTH_12MA, +}; + +enum rpu_oper_mode { + PM_RPU_MODE_LOCKSTEP, + PM_RPU_MODE_SPLIT, +}; + +enum rpu_boot_mem { + PM_RPU_BOOTMEM_LOVEC, + PM_RPU_BOOTMEM_HIVEC, +}; + +enum rpu_tcm_comb { + PM_RPU_TCM_SPLIT, + PM_RPU_TCM_COMB, +}; + +enum tap_delay_signal_type { + PM_TAPDELAY_NAND_DQS_IN, + PM_TAPDELAY_NAND_DQS_OUT, + PM_TAPDELAY_QSPI, + PM_TAPDELAY_MAX, +}; + +enum tap_delay_bypass_ctrl { + PM_TAPDELAY_BYPASS_DISABLE, + PM_TAPDELAY_BYPASS_ENABLE, +}; + +enum sgmii_mode { + PM_SGMII_DISABLE, + PM_SGMII_ENABLE, +}; + +enum tap_delay_type { + PM_TAPDELAY_INPUT, + PM_TAPDELAY_OUTPUT, +}; + +enum dll_reset_type { + PM_DLL_RESET_ASSERT, + PM_DLL_RESET_RELEASE, + PM_DLL_RESET_PULSE, +}; + +enum pm_register_access_id { + CONFIG_REG_WRITE, + CONFIG_REG_READ, +}; + /** * struct zynqmp_pm_query_data - PM query data * @qid: query ID @@ -270,6 +549,8 @@ struct zynqmp_eemi_ops { int (*get_chipid)(u32 *idcode, u32 *version); int (*fpga_load)(const u64 address, const u32 size, const u32 flags); int (*fpga_get_status)(u32 *value); + int (*fpga_read)(const u32 reg_numframes, const u64 phys_address, + u32 readback_type, u32 *value); int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out); int (*clock_enable)(u32 clock_id); int (*clock_disable)(u32 clock_id); @@ -295,11 +576,48 @@ struct zynqmp_eemi_ops { const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack); + int (*sha_hash)(const u64 address, const u32 size, const u32 flags); + int (*rsa)(const u64 address, const u32 size, const u32 flags); + int (*request_suspend)(const u32 node, + const enum zynqmp_pm_request_ack ack, + const u32 latency, + const u32 state); + int (*force_powerdown)(const u32 target, + const enum zynqmp_pm_request_ack ack); + int (*request_wakeup)(const u32 node, + const bool set_addr, + const u64 address, + const enum zynqmp_pm_request_ack ack); + int (*set_wakeup_source)(const u32 target, + const u32 wakeup_node, + const u32 enable); + int (*system_shutdown)(const u32 type, const u32 subtype); + int (*set_max_latency)(const u32 node, const u32 latency); + int (*set_configuration)(const u32 physical_addr); + int (*get_node_status)(const u32 node, u32 *const status, + u32 *const requirements, u32 *const usage); + int (*get_operating_characteristic)(const u32 node, + const enum zynqmp_pm_opchar_type + type, u32 *const result); + int (*pinctrl_request)(const u32 pin); + int (*pinctrl_release)(const u32 pin); + int (*pinctrl_get_function)(const u32 pin, u32 *id); + int (*pinctrl_set_function)(const u32 pin, const u32 id); + int (*pinctrl_get_config)(const u32 pin, const u32 param, u32 *value); + int (*pinctrl_set_config)(const u32 pin, const u32 param, u32 value); + int (*register_access)(u32 register_access_id, u32 address, + u32 mask, u32 value, u32 *out); + int (*aes)(const u64 address, u32 *out); + int (*efuse_access)(const u64 address, u32 *out); + int (*secure_image)(const u64 src_addr, u64 key_addr, u64 *dst); + int (*pdi_load)(const u32 src, const u64 address); }; int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); +int zynqmp_pm_ggs_init(struct kobject *parent_kobj); + #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP) const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void); #else diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index e8ca62b2cb5b..985ede34330b 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -11,6 +11,9 @@ #include <linux/mutex.h> #include <linux/platform_device.h> +#define ENCRYPTED_KEY_LEN 64 /* Bytes */ +#define ENCRYPTED_IV_LEN 24 /* Bytes */ + struct fpga_manager; struct sg_table; @@ -73,7 +76,6 @@ enum fpga_mgr_states { #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4) - /** * struct fpga_image_info - information specific to a FPGA image * @flags: boolean flags as defined above @@ -82,6 +84,8 @@ enum fpga_mgr_states { * @config_complete_timeout_us: maximum time for FPGA to switch to operating * status in the write_complete op. * @firmware_name: name of FPGA image firmware file + * @key: key value useful for Encrypted Bitstream loading to read the userkey + * @iv: iv (or) initialization vector is useful for Encrypted Bitstream loading * @sgt: scatter/gather table containing FPGA image * @buf: contiguous buffer containing FPGA image * @count: size of buf @@ -95,6 +99,8 @@ struct fpga_image_info { u32 disable_timeout_us; u32 config_complete_timeout_us; char *firmware_name; + char key[ENCRYPTED_KEY_LEN]; + char iv[ENCRYPTED_IV_LEN]; struct sg_table *sgt; const char *buf; size_t count; @@ -114,6 +120,7 @@ struct fpga_image_info { * @write: write count bytes of configuration data to the FPGA * @write_sg: write the scatter list of configuration data to the FPGA * @write_complete: set FPGA to operating state after writing is done + * @read: optional: read FPGA configuration information * @fpga_remove: optional: Set FPGA into a specific state during driver remove * @groups: optional attribute groups. * @@ -132,6 +139,7 @@ struct fpga_manager_ops { int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); int (*write_complete)(struct fpga_manager *mgr, struct fpga_image_info *info); + int (*read)(struct fpga_manager *mgr, struct seq_file *s); void (*fpga_remove)(struct fpga_manager *mgr); const struct attribute_group **groups; }; @@ -157,21 +165,31 @@ struct fpga_compat_id { /** * struct fpga_manager - fpga manager structure * @name: name of low level fpga manager + * @flags: flags determines the type of Bitstream + * @key: key value useful for Encrypted Bitstream loading to read the userkey + * @iv: iv (or) initialization vector is useful for Encrypted Bitstream loading * @dev: fpga manager device * @ref_mutex: only allows one reference to fpga manager * @state: state of fpga manager * @compat_id: FPGA manager id for compatibility check. * @mops: pointer to struct of fpga manager ops * @priv: low level driver private date + * @dir: debugfs image directory */ struct fpga_manager { const char *name; + long int flags; + char key[ENCRYPTED_KEY_LEN]; + char iv[ENCRYPTED_IV_LEN]; struct device dev; struct mutex ref_mutex; enum fpga_mgr_states state; struct fpga_compat_id *compat_id; const struct fpga_manager_ops *mops; void *priv; +#ifdef CONFIG_FPGA_MGR_DEBUG_FS + struct dentry *dir; +#endif }; #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev) diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 316087da1d09..8013314c82f9 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -134,6 +134,9 @@ struct gic_chip_data; void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); int gic_cpu_if_down(unsigned int gic_nr); +void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); + +void gic_set_cpu(unsigned int cpu, unsigned int irq); void gic_cpu_save(struct gic_chip_data *gic); void gic_cpu_restore(struct gic_chip_data *gic); void gic_dist_save(struct gic_chip_data *gic); diff --git a/include/linux/mailbox/zynqmp-ipi-message.h b/include/linux/mailbox/zynqmp-ipi-message.h index 9542b41eacfd..d9f0a7471b51 100644 --- a/include/linux/mailbox/zynqmp-ipi-message.h +++ b/include/linux/mailbox/zynqmp-ipi-message.h @@ -3,6 +3,9 @@ #ifndef _LINUX_ZYNQMP_IPI_MESSAGE_H_ #define _LINUX_ZYNQMP_IPI_MESSAGE_H_ +/* IPI buffer MAX length */ +#define IPI_BUF_LEN_MAX 32U + /** * struct zynqmp_ipi_message - ZynqMP IPI message structure * @len: Length of message diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 936a3fdb48b5..0341b38c152d 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -72,7 +72,8 @@ struct mtd_oob_ops { }; #define MTD_MAX_OOBFREE_ENTRIES_LARGE 32 -#define MTD_MAX_ECCPOS_ENTRIES_LARGE 640 +#define MTD_MAX_ECCPOS_ENTRIES_LARGE 1260 + /** * struct mtd_oob_region - oob region definition * @offset: region offset diff --git a/include/linux/mtd/onfi.h b/include/linux/mtd/onfi.h index 339ac798568e..0837ab74b2e7 100644 --- a/include/linux/mtd/onfi.h +++ b/include/linux/mtd/onfi.h @@ -161,8 +161,10 @@ struct onfi_ext_param_page { * @tR: Page read time * @tCCS: Change column setup time * @async_timing_mode: Supported asynchronous timing mode + * @src_sync_timing_mode: Supported synchronous timing mode * @vendor_revision: Vendor specific revision number * @vendor: Vendor specific data + * @jedec_id: Jedec ID of nand flash device */ struct onfi_params { int version; @@ -171,8 +173,10 @@ struct onfi_params { u16 tR; u16 tCCS; u16 async_timing_mode; + u16 src_sync_timing_mode; u16 vendor_revision; u8 vendor[88]; + u8 jedec_id; }; #endif /* __LINUX_MTD_ONFI_H */ diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index ac3884a28dea..08437edb1a42 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -438,6 +438,7 @@ struct nand_ecc_ctrl { * @tWHR_min: WE# high to RE# low * @tWP_min: WE# pulse width * @tWW_min: WP# transition to WE# low + * @mode: sdr timing mode value */ struct nand_sdr_timings { u64 tBERS_max; @@ -478,6 +479,7 @@ struct nand_sdr_timings { u32 tWHR_min; u32 tWP_min; u32 tWW_min; + u8 mode; }; /** @@ -1369,4 +1371,13 @@ static inline void *nand_get_data_buf(struct nand_chip *chip) return chip->data_buf; } +/* return the supported synchronous timing mode. */ +static inline int onfi_get_sync_timing_mode(struct nand_chip *chip) +{ + if (!chip->parameters.onfi) + return ONFI_TIMING_MODE_UNKNOWN; + + return le16_to_cpu(chip->parameters.onfi->src_sync_timing_mode); +} + #endif /* __LINUX_MTD_RAWNAND_H */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 9f57cdfcc93d..2856030ff94a 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -25,6 +25,7 @@ #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ +#define SNOR_MFR_ISSI CFI_MFR_PMC /* * Note on opcode nomenclature: some opcodes have a format like @@ -98,6 +99,8 @@ #define SPINOR_OP_WRDI 0x04 /* Write disable */ #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */ +#define GLOBAL_BLKPROT_UNLK 0x98 /* Clear global write protection bits */ + /* Used for S3AN flashes only */ #define SPINOR_OP_XSE 0x50 /* Sector erase */ #define SPINOR_OP_XPP 0x82 /* Page program */ @@ -106,13 +109,13 @@ #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */ #define XSR_RDY BIT(7) /* Ready */ - /* Used for Macronix and Winbond flashes. */ #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ /* Used for Spansion flashes only. */ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ +#define SPINOR_OP_BRRD 0x16 /* Bank register read */ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ /* Used for Micron flashes only. */ @@ -126,8 +129,17 @@ #define SR_BP0 BIT(2) /* Block protect 0 */ #define SR_BP1 BIT(3) /* Block protect 1 */ #define SR_BP2 BIT(4) /* Block protect 2 */ +#define SR_BP_BIT_OFFSET 2 /* Offset to Block protect 0 */ +#define SR_BP_BIT_MASK (SR_BP2 | SR_BP1 | SR_BP0) + #define SR_TB BIT(5) /* Top/Bottom protect */ #define SR_SRWD BIT(7) /* SR write protect */ +#define SR_BP3 0x40 +/* Bit to determine whether protection starts from top or bottom */ +#define SR_BP_TB 0x20 +#define BP_BITS_FROM_SR(sr) (((sr) & SR_BP_BIT_MASK) >> SR_BP_BIT_OFFSET) +#define M25P_MAX_LOCKABLE_SECTORS 64 + /* Spansion/Cypress specific status bits */ #define SR_E_ERR BIT(5) #define SR_P_ERR BIT(6) @@ -146,6 +158,16 @@ /* Configuration Register bits. */ #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */ +/* Extended/Bank Address Register bits */ +#define EAR_SEGMENT_MASK 0x7 /* 128 Mb segment mask */ + +enum read_mode { + SPI_NOR_NORMAL = 0, + SPI_NOR_FAST, + SPI_NOR_DUAL, + SPI_NOR_QUAD, +}; + /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7) @@ -382,6 +404,7 @@ struct spi_nor { struct mtd_info mtd; struct mutex lock; struct device *dev; + struct spi_device *spi; const struct flash_info *info; u32 page_size; u8 addr_width; @@ -389,13 +412,22 @@ struct spi_nor { u8 read_opcode; u8 read_dummy; u8 program_opcode; + enum read_mode flash_read; + u32 jedec_id; + u16 curbank; + u16 n_sectors; + u32 sector_size; enum spi_nor_protocol read_proto; enum spi_nor_protocol write_proto; enum spi_nor_protocol reg_proto; bool sst_write_second; + bool shift; + bool isparallel; + bool isstacked; u32 flags; u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE]; struct spi_nor_erase_map erase_map; + bool is_lock; int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops); void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); @@ -536,6 +568,15 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, const struct spi_nor_hwcaps *hwcaps); /** + * spi_nor_shutdown() - prepare for reboot + * @nor: the spi_nor structure + * + * The drivers can use this fuction to get the address back to + * 0 as will be required for a ROM boot. + */ +void spi_nor_shutdown(struct spi_nor *nor); + +/** * spi_nor_restore_addr_mode() - restore the status of SPI NOR * @nor: the spi_nor structure */ diff --git a/include/linux/of.h b/include/linux/of.h index 0cf857012f11..682295399fbb 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -1346,6 +1346,8 @@ enum of_reconfig_change { }; #ifdef CONFIG_OF_DYNAMIC +#include <linux/slab.h> + extern int of_reconfig_notifier_register(struct notifier_block *); extern int of_reconfig_notifier_unregister(struct notifier_block *); extern int of_reconfig_notify(unsigned long, struct of_reconfig_data *rd); @@ -1389,6 +1391,23 @@ static inline int of_changeset_update_property(struct of_changeset *ocs, { return of_changeset_action(ocs, OF_RECONFIG_UPDATE_PROPERTY, np, prop); } + +struct device_node *of_changeset_create_device_nodev( + struct of_changeset *ocs, struct device_node *parent, + const char *fmt, va_list vargs); + +__printf(3, 4) struct device_node * +of_changeset_create_device_node(struct of_changeset *ocs, + struct device_node *parent, const char *fmt, ...); + +int __of_changeset_add_update_property_copy(struct of_changeset *ocs, + struct device_node *np, const char *name, const void *value, + int length, bool update); + +int __of_changeset_add_update_property_string_list( + struct of_changeset *ocs, struct device_node *np, + const char *name, const char **strs, int count, bool update); + #else /* CONFIG_OF_DYNAMIC */ static inline int of_reconfig_notifier_register(struct notifier_block *nb) { @@ -1408,8 +1427,322 @@ static inline int of_reconfig_get_state_change(unsigned long action, { return -EINVAL; } + +static inline struct device_node *of_changeset_create_device_nodev( + struct of_changeset *ocs, struct device_node *parent, + const char *fmt, va_list vargs) +{ + return ERR_PTR(-EINVAL); +} + +static inline __printf(3, 4) struct device_node * +of_changeset_create_device_node(struct of_changeset *ocs, + struct device_node *parent, const char *fmt, ...) +{ + return ERR_PTR(-EINVAL); +} + +static inline int __of_changeset_add_update_property_copy( + struct of_changeset *ocs, struct device_node *np, + const char *name, const void *value, int length, bool update) +{ + return -EINVAL; +} + +static inline __printf(4, 5) int of_changeset_add_property_stringf( + struct of_changeset *ocs, struct device_node *np, + const char *name, const char *fmt, ...) +{ + return -EINVAL; +} + +static inline int of_changeset_update_property_stringf( + struct of_changeset *ocs, struct device_node *np, + const char *name, const char *fmt, ...) +{ + return -EINVAL; +} + +static inline int __of_changeset_add_update_property_string_list( + struct of_changeset *ocs, struct device_node *np, + const char *name, const char **strs, int count, bool update) +{ + return -EINVAL; +} + #endif /* CONFIG_OF_DYNAMIC */ +#ifdef CONFIG_OF_DYNAMIC +/** + * of_changeset_add_property_copy - Create a new property copying name & value + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * @value: pointer to the value data + * @length: length of the value in bytes + * + * Adds a property to the changeset by making copies of the name & value + * entries. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int of_changeset_add_property_copy(struct of_changeset *ocs, + struct device_node *np, const char *name, + const void *value, int length) +{ + return __of_changeset_add_update_property_copy(ocs, np, name, value, + length, false); +} + +/** + * of_changeset_update_property_copy - Update a property copying name & value + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * @value: pointer to the value data + * @length: length of the value in bytes + * + * Update a property to the changeset by making copies of the name & value + * entries. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int of_changeset_update_property_copy(struct of_changeset *ocs, + struct device_node *np, const char *name, + const void *value, int length) +{ + return __of_changeset_add_update_property_copy(ocs, np, name, value, + length, true); +} + +/** + * __of_changeset_add_update_property_string - Create/update a string property + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * @str: string property value + * @update: True on update operation + * + * Adds/updates a string property to the changeset by making copies of the name + * and the given value. The @update parameter controls whether an add or + * update takes place. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int __of_changeset_add_update_property_string( + struct of_changeset *ocs, struct device_node *np, const char *name, + const char *str, bool update) +{ + return __of_changeset_add_update_property_copy(ocs, np, name, str, + strlen(str) + 1, update); +} + +/** + * __of_changeset_add_update_property_stringv - Create/update a formatted + * string property + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * @fmt: format of string property + * @vargs: arguments of the format string + * @update: True on update operation + * + * Adds/updates a string property to the changeset by making copies of the name + * and the formatted value. The @update parameter controls whether an add or + * update takes place. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int __of_changeset_add_update_property_stringv( + struct of_changeset *ocs, struct device_node *np, const char *name, + const char *fmt, va_list vargs, bool update) +{ + char *str; + int ret; + + str = kvasprintf(GFP_KERNEL, fmt, vargs); + if (!str) + return -ENOMEM; + ret = __of_changeset_add_update_property_string(ocs, np, name, str, + update); + kfree(str); + + return ret; +} + +/** + * of_changeset_add_property_string_list - Create a new string list property + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * @strs: pointer to the string list + * @count: string count + * + * Adds a string list property to the changeset. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int of_changeset_add_property_string_list( + struct of_changeset *ocs, struct device_node *np, const char *name, + const char **strs, int count) +{ + return __of_changeset_add_update_property_string_list(ocs, np, name, + strs, count, false); +} + +/** + * of_changeset_update_property_string_list - Update string list property + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * @strs: pointer to the string list + * @count: string count + * + * Updates a string list property to the changeset. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int of_changeset_update_property_string_list( + struct of_changeset *ocs, struct device_node *np, + const char *name, const char **strs, int count) +{ + return __of_changeset_add_update_property_string_list(ocs, np, name, + strs, count, true); +} + +/** + * of_changeset_add_property_string - Adds a string property + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * @str: string property + * + * Adds a string property to the changeset by making copies of the name + * and the string value. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int of_changeset_add_property_string( + struct of_changeset *ocs, struct device_node *np, + const char *name, const char *str) +{ + return __of_changeset_add_update_property_string(ocs, np, name, str, + false); +} + +/** + * of_changeset_update_property_string - Update a string property + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * @str: string property + * + * Updates a string property to the changeset by making copies of the name + * and the string value. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int of_changeset_update_property_string( + struct of_changeset *ocs, struct device_node *np, + const char *name, const char *str) +{ + return __of_changeset_add_update_property_string(ocs, np, name, str, + true); +} + +/** + * of_changeset_add_property_u32 - Create a new u32 property + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * @val: value in host endian format + * + * Adds a u32 property to the changeset. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int of_changeset_add_property_u32(struct of_changeset *ocs, + struct device_node *np, const char *name, u32 val) +{ + val = cpu_to_be32(val); + return __of_changeset_add_update_property_copy(ocs, np, name, &val, + sizeof(val), false); +} + +/** + * of_changeset_update_property_u32 - Update u32 property + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * @val: value in host endian format + * + * Updates a u32 property to the changeset. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int of_changeset_update_property_u32( + struct of_changeset *ocs, struct device_node *np, + const char *name, u32 val) +{ + val = cpu_to_be32(val); + return __of_changeset_add_update_property_copy(ocs, np, name, &val, + sizeof(val), true); +} + +/** + * of_changeset_add_property_bool - Create a new u32 property + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * + * Adds a bool property to the changeset. Note that there is + * no option to set the value to false, since the property + * existing sets it to true. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int of_changeset_add_property_bool( + struct of_changeset *ocs, struct device_node *np, const char *name) +{ + return __of_changeset_add_update_property_copy(ocs, np, name, "", 0, + false); +} + +/** + * of_changeset_update_property_bool - Update a bool property + * + * @ocs: changeset pointer + * @np: device node pointer + * @name: name of the property + * + * Updates a property to the changeset. Note that there is + * no option to set the value to false, since the property + * existing sets it to true. + * + * Returns zero on success, a negative error value otherwise. + */ +static inline int of_changeset_update_property_bool(struct of_changeset *ocs, + struct device_node *np, const char *name) +{ + return __of_changeset_add_update_property_copy(ocs, np, name, "", 0, + true); +} +#endif + +/* CONFIG_OF_RESOLVE api */ +extern int of_resolve_phandles(struct device_node *tree); + /** * of_device_is_system_power_controller - Tells if system-power-controller is found for device_node * @np: Pointer to the given device_node diff --git a/include/linux/phy/phy-zynqmp.h b/include/linux/phy/phy-zynqmp.h new file mode 100644 index 000000000000..0a25fa85527e --- /dev/null +++ b/include/linux/phy/phy-zynqmp.h @@ -0,0 +1,60 @@ +/* + * Xilinx ZynqMP PHY header + * + * Copyright (C) 2016 Xilinx, Inc. + * + * Author: Anurag Kumar Vulisha <anuragku@xilinx.com> + * Author: Hyun Woo Kwon <hyunk@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PHY_ZYNQMP_H_ +#define _PHY_ZYNQMP_H_ + +struct phy; + +#if defined(CONFIG_PHY_XILINX_ZYNQMP) + +extern int xpsgtr_override_deemph(struct phy *phy, u8 plvl, u8 vlvl); +extern int xpsgtr_margining_factor(struct phy *phy, u8 plvl, u8 vlvl); +extern int xpsgtr_wait_pll_lock(struct phy *phy); +int xpsgtr_usb_crst_assert(struct phy *phy); +int xpsgtr_usb_crst_release(struct phy *phy); +#else + +static inline int xpsgtr_override_deemph(struct phy *base, u8 plvl, u8 vlvl) +{ + return -ENODEV; +} + +static inline int xpsgtr_margining_factor(struct phy *base, u8 plvl, u8 vlvl) +{ + return -ENODEV; +} + +extern inline int xpsgtr_wait_pll_lock(struct phy *phy) +{ + return -ENODEV; +} + +extern inline int xpsgtr_usb_crst_assert(struct phy *phy) +{ + return -ENODEV; +} + +extern inline int xpsgtr_usb_crst_release(struct phy *phy) +{ + return -ENODEV; +} + +#endif + +#endif /* _PHY_ZYNQMP_H_ */ diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h index 04d04709f2bd..2c911b7f646d 100644 --- a/include/linux/remoteproc.h +++ b/include/linux/remoteproc.h @@ -344,6 +344,8 @@ struct firmware; * @start: power on the device and boot it * @stop: power off the device * @kick: kick a virtqueue (virtqueue id given as a parameter) + * @peek_remote_kick: check if remote has kicked + * @ack_remote_kick: ack remote kick * @da_to_va: optional platform hook to perform address translations * @parse_fw: parse firmware to extract information (e.g. resource table) * @find_loaded_rsc_table: find the loaded resouce table @@ -356,6 +358,8 @@ struct rproc_ops { int (*start)(struct rproc *rproc); int (*stop)(struct rproc *rproc); void (*kick)(struct rproc *rproc, int vqid); + bool (*peek_remote_kick)(struct rproc *rproc, char *buf, size_t *len); + void (*ack_remote_kick)(struct rproc *rproc); void * (*da_to_va)(struct rproc *rproc, u64 da, int len); int (*parse_fw)(struct rproc *rproc, const struct firmware *fw); struct resource_table *(*find_loaded_rsc_table)( @@ -461,6 +465,7 @@ struct rproc_dump_segment { * @auto_boot: flag to indicate if remote processor should be auto-started * @dump_segments: list of segments in the firmware * @nb_vdev: number of vdev currently handled by rproc + * @sysfs_kick: allow kick remoteproc from sysfs */ struct rproc { struct list_head node; @@ -494,6 +499,7 @@ struct rproc { bool auto_boot; struct list_head dump_segments; int nb_vdev; + int sysfs_kick; }; /** diff --git a/include/linux/soc/xilinx/zynqmp/fw.h b/include/linux/soc/xilinx/zynqmp/fw.h new file mode 100644 index 000000000000..98165fa2d1ca --- /dev/null +++ b/include/linux/soc/xilinx/zynqmp/fw.h @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + */ + +#ifndef __SOC_ZYNQMP_FW_H__ +#define __SOC_ZYNQMP_FW_H__ + +#include <linux/nvmem-consumer.h> + +enum { + ZYNQMP_SILICON_V1 = 0, + ZYNQMP_SILICON_V2, + ZYNQMP_SILICON_V3, + ZYNQMP_SILICON_V4, +}; + +static inline char *zynqmp_nvmem_get_silicon_version(struct device *dev, + const char *cname) +{ + struct nvmem_cell *cell; + ssize_t data; + char *ret; + + cell = nvmem_cell_get(dev, cname); + if (IS_ERR(cell)) + return ERR_CAST(cell); + + ret = nvmem_cell_read(cell, &data); + nvmem_cell_put(cell); + + return ret; +} + +#endif /* __SOC_ZYNQMP_FW_H__ */ diff --git a/include/linux/soc/xilinx/zynqmp/tap_delays.h b/include/linux/soc/xilinx/zynqmp/tap_delays.h new file mode 100644 index 000000000000..5f2ef35c0d8e --- /dev/null +++ b/include/linux/soc/xilinx/zynqmp/tap_delays.h @@ -0,0 +1,32 @@ +/* + * Xilinx Zynq MPSoC Power Management + * + * Copyright (C) 2016 - 2018, Xilinx, Inc. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/firmware/xlnx-zynqmp.h> + +#ifdef CONFIG_ARCH_ZYNQMP +/* API for programming the tap delays */ +void arasan_zynqmp_set_tap_delay(u8 deviceid, u8 itap_delay, u8 otap_delay); + +/* API to reset the DLL */ +void zynqmp_dll_reset(u8 deviceid); +#else +inline void arasan_zynqmp_set_tap_delay(u8 deviceid, u8 itap_delay, + u8 otap_delay) {} +inline void zynqmp_dll_reset(u8 deviceid) {} +#endif diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 053abd22ad31..1f8be03e0560 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -464,6 +464,20 @@ struct spi_controller { #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ + /* Controller may support data stripe feature when more than one + * chips are present. + * Setting data stripe will send data in following manner: + * -> even bytes i.e. 0, 2, 4,... are transmitted on lower data bus + * -> odd bytes i.e. 1, 3, 5,.. are transmitted on upper data bus + */ +#define SPI_MASTER_QUAD_MODE BIT(6) /* support quad mode */ +#define SPI_MASTER_DATA_STRIPE BIT(7) /* support data stripe */ + /* Controller may support asserting more than one chip select at once. + * This flag will enable that feature. + */ +#define SPI_MASTER_BOTH_CS BIT(8) /* assert both chip selects */ +#define SPI_MASTER_U_PAGE BIT(9) /* select upper flash */ + /* flag indicating this is an SPI slave controller */ bool slave; @@ -732,6 +746,7 @@ extern void spi_res_release(struct spi_controller *ctlr, * @len: size of rx and tx buffers (in bytes) * @speed_hz: Select a speed other than the device default for this * transfer. If 0 the default (from @spi_device) is used. + * @dummy: number of dummy cycles. * @bits_per_word: select a bits_per_word other than the device default * for this transfer. If 0 the default (from @spi_device) is used. * @cs_change: affects chipselect after this transfer completes @@ -745,6 +760,7 @@ extern void spi_res_release(struct spi_controller *ctlr, * @transfer_list: transfers are sequenced through @spi_message.transfers * @tx_sg: Scatterlist for transmit, currently not for client use * @rx_sg: Scatterlist for receive, currently not for client use + * @stripe: true-> enable stripe, false-> disable stripe. * * SPI transfers always write the same number of bytes as they read. * Protocol drivers should always provide @rx_buf and/or @tx_buf. @@ -826,7 +842,8 @@ struct spi_transfer { u16 delay_usecs; u32 speed_hz; u16 word_delay; - + u32 dummy; + bool stripe; struct list_head transfer_list; }; @@ -1278,7 +1295,6 @@ struct spi_board_info { /* slower signaling on noisy or low voltage boards */ u32 max_speed_hz; - /* bus_num is board specific and matches the bus_num of some * spi_controller that will probably be registered later. * @@ -1358,6 +1374,9 @@ of_find_spi_device_by_node(struct device_node *node) #endif /* IS_ENABLED(CONFIG_OF) */ +bool +update_stripe(const u8 opcode); + /* Compatibility layer */ #define spi_master spi_controller diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index edd89b7c8f18..5661a4459dda 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -61,7 +61,8 @@ struct ci_hdrc_platform_data { #define CI_HDRC_OVERRIDE_PHY_CONTROL BIT(12) /* Glue layer manages phy */ #define CI_HDRC_REQUIRES_ALIGNED_DMA BIT(13) #define CI_HDRC_IMX_IS_HSIC BIT(14) -#define CI_HDRC_PMQOS BIT(15) +#define CI_HDRC_PHY_VBUS_CONTROL BIT(15) +#define CI_HDRC_PMQOS BIT(16) enum usb_dr_mode dr_mode; #define CI_HDRC_CONTROLLER_RESET_EVENT 0 #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1 diff --git a/include/linux/usb/xhci_pdriver.h b/include/linux/usb/xhci_pdriver.h new file mode 100644 index 000000000000..af8043181395 --- /dev/null +++ b/include/linux/usb/xhci_pdriver.h @@ -0,0 +1,29 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + */ + +#ifndef __USB_CORE_XHCI_PDRIVER_H +#define __USB_CORE_XHCI_PDRIVER_H + +/* Call dwc3_host_wakeup_capable() only for dwc3 DRD mode or HOST only mode */ +#if (IS_REACHABLE(CONFIG_USB_DWC3_HOST) || \ + (IS_REACHABLE(CONFIG_USB_DWC3_OF_SIMPLE) && \ + !IS_REACHABLE(CONFIG_USB_DWC3_GADGET))) + + /* Let the dwc3 driver know about device wakeup capability */ +void dwc3_host_wakeup_capable(struct device *dev, bool wakeup); + +#else +void dwc3_host_wakeup_capable(struct device *dev, bool wakeup) +{ ; } +#endif + +#endif /* __USB_CORE_XHCI_PDRIVER_H */ diff --git a/include/linux/xilinx_phy.h b/include/linux/xilinx_phy.h new file mode 100644 index 000000000000..34a048f7dbe6 --- /dev/null +++ b/include/linux/xilinx_phy.h @@ -0,0 +1,20 @@ +#ifndef _XILINX_PHY_H +#define _XILINX_PHY_H + +/* Mask used for ID comparisons */ +#define XILINX_PHY_ID_MASK 0xfffffff0 + +/* Known PHY IDs */ +#define XILINX_PHY_ID 0x01740c00 + +/* struct phy_device dev_flags definitions */ +#define XAE_PHY_TYPE_MII 0 +#define XAE_PHY_TYPE_GMII 1 +#define XAE_PHY_TYPE_RGMII_1_3 2 +#define XAE_PHY_TYPE_RGMII_2_0 3 +#define XAE_PHY_TYPE_SGMII 4 +#define XAE_PHY_TYPE_1000BASE_X 5 +#define XAE_PHY_TYPE_2500 6 +#define XXE_PHY_TYPE_USXGMII 7 + +#endif /* _XILINX_PHY_H */ diff --git a/include/media/media-entity.h b/include/media/media-entity.h index 8cb2c504a05c..96310de47a25 100644 --- a/include/media/media-entity.h +++ b/include/media/media-entity.h @@ -205,6 +205,9 @@ struct media_pad { * @link_validate: Return whether a link is valid from the entity point of * view. The media_pipeline_start() function * validates all links by calling this operation. Optional. + * @has_route: Return whether a route exists inside the entity between + * two given pads. Optional. If the operation isn't + * implemented all pads will be considered as connected. * * .. note:: * @@ -217,6 +220,8 @@ struct media_entity_operations { const struct media_pad *local, const struct media_pad *remote, u32 flags); int (*link_validate)(struct media_link *link); + bool (*has_route)(struct media_entity *entity, unsigned int pad0, + unsigned int pad1); }; /** @@ -879,6 +884,9 @@ int media_entity_get_fwnode_pad(struct media_entity *entity, struct fwnode_handle *fwnode, unsigned long direction_flags); +bool media_entity_has_route(struct media_entity *entity, unsigned int sink, + unsigned int source); + /** * media_graph_walk_init - Allocate resources used by graph walk. * diff --git a/include/media/v4l2-subdev.h b/include/media/v4l2-subdev.h index 7168311e8ecc..ce025f06c2ef 100644 --- a/include/media/v4l2-subdev.h +++ b/include/media/v4l2-subdev.h @@ -710,6 +710,10 @@ struct v4l2_subdev_pad_ops { struct v4l2_mbus_frame_desc *fd); int (*set_frame_desc)(struct v4l2_subdev *sd, unsigned int pad, struct v4l2_mbus_frame_desc *fd); + int (*get_routing)(struct v4l2_subdev *sd, + struct v4l2_subdev_routing *route); + int (*set_routing)(struct v4l2_subdev *sd, + struct v4l2_subdev_routing *route); }; /** diff --git a/include/soc/xilinx/xlnx_vcu.h b/include/soc/xilinx/xlnx_vcu.h new file mode 100644 index 000000000000..ff03ede993ed --- /dev/null +++ b/include/soc/xilinx/xlnx_vcu.h @@ -0,0 +1,39 @@ +/* + * Xilinx VCU Init + * + * Copyright (C) 2016 - 2017 Xilinx, Inc. + * + * Contacts Dhaval Shah <dshah@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef _XILINX_VCU_H_ +#define _XILINX_VCU_H_ + +#define VCU_GASKET_INIT 0x74 +#define VCU_GASKET_VALUE 0x03 + +/** + * struct xvcu_device - Xilinx VCU init device structure + * @dev: Platform device + * @pll_ref: pll ref clock source + * @reset_gpio: vcu reset gpio + * @aclk: axi clock source + * @logicore_reg_ba: logicore reg base address + * @vcu_slcr_ba: vcu_slcr Register base address + */ +struct xvcu_device { + struct device *dev; + struct clk *pll_ref; + struct clk *aclk; + struct gpio_desc *reset_gpio; + void __iomem *logicore_reg_ba; + void __iomem *vcu_slcr_ba; +}; + +u32 xvcu_get_color_depth(struct xvcu_device *xvcu); +u32 xvcu_get_memory_depth(struct xvcu_device *xvcu); +u32 xvcu_get_clock_frequency(struct xvcu_device *xvcu); +u32 xvcu_get_num_cores(struct xvcu_device *xvcu); + +#endif /* _XILINX_VCU_H_ */ diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3f987a..3193c3c3f5c0 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -145,6 +145,14 @@ extern "C" { #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ /* + * 2 plane 10 bit per component YCbCr + * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian + * index 1 = Cb:Cr plane, [63:0] x:Cb2:Cr2:Cb1:x:Cr1:Cb0:Cr0 2:10:10:10:2:10:10:10 little endian + */ +#define DRM_FORMAT_XV15 fourcc_code('X', 'V', '1', '5') /* 2x2 subsampled Cb:Cr plane 2:10:10:10 */ +#define DRM_FORMAT_XV20 fourcc_code('X', 'V', '2', '0') /* 2x1 subsampled Cb:Cr plane 2:10:10:10 */ + +/* * Floating point 64bpp RGB * IEEE 754-2008 binary16 half-precision float * [15:0] sign:exponent:mantissa 1:5:10 @@ -209,6 +217,13 @@ extern "C" { #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') +#define DRM_FORMAT_AVUY fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */ +#define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', '2', '4') /* [31:0] x:Cr:Cb:Y 8:8:8:8 little endian */ +#define DRM_FORMAT_XVUY2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] x:Cr:Cb:Y 2:10:10:10 little endian */ + +/* Grey scale */ +#define DRM_FORMAT_Y8 fourcc_code('G', 'R', 'E', 'Y') /* 8 Greyscale */ +#define DRM_FORMAT_Y10 fourcc_code('Y', '1', '0', ' ') /* 10 Greyscale */ /* * 2 plane RGB + A * index 0 = RGB plane, same format as the corresponding non _A8 format has diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 83cd1636b9be..b35aebf3f8d1 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -475,6 +475,8 @@ struct drm_mode_fb_cmd { #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ #define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ +#define DRM_MODE_FB_ALTERNATE_TOP (1<<2) /* for alternate top field */ +#define DRM_MODE_FB_ALTERNATE_BOTTOM (1<<3) /* for alternate bottom field */ struct drm_mode_fb_cmd2 { __u32 fb_id; diff --git a/include/uapi/linux/if_alg.h b/include/uapi/linux/if_alg.h index bc2bcdec377b..aa31b18ebf0a 100644 --- a/include/uapi/linux/if_alg.h +++ b/include/uapi/linux/if_alg.h @@ -35,6 +35,7 @@ struct af_alg_iv { #define ALG_SET_OP 3 #define ALG_SET_AEAD_ASSOCLEN 4 #define ALG_SET_AEAD_AUTHSIZE 5 +#define ALG_SET_KEY_TYPE 6 /* Operations */ #define ALG_OP_DECRYPT 0 diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index 2a6b253cfb05..7e75f4d8319b 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -34,7 +34,7 @@ #define MEDIA_BUS_FMT_FIXED 0x0001 -/* RGB - next is 0x101c */ +/* RGB - next is 0x101e */ #define MEDIA_BUS_FMT_RGB444_1X12 0x1016 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 @@ -62,8 +62,11 @@ #define MEDIA_BUS_FMT_RGB101010_1X30 0x1018 #define MEDIA_BUS_FMT_RGB121212_1X36 0x1019 #define MEDIA_BUS_FMT_RGB161616_1X48 0x101a +#define MEDIA_BUS_FMT_RBG101010_1X30 0x101b +#define MEDIA_BUS_FMT_RBG121212_1X36 0x101c +#define MEDIA_BUS_FMT_RBG161616_1X48 0x101d -/* YUV (including grey) - next is 0x202d */ +/* YUV (including grey) - next is 0x2035 */ #define MEDIA_BUS_FMT_Y8_1X8 0x2001 #define MEDIA_BUS_FMT_UV8_1X8 0x2015 #define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 @@ -80,11 +83,13 @@ #define MEDIA_BUS_FMT_VYUY10_2X10 0x2019 #define MEDIA_BUS_FMT_YUYV10_2X10 0x200b #define MEDIA_BUS_FMT_YVYU10_2X10 0x200c +#define MEDIA_BUS_FMT_VYYUYY10_4X20 0x2031 #define MEDIA_BUS_FMT_Y12_1X12 0x2013 #define MEDIA_BUS_FMT_UYVY12_2X12 0x201c #define MEDIA_BUS_FMT_VYUY12_2X12 0x201d #define MEDIA_BUS_FMT_YUYV12_2X12 0x201e #define MEDIA_BUS_FMT_YVYU12_2X12 0x201f +#define MEDIA_BUS_FMT_VUY12_1X36 0x2033 #define MEDIA_BUS_FMT_UYVY8_1X16 0x200f #define MEDIA_BUS_FMT_VYUY8_1X16 0x2010 #define MEDIA_BUS_FMT_YUYV8_1X16 0x2011 @@ -102,12 +107,19 @@ #define MEDIA_BUS_FMT_YUYV12_1X24 0x2022 #define MEDIA_BUS_FMT_YVYU12_1X24 0x2023 #define MEDIA_BUS_FMT_YUV10_1X30 0x2016 +#define MEDIA_BUS_FMT_VUY10_1X30 0x2032 #define MEDIA_BUS_FMT_UYYVYY10_0_5X30 0x2027 #define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 #define MEDIA_BUS_FMT_UYYVYY12_0_5X36 0x2028 #define MEDIA_BUS_FMT_YUV12_1X36 0x2029 #define MEDIA_BUS_FMT_YUV16_1X48 0x202a +#define MEDIA_BUS_FMT_VUY16_1X48 0x2034 #define MEDIA_BUS_FMT_UYYVYY16_0_5X48 0x202b +#define MEDIA_BUS_FMT_VYYUYY8_1X24 0x202c +#define MEDIA_BUS_FMT_Y16_1X16 0x202d +#define MEDIA_BUS_FMT_UYYVYY12_4X24 0x202e +#define MEDIA_BUS_FMT_UYYVYY16_4X32 0x202f +#define MEDIA_BUS_FMT_UYVY16_2X32 0x2030 /* Bayer - next is 0x3021 */ #define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001 diff --git a/include/uapi/linux/uio/uio.h b/include/uapi/linux/uio/uio.h new file mode 100644 index 000000000000..db92d311c85f --- /dev/null +++ b/include/uapi/linux/uio/uio.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * The header for UIO driver + * + * Copyright (C) 2019 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com> + */ + +#ifndef _UAPI_UIO_UIO_H_ +#define _UAPI_UIO_UIO_H_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +/** + * enum uio_dmabuf_dir - list of dma directions for mapping management + * @UIO_DMABUF_DIR_BIDIR: Bidirectional DMA. To and from device + * @UIO_DMABUF_DIR_TO_DEV: DMA to device + * @UIO_DMABUF_DIR_FROM_DEV: DMA from device + * @UIO_DMABUF_DIR_NONE: Direction not specified + */ +enum uio_dmabuf_dir { + UIO_DMABUF_DIR_BIDIR = 1, + UIO_DMABUF_DIR_TO_DEV = 2, + UIO_DMABUF_DIR_FROM_DEV = 3, + UIO_DMABUF_DIR_NONE = 4, +}; + +/** + * struct uio_dmabuf_args - arguments from userspace to map / unmap dmabuf + * @dbuf_fd: The fd or dma buf + * @dma_addr: The dma address of dmabuf @dbuf_fd + * @size: The size of dmabuf @dbuf_fd + * @dir: direction of dma transfer of dmabuf @dbuf_fd + */ +struct uio_dmabuf_args { + __s32 dbuf_fd; + __u64 dma_addr; + __u64 size; + __u8 dir; +}; + +#define UIO_IOC_BASE 'U' + +/** + * DOC: UIO_IOC_MAP_DMABUF - Map the dma buf to userspace uio application + * + * This takes uio_dmabuf_args, and maps the given dmabuf @dbuf_fd and returns + * information to userspace. + * FIXME: This is experimental and may change at any time. Don't consider this + * as stable ABI. + */ +#define UIO_IOC_MAP_DMABUF _IOWR(UIO_IOC_BASE, 0x1, struct uio_dmabuf_args) + +/** + * DOC: UIO_IOC_UNMAP_DMABUF - Unmap the dma buf + * + * This takes uio_dmabuf_args, and unmaps the previous mapped dmabuf @dbuf_fd. + * FIXME: This is experimental and may change at any time. Don't consider this + * as stable ABI. + */ +#define UIO_IOC_UNMAP_DMABUF _IOWR(UIO_IOC_BASE, 0x2, struct uio_dmabuf_args) + +#endif diff --git a/include/uapi/linux/v4l2-mediabus.h b/include/uapi/linux/v4l2-mediabus.h index 123a231001a8..325c985ed06f 100644 --- a/include/uapi/linux/v4l2-mediabus.h +++ b/include/uapi/linux/v4l2-mediabus.h @@ -68,6 +68,8 @@ enum v4l2_mbus_pixelcode { V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB888_2X12_BE), V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB888_2X12_LE), V4L2_MBUS_FROM_MEDIA_BUS_FMT(ARGB8888_1X32), + V4L2_MBUS_FROM_MEDIA_BUS_FMT(RBG888_1X24), + V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB888_1X32_PADHI), V4L2_MBUS_FROM_MEDIA_BUS_FMT(Y8_1X8), V4L2_MBUS_FROM_MEDIA_BUS_FMT(UV8_1X8), @@ -104,6 +106,7 @@ enum v4l2_mbus_pixelcode { V4L2_MBUS_FROM_MEDIA_BUS_FMT(VYUY12_1X24), V4L2_MBUS_FROM_MEDIA_BUS_FMT(YUYV12_1X24), V4L2_MBUS_FROM_MEDIA_BUS_FMT(YVYU12_1X24), + V4L2_MBUS_FROM_MEDIA_BUS_FMT(VUY8_1X24), V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR8_1X8), V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGBRG8_1X8), diff --git a/include/uapi/linux/v4l2-subdev.h b/include/uapi/linux/v4l2-subdev.h index 03970ce30741..b76f9b4afe05 100644 --- a/include/uapi/linux/v4l2-subdev.h +++ b/include/uapi/linux/v4l2-subdev.h @@ -155,6 +155,27 @@ struct v4l2_subdev_selection { __u32 reserved[8]; }; + +/** + * struct v4l2_subdev_route - A signal route inside a subdev + * @sink: the sink pad + * @source: the source pad + */ +struct v4l2_subdev_route { + __u32 sink; + __u32 source; +}; + +/** + * struct v4l2_subdev_routing - Routing information + * @num_routes: the total number of routes in the routes array + * @routes: the routes array + */ +struct v4l2_subdev_routing { + __u32 num_routes; + struct v4l2_subdev_route *routes; +}; + /* Backwards compatibility define --- to be removed */ #define v4l2_subdev_edid v4l2_edid @@ -181,5 +202,7 @@ struct v4l2_subdev_selection { #define VIDIOC_SUBDEV_ENUM_DV_TIMINGS _IOWR('V', 98, struct v4l2_enum_dv_timings) #define VIDIOC_SUBDEV_QUERY_DV_TIMINGS _IOR('V', 99, struct v4l2_dv_timings) #define VIDIOC_SUBDEV_DV_TIMINGS_CAP _IOWR('V', 100, struct v4l2_dv_timings_cap) +#define VIDIOC_SUBDEV_G_ROUTING _IOWR('V', 38, struct v4l2_subdev_routing) +#define VIDIOC_SUBDEV_S_ROUTING _IOWR('V', 39, struct v4l2_subdev_routing) #endif diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index dcd776e77442..b7f1bcaf37ec 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -546,20 +546,25 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */ #define V4L2_PIX_FMT_ABGR32 v4l2_fourcc('A', 'R', '2', '4') /* 32 BGRA-8-8-8-8 */ #define V4L2_PIX_FMT_XBGR32 v4l2_fourcc('X', 'R', '2', '4') /* 32 BGRX-8-8-8-8 */ -#define V4L2_PIX_FMT_BGRA32 v4l2_fourcc('R', 'A', '2', '4') /* 32 ABGR-8-8-8-8 */ -#define V4L2_PIX_FMT_BGRX32 v4l2_fourcc('R', 'X', '2', '4') /* 32 XBGR-8-8-8-8 */ #define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */ #define V4L2_PIX_FMT_RGBA32 v4l2_fourcc('A', 'B', '2', '4') /* 32 RGBA-8-8-8-8 */ #define V4L2_PIX_FMT_RGBX32 v4l2_fourcc('X', 'B', '2', '4') /* 32 RGBX-8-8-8-8 */ #define V4L2_PIX_FMT_ARGB32 v4l2_fourcc('B', 'A', '2', '4') /* 32 ARGB-8-8-8-8 */ +#define V4L2_PIX_FMT_BGRA32 v4l2_fourcc('A', 'B', 'G', 'R') /* 32 ABGR-8-8-8-8 */ #define V4L2_PIX_FMT_XRGB32 v4l2_fourcc('B', 'X', '2', '4') /* 32 XRGB-8-8-8-8 */ +#define V4L2_PIX_FMT_BGRX32 v4l2_fourcc('X', 'B', 'G', 'R') /* 32 XBGR-8-8-8-8 */ +#define V4L2_PIX_FMT_XBGR30 v4l2_fourcc('R', 'X', '3', '0') /* 32 XBGR-2-10-10-10 */ +#define V4L2_PIX_FMT_XBGR40 v4l2_fourcc('R', 'X', '4', '0') /* 40 XBGR-4-12-12-12 */ +#define V4L2_PIX_FMT_BGR48 v4l2_fourcc('R', 'G', '4', '8') /* 32 BGR-16-16-16 */ /* Grey formats */ #define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */ #define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') /* 4 Greyscale */ #define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') /* 6 Greyscale */ #define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */ +#define V4L2_PIX_FMT_XY10 v4l2_fourcc('X', 'Y', '1', '0') /* 10 Greyscale 2-10-10-10 */ #define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */ +#define V4L2_PIX_FMT_XY12 v4l2_fourcc('X', 'Y', '1', '2') /* 12 Greyscale 4-12-12-12 */ #define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */ #define V4L2_PIX_FMT_Y16_BE v4l2_fourcc_be('Y', '1', '6', ' ') /* 16 Greyscale BE */ @@ -581,6 +586,9 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') /* 16 YUV 4:2:2 */ #define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') /* 12 YUV 4:1:1 */ #define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */ +#define V4L2_PIX_FMT_XVUY32 v4l2_fourcc('X', 'V', '3', '2') /* 32 XVUY 8:8:8:8 */ +#define V4L2_PIX_FMT_AVUY32 v4l2_fourcc('A', 'V', '3', '2') /* 32 AVUY 8:8:8:8 */ +#define V4L2_PIX_FMT_VUY24 v4l2_fourcc('V', 'U', '2', '4') /* 24 VUY 8:8:8 */ #define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */ #define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */ #define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */ @@ -591,6 +599,7 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */ #define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ #define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */ +#define V4L2_PIX_FMT_XVUY10 v4l2_fourcc('X', '4', '1', '0') /* 32 XVUY 2-10-10-10 */ /* two planes -- one Y, one Cr + Cb interleaved */ #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ @@ -599,6 +608,14 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ +#define V4L2_PIX_FMT_XV20 v4l2_fourcc('X', 'V', '2', '0') /* 32 XY/UV 4:2:2 10-bit */ +#define V4L2_PIX_FMT_XV15 v4l2_fourcc('X', 'V', '1', '5') /* 32 XY/UV 4:2:0 10-bit */ +#define V4L2_PIX_FMT_X012 v4l2_fourcc('X', '0', '1', '2') /* 40 XY/UV 4:2:0 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X212 v4l2_fourcc('X', '2', '1', '2') /* 40 XY/UV 4:2:2 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X412 v4l2_fourcc('X', '4', '1', '2') /* 40 XY/UV 4:4:4 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X016 v4l2_fourcc('X', '0', '1', '6') /* 32 XY/UV 4:2:0 16-bit */ +#define V4L2_PIX_FMT_X216 v4l2_fourcc('X', '2', '1', '6') /* 32 XY/UV 4:2:2 16-bit */ +#define V4L2_PIX_FMT_X416 v4l2_fourcc('X', '4', '1', '6') /* 32 XY/UV 4:4:4 16-bit */ /* two non contiguous planes - one Y, one Cr + Cb interleaved */ #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */ @@ -606,6 +623,14 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_NV16M v4l2_fourcc('N', 'M', '1', '6') /* 16 Y/CbCr 4:2:2 */ #define V4L2_PIX_FMT_NV61M v4l2_fourcc('N', 'M', '6', '1') /* 16 Y/CrCb 4:2:2 */ #define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 macroblocks */ +#define V4L2_PIX_FMT_XV20M v4l2_fourcc('X', 'M', '2', '0') /* 32 XY/UV 4:2:2 10-bit */ +#define V4L2_PIX_FMT_XV15M v4l2_fourcc('X', 'M', '1', '5') /* 32 XY/UV 4:2:0 10-bit */ +#define V4L2_PIX_FMT_X012M v4l2_fourcc('M', '0', '1', '2') /* 40 XY/UV 4:2:0 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X212M v4l2_fourcc('M', '2', '1', '2') /* 40 XY/UV 4:2:2 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X412M v4l2_fourcc('M', '4', '1', '2') /* 40 XY/UV 4:4:4 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X016M v4l2_fourcc('M', '0', '1', '6') /* 32 XY/UV 4:2:0 16-bit */ +#define V4L2_PIX_FMT_X216M v4l2_fourcc('M', '2', '1', '6') /* 32 XY/UV 4:2:2 16-bit */ +#define V4L2_PIX_FMT_X416M v4l2_fourcc('M', '4', '1', '6') /* 32 XY/UV 4:4:4 16-bit */ #define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 16x16 macroblocks */ /* three planes - Y Cb, Cr */ diff --git a/include/uapi/linux/xilinx-csi2rxss.h b/include/uapi/linux/xilinx-csi2rxss.h new file mode 100644 index 000000000000..df64ddc5eed4 --- /dev/null +++ b/include/uapi/linux/xilinx-csi2rxss.h @@ -0,0 +1,18 @@ +#ifndef __UAPI_XILINX_CSI2RXSS_H__ +#define __UAPI_XILINX_CSI2RXSS_H__ + +#include <linux/videodev2.h> + +/* + * Events + * + * V4L2_EVENT_XLNXCSIRX_SPKT: Short packet received + * V4L2_EVENT_XLNXCSIRX_SPKT_OVF: Short packet FIFO overflow + * V4L2_EVENT_XLNXCSIRX_SLBF: Stream line buffer full + */ +#define V4L2_EVENT_XLNXCSIRX_CLASS (V4L2_EVENT_PRIVATE_START | 0x100) +#define V4L2_EVENT_XLNXCSIRX_SPKT (V4L2_EVENT_XLNXCSIRX_CLASS | 0x1) +#define V4L2_EVENT_XLNXCSIRX_SPKT_OVF (V4L2_EVENT_XLNXCSIRX_CLASS | 0x2) +#define V4L2_EVENT_XLNXCSIRX_SLBF (V4L2_EVENT_XLNXCSIRX_CLASS | 0x3) + +#endif /* __UAPI_XILINX_CSI2RXSS_H__ */ diff --git a/include/uapi/linux/xilinx-hls.h b/include/uapi/linux/xilinx-hls.h new file mode 100644 index 000000000000..a7f6447927e0 --- /dev/null +++ b/include/uapi/linux/xilinx-hls.h @@ -0,0 +1,21 @@ +#ifndef __UAPI_XILINX_HLS_H__ +#define __UAPI_XILINX_HLS_H__ + +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/videodev2.h> + +struct xilinx_axi_hls_register { + __u32 offset; + __u32 value; +}; + +struct xilinx_axi_hls_registers { + __u32 num_regs; + struct xilinx_axi_hls_register __user *regs; +}; + +#define XILINX_AXI_HLS_READ _IOWR('V', BASE_VIDIOC_PRIVATE+0, struct xilinx_axi_hls_registers) +#define XILINX_AXI_HLS_WRITE _IOW('V', BASE_VIDIOC_PRIVATE+1, struct xilinx_axi_hls_registers) + +#endif /* __UAPI_XILINX_HLS_H__ */ diff --git a/include/uapi/linux/xilinx-sdirxss.h b/include/uapi/linux/xilinx-sdirxss.h new file mode 100644 index 000000000000..b7a98041f169 --- /dev/null +++ b/include/uapi/linux/xilinx-sdirxss.h @@ -0,0 +1,66 @@ +#ifndef __UAPI_XILINX_SDIRXSS_H__ +#define __UAPI_XILINX_SDIRXSS_H__ + +#include <linux/types.h> +#include <linux/videodev2.h> + +/* + * Events + * + * V4L2_EVENT_XLNXSDIRX_VIDUNLOCK: Video unlock event + * V4L2_EVENT_XLNXSDIRX_UNDERFLOW: Video in to AXI4 Stream core underflowed + * V4L2_EVENT_XLNXSDIRX_OVERFLOW: Video in to AXI4 Stream core overflowed + */ +#define V4L2_EVENT_XLNXSDIRX_CLASS (V4L2_EVENT_PRIVATE_START | 0x200) +#define V4L2_EVENT_XLNXSDIRX_VIDUNLOCK (V4L2_EVENT_XLNXSDIRX_CLASS | 0x1) +#define V4L2_EVENT_XLNXSDIRX_UNDERFLOW (V4L2_EVENT_XLNXSDIRX_CLASS | 0x2) +#define V4L2_EVENT_XLNXSDIRX_OVERFLOW (V4L2_EVENT_XLNXSDIRX_CLASS | 0x3) + +/* + * This enum is used to prepare the bitmask + * of modes to be detected + */ +enum { + XSDIRX_MODE_SD_OFFSET = 0, + XSDIRX_MODE_HD_OFFSET, + XSDIRX_MODE_3G_OFFSET, + XSDIRX_MODE_6G_OFFSET, + XSDIRX_MODE_12GI_OFFSET, + XSDIRX_MODE_12GF_OFFSET, + XSDIRX_MODE_NUM_SUPPORTED, +}; + +#define XSDIRX_DETECT_ALL_MODES (BIT(XSDIRX_MODE_SD_OFFSET) | \ + BIT(XSDIRX_MODE_HD_OFFSET) | \ + BIT(XSDIRX_MODE_3G_OFFSET) | \ + BIT(XSDIRX_MODE_6G_OFFSET) | \ + BIT(XSDIRX_MODE_12GI_OFFSET) | \ + BIT(XSDIRX_MODE_12GF_OFFSET)) + +/* + * EDH Error Types + * ANC - Ancillary Data Packet Errors + * FF - Full Field Errors + * AP - Active Portion Errors + */ + +#define XSDIRX_EDH_ERRCNT_ANC_EDH_ERR BIT(0) +#define XSDIRX_EDH_ERRCNT_ANC_EDA_ERR BIT(1) +#define XSDIRX_EDH_ERRCNT_ANC_IDH_ERR BIT(2) +#define XSDIRX_EDH_ERRCNT_ANC_IDA_ERR BIT(3) +#define XSDIRX_EDH_ERRCNT_ANC_UES_ERR BIT(4) +#define XSDIRX_EDH_ERRCNT_FF_EDH_ERR BIT(5) +#define XSDIRX_EDH_ERRCNT_FF_EDA_ERR BIT(6) +#define XSDIRX_EDH_ERRCNT_FF_IDH_ERR BIT(7) +#define XSDIRX_EDH_ERRCNT_FF_IDA_ERR BIT(8) +#define XSDIRX_EDH_ERRCNT_FF_UES_ERR BIT(9) +#define XSDIRX_EDH_ERRCNT_AP_EDH_ERR BIT(10) +#define XSDIRX_EDH_ERRCNT_AP_EDA_ERR BIT(11) +#define XSDIRX_EDH_ERRCNT_AP_IDH_ERR BIT(12) +#define XSDIRX_EDH_ERRCNT_AP_IDA_ERR BIT(13) +#define XSDIRX_EDH_ERRCNT_AP_UES_ERR BIT(14) +#define XSDIRX_EDH_ERRCNT_PKT_CHKSUM_ERR BIT(15) + +#define XSDIRX_EDH_ALLERR_MASK 0xFFFF + +#endif /* __UAPI_XILINX_SDIRXSS_H__ */ diff --git a/include/uapi/linux/xilinx-v4l2-controls.h b/include/uapi/linux/xilinx-v4l2-controls.h index b6441fe705c5..61a02a326515 100644 --- a/include/uapi/linux/xilinx-v4l2-controls.h +++ b/include/uapi/linux/xilinx-v4l2-controls.h @@ -70,5 +70,146 @@ #define V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH (V4L2_CID_XILINX_TPG + 16) /* Noise level */ #define V4L2_CID_XILINX_TPG_NOISE_GAIN (V4L2_CID_XILINX_TPG + 17) +/* Foreground pattern (HLS)*/ +#define V4L2_CID_XILINX_TPG_HLS_FG_PATTERN (V4L2_CID_XILINX_TPG + 18) +/* + * Xilinx CRESAMPLE Video IP + */ + +#define V4L2_CID_XILINX_CRESAMPLE (V4L2_CID_USER_BASE + 0xc020) + +/* The field parity for interlaced video */ +#define V4L2_CID_XILINX_CRESAMPLE_FIELD_PARITY (V4L2_CID_XILINX_CRESAMPLE + 1) +/* Specify if the first line of video contains the Chroma information */ +#define V4L2_CID_XILINX_CRESAMPLE_CHROMA_PARITY (V4L2_CID_XILINX_CRESAMPLE + 2) + +/* + * Xilinx RGB2YUV Video IPs + */ + +#define V4L2_CID_XILINX_RGB2YUV (V4L2_CID_USER_BASE + 0xc040) + +/* Maximum Luma(Y) value */ +#define V4L2_CID_XILINX_RGB2YUV_YMAX (V4L2_CID_XILINX_RGB2YUV + 1) +/* Minimum Luma(Y) value */ +#define V4L2_CID_XILINX_RGB2YUV_YMIN (V4L2_CID_XILINX_RGB2YUV + 2) +/* Maximum Cb Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CBMAX (V4L2_CID_XILINX_RGB2YUV + 3) +/* Minimum Cb Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CBMIN (V4L2_CID_XILINX_RGB2YUV + 4) +/* Maximum Cr Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CRMAX (V4L2_CID_XILINX_RGB2YUV + 5) +/* Minimum Cr Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CRMIN (V4L2_CID_XILINX_RGB2YUV + 6) +/* The offset compensation value for Luma(Y) */ +#define V4L2_CID_XILINX_RGB2YUV_YOFFSET (V4L2_CID_XILINX_RGB2YUV + 7) +/* The offset compensation value for Cb Chroma */ +#define V4L2_CID_XILINX_RGB2YUV_CBOFFSET (V4L2_CID_XILINX_RGB2YUV + 8) +/* The offset compensation value for Cr Chroma */ +#define V4L2_CID_XILINX_RGB2YUV_CROFFSET (V4L2_CID_XILINX_RGB2YUV + 9) + +/* Y = CA * R + (1 - CA - CB) * G + CB * B */ + +/* CA coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_ACOEF (V4L2_CID_XILINX_RGB2YUV + 10) +/* CB coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_BCOEF (V4L2_CID_XILINX_RGB2YUV + 11) +/* CC coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_CCOEF (V4L2_CID_XILINX_RGB2YUV + 12) +/* CD coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_DCOEF (V4L2_CID_XILINX_RGB2YUV + 13) + +/* + * Xilinx HLS Video IP + */ + +#define V4L2_CID_XILINX_HLS (V4L2_CID_USER_BASE + 0xc060) + +/* The IP model */ +#define V4L2_CID_XILINX_HLS_MODEL (V4L2_CID_XILINX_HLS + 1) + +/* + * Xilinx MIPI CSI2 Rx Subsystem + */ + +/* Base ID */ +#define V4L2_CID_XILINX_MIPICSISS (V4L2_CID_USER_BASE + 0xc080) + +/* Active Lanes */ +#define V4L2_CID_XILINX_MIPICSISS_ACT_LANES (V4L2_CID_XILINX_MIPICSISS + 1) +/* Frames received since streaming is set */ +#define V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER (V4L2_CID_XILINX_MIPICSISS + 2) +/* Reset all event counters */ +#define V4L2_CID_XILINX_MIPICSISS_RESET_COUNTERS (V4L2_CID_XILINX_MIPICSISS + 3) + +/* + * Xilinx Gamma Correction IP + */ + +/* Base ID */ +#define V4L2_CID_XILINX_GAMMA_CORR (V4L2_CID_USER_BASE + 0xc0c0) +/* Adjust Red Gamma */ +#define V4L2_CID_XILINX_GAMMA_CORR_RED_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 1) +/* Adjust Blue Gamma */ +#define V4L2_CID_XILINX_GAMMA_CORR_BLUE_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 2) +/* Adjust Green Gamma */ +#define V4L2_CID_XILINX_GAMMA_CORR_GREEN_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 3) + +/* + * Xilinx Color Space Converter (CSC) VPSS + */ + +/* Base ID */ +#define V4L2_CID_XILINX_CSC (V4L2_CID_USER_BASE + 0xc0a0) +/* Adjust Brightness */ +#define V4L2_CID_XILINX_CSC_BRIGHTNESS (V4L2_CID_XILINX_CSC + 1) +/* Adjust Contrast */ +#define V4L2_CID_XILINX_CSC_CONTRAST (V4L2_CID_XILINX_CSC + 2) +/* Adjust Red Gain */ +#define V4L2_CID_XILINX_CSC_RED_GAIN (V4L2_CID_XILINX_CSC + 3) +/* Adjust Green Gain */ +#define V4L2_CID_XILINX_CSC_GREEN_GAIN (V4L2_CID_XILINX_CSC + 4) +/* Adjust Blue Gain */ +#define V4L2_CID_XILINX_CSC_BLUE_GAIN (V4L2_CID_XILINX_CSC + 5) + +/* + * Xilinx SDI Rx Subsystem + */ + +/* Base ID */ +#define V4L2_CID_XILINX_SDIRX (V4L2_CID_USER_BASE + 0xc100) + +/* Framer Control */ +#define V4L2_CID_XILINX_SDIRX_FRAMER (V4L2_CID_XILINX_SDIRX + 1) +/* Video Lock Window Control */ +#define V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW (V4L2_CID_XILINX_SDIRX + 2) +/* EDH Error Mask Control */ +#define V4L2_CID_XILINX_SDIRX_EDH_ERRCNT_ENABLE (V4L2_CID_XILINX_SDIRX + 3) +/* Mode search Control */ +#define V4L2_CID_XILINX_SDIRX_SEARCH_MODES (V4L2_CID_XILINX_SDIRX + 4) +/* Get Detected Mode control */ +#define V4L2_CID_XILINX_SDIRX_MODE_DETECT (V4L2_CID_XILINX_SDIRX + 5) +/* Get CRC error status */ +#define V4L2_CID_XILINX_SDIRX_CRC (V4L2_CID_XILINX_SDIRX + 6) +/* Get EDH error count control */ +#define V4L2_CID_XILINX_SDIRX_EDH_ERRCNT (V4L2_CID_XILINX_SDIRX + 7) +/* Get EDH status control */ +#define V4L2_CID_XILINX_SDIRX_EDH_STATUS (V4L2_CID_XILINX_SDIRX + 8) +/* Get Transport Interlaced status */ +#define V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED (V4L2_CID_XILINX_SDIRX + 9) +/* Get Active Streams count */ +#define V4L2_CID_XILINX_SDIRX_ACTIVE_STREAMS (V4L2_CID_XILINX_SDIRX + 10) +/* Is Mode 3GB */ +#define V4L2_CID_XILINX_SDIRX_IS_3GB (V4L2_CID_XILINX_SDIRX + 11) + +/* + * Xilinx VIP + */ + +/* Base ID */ +#define V4L2_CID_XILINX_VIP (V4L2_CID_USER_BASE + 0xc120) + +/* Low latency mode */ +#define V4L2_CID_XILINX_LOW_LATENCY (V4L2_CID_XILINX_VIP + 1) #endif /* __UAPI_XILINX_V4L2_CONTROLS_H__ */ diff --git a/include/uapi/linux/xilinx-v4l2-events.h b/include/uapi/linux/xilinx-v4l2-events.h new file mode 100644 index 000000000000..e31e998eba67 --- /dev/null +++ b/include/uapi/linux/xilinx-v4l2-events.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx V4L2 SCD Driver + * + * Copyright (C) 2017-2018 Xilinx, Inc. + * + * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> + * + */ + +#ifndef __UAPI_XILINX_V4L2_EVENTS_H__ +#define __UAPI_XILINX_V4L2_EVENTS_H__ + +#include <linux/videodev2.h> + +/* + * Events + * + * V4L2_EVENT_XLNXSCD: Scene Change Detection + */ +#define V4L2_EVENT_XLNXSCD_CLASS (V4L2_EVENT_PRIVATE_START | 0x300) +#define V4L2_EVENT_XLNXSCD (V4L2_EVENT_XLNXSCD_CLASS | 0x1) + +#endif /* __UAPI_XILINX_V4L2_EVENTS_H__ */ diff --git a/include/uapi/linux/xlnx_ctrl.h b/include/uapi/linux/xlnx_ctrl.h new file mode 100644 index 000000000000..35ff1fdbf65b --- /dev/null +++ b/include/uapi/linux/xlnx_ctrl.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Xilinx Controls Header + * + * Copyright (C) 2019 Xilinx, Inc. + * + * Contacts: Saurabh Sengar <saurabh.singh@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __UAPI_XLNX_CTRL_H__ +#define __UAPI_XLNX_CTRL_H__ + +#define XSET_FB_CAPTURE 16 +#define XSET_FB_CONFIGURE 17 +#define XSET_FB_ENABLE 18 +#define XSET_FB_DISABLE 19 +#define XSET_FB_RELEASE 20 +#define XSET_FB_ENABLE_SNGL 21 +#define XSET_FB_POLL 22 +#define XVPSS_SET_CONFIGURE 16 +#define XVPSS_SET_ENABLE 17 +#define XVPSS_SET_DISABLE 18 + +#endif /* __UAPI_XLNX_CTRL_H__ */ + diff --git a/include/uapi/linux/xlnxsync.h b/include/uapi/linux/xlnxsync.h new file mode 100644 index 000000000000..989b2f1ef93c --- /dev/null +++ b/include/uapi/linux/xlnxsync.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __XLNXSYNC_H__ +#define __XLNXSYNC_H__ + +/* Bit offset in channel status byte */ +/* x = channel */ +#define XLNXSYNC_CHX_FB0_MASK(x) BIT(0 + ((x) << 3)) +#define XLNXSYNC_CHX_FB1_MASK(x) BIT(1 + ((x) << 3)) +#define XLNXSYNC_CHX_FB2_MASK(x) BIT(2 + ((x) << 3)) +#define XLNXSYNC_CHX_ENB_MASK(x) BIT(3 + ((x) << 3)) +#define XLNXSYNC_CHX_SYNC_ERR_MASK(x) BIT(4 + ((x) << 3)) +#define XLNXSYNC_CHX_WDG_ERR_MASK(x) BIT(5 + ((x) << 3)) + +/* + * This is set in the fb_id or channel_id of struct xlnxsync_chan_config when + * configuring the channel. This makes the driver auto search for the free + * framebuffer or channel slot. + */ +#define XLNXSYNC_AUTO_SEARCH 0xFF + +#define XLNXSYNC_MAX_ENC_CHANNEL 4 +#define XLNXSYNC_MAX_DEC_CHANNEL 2 +#define XLNXSYNC_BUF_PER_CHANNEL 3 + +/** + * struct xlnxsync_chan_config - Synchronizer channel configuration struct + * @luma_start_address: Start address of Luma buffer + * @chroma_start_address: Start address of Chroma buffer + * @luma_end_address: End address of Luma buffer + * @chroma_end_address: End address of Chroma buffer + * @luma_margin: Margin for Luma buffer + * @chroma_margin: Margin for Chroma buffer + * @fb_id: Framebuffer index. Valid values 0/1/2/XLNXSYNC_AUTO_SEARCH + * @channel_id: Channel index to be configured. + * Valid 0..3 & XLNXSYNC_AUTO_SEARCH + * @ismono: Flag to indicate if buffer is Luma only. + * + * This structure contains the configuration for monitoring a particular + * framebuffer on a particular channel. + */ +struct xlnxsync_chan_config { + u64 luma_start_address; + u64 chroma_start_address; + u64 luma_end_address; + u64 chroma_end_address; + u32 luma_margin; + u32 chroma_margin; + u8 fb_id; + u8 channel_id; + u8 ismono; +}; + +/** + * struct xlnxsync_clr_err - Clear channel error + * @channel_id: Channel id whose error needs to be cleared + * @sync_err: Set this to clear sync error + * @wdg_err: Set this to clear watchdog error + */ +struct xlnxsync_clr_err { + u8 channel_id; + u8 sync_err; + u8 wdg_err; +}; + +/** + * struct xlnxsync_fbdone - Framebuffer Done + * @status: Framebuffer Done status + */ +struct xlnxsync_fbdone { + u8 status[XLNXSYNC_MAX_ENC_CHANNEL][XLNXSYNC_BUF_PER_CHANNEL]; +}; + +/** + * struct xlnxsync_config - Synchronizer IP configuration + * @encode: true if encoder type, false for decoder type + * @max_channels: Maximum channels this IP supports + */ +struct xlnxsync_config { + u8 encode; + u8 max_channels; +}; + +#define XLNXSYNC_MAGIC 'X' + +/* + * This ioctl is used to get the IP config (i.e. encode / decode) + * and max number of channels + */ +#define XLNXSYNC_GET_CFG _IOR(XLNXSYNC_MAGIC, 1,\ + struct xlnxsync_config *) +/* This ioctl is used to get the channel status */ +#define XLNXSYNC_GET_CHAN_STATUS _IOR(XLNXSYNC_MAGIC, 2, u32 *) +/* This is used to set the framebuffer address for a channel */ +#define XLNXSYNC_SET_CHAN_CONFIG _IOW(XLNXSYNC_MAGIC, 3,\ + struct xlnxsync_chan_config *) +/* Enable a channel. The argument is channel number between 0 and 3 */ +#define XLNXSYNC_CHAN_ENABLE _IOR(XLNXSYNC_MAGIC, 4, u8) +/* Enable a channel. The argument is channel number between 0 and 3 */ +#define XLNXSYNC_CHAN_DISABLE _IOR(XLNXSYNC_MAGIC, 5, u8) +/* This is used to clear the Sync and Watchdog errors for a channel */ +#define XLNXSYNC_CLR_CHAN_ERR _IOW(XLNXSYNC_MAGIC, 6,\ + struct xlnxsync_clr_err *) +/* This is used to get the framebuffer done status for a channel */ +#define XLNXSYNC_GET_CHAN_FBDONE_STAT _IOR(XLNXSYNC_MAGIC, 7,\ + struct xlnxsync_fbdone *) +/* This is used to clear the framebuffer done status for a channel */ +#define XLNXSYNC_CLR_CHAN_FBDONE_STAT _IOW(XLNXSYNC_MAGIC, 8,\ + struct xlnxsync_fbdone *) + +#endif diff --git a/include/uapi/linux/zocl_ioctl.h b/include/uapi/linux/zocl_ioctl.h new file mode 100644 index 000000000000..ee1f1e289cd8 --- /dev/null +++ b/include/uapi/linux/zocl_ioctl.h @@ -0,0 +1,125 @@ +/* + * A GEM style CMA backed memory manager for ZynQ based OpenCL accelerators. + * + * Copyright (C) 2016 Xilinx, Inc. All rights reserved. + * + * Authors: + * Sonal Santan <sonal.santan@xilinx.com> + * Umang Parekh <umang.parekh@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _XCL_ZOCL_IOCTL_H_ +#define _XCL_ZOCL_IOCTL_H_ + +enum { + DRM_ZOCL_CREATE_BO = 0, + DRM_ZOCL_MAP_BO, + DRM_ZOCL_SYNC_BO, + DRM_ZOCL_INFO_BO, + DRM_ZOCL_PWRITE_BO, + DRM_ZOCL_PREAD_BO, + DRM_ZOCL_NUM_IOCTLS +}; + +enum drm_zocl_sync_bo_dir { + DRM_ZOCL_SYNC_BO_TO_DEVICE, + DRM_ZOCL_SYNC_BO_FROM_DEVICE +}; + +#define DRM_ZOCL_BO_FLAGS_COHERENT 0x00000001 +#define DRM_ZOCL_BO_FLAGS_CMA 0x00000002 + +struct drm_zocl_create_bo { + uint64_t size; + uint32_t handle; + uint32_t flags; +}; + +struct drm_zocl_map_bo { + uint32_t handle; + uint32_t pad; + uint64_t offset; +}; + +/** + * struct drm_zocl_sync_bo - used for SYNQ_BO IOCTL + * @handle: GEM object handle + * @dir: DRM_ZOCL_SYNC_DIR_XXX + * @offset: Offset into the object to write to + * @size: Length of data to write + */ +struct drm_zocl_sync_bo { + uint32_t handle; + enum drm_zocl_sync_bo_dir dir; + uint64_t offset; + uint64_t size; +}; + +/** + * struct drm_zocl_info_bo - used for INFO_BO IOCTL + * @handle: GEM object handle + * @size: Size of BO + * @paddr: physical address + */ +struct drm_zocl_info_bo { + uint32_t handle; + uint64_t size; + uint64_t paddr; +}; + +/** + * struct drm_zocl_pwrite_bo - used for PWRITE_BO IOCTL + * @handle: GEM object handle + * @pad: Padding + * @offset: Offset into the object to write to + * @size: Length of data to write + * @data_ptr: Pointer to read the data from (pointers not 32/64 compatible) + */ +struct drm_zocl_pwrite_bo { + uint32_t handle; + uint32_t pad; + uint64_t offset; + uint64_t size; + uint64_t data_ptr; +}; + +/** + * struct drm_zocl_pread_bo - used for PREAD_BO IOCTL + * @handle: GEM object handle + * @pad: Padding + * @offset: Offset into the object to read from + * @size: Length of data to wrreadite + * @data_ptr: Pointer to write the data into (pointers not 32/64 compatible) + */ +struct drm_zocl_pread_bo { + uint32_t handle; + uint32_t pad; + uint64_t offset; + uint64_t size; + uint64_t data_ptr; +}; + +#define DRM_IOCTL_ZOCL_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_CREATE_BO, \ + struct drm_zocl_create_bo) +#define DRM_IOCTL_ZOCL_MAP_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_MAP_BO, struct drm_zocl_map_bo) +#define DRM_IOCTL_ZOCL_SYNC_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_SYNC_BO, struct drm_zocl_sync_bo) +#define DRM_IOCTL_ZOCL_INFO_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_INFO_BO, struct drm_zocl_info_bo) +#define DRM_IOCTL_ZOCL_PWRITE_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_PWRITE_BO, \ + struct drm_zocl_pwrite_bo) +#define DRM_IOCTL_ZOCL_PREAD_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_PREAD_BO, struct drm_zocl_pread_bo) +#endif diff --git a/include/uapi/misc/xilinx_sdfec.h b/include/uapi/misc/xilinx_sdfec.h new file mode 100644 index 000000000000..13c4a9f9c360 --- /dev/null +++ b/include/uapi/misc/xilinx_sdfec.h @@ -0,0 +1,470 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Xilinx SD-FEC + * + * Copyright (C) 2016 - 2017 Xilinx, Inc. + * + * Description: + * This driver is developed for SDFEC16 IP. It provides a char device + * in sysfs and supports file operations like open(), close() and ioctl(). + */ +#ifndef __XILINX_SDFEC_H__ +#define __XILINX_SDFEC_H__ + +/* Shared LDPC Tables */ +#define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000) +#define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x103FC) +#define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000) +#define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x18FFC) +#define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000) +#define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x27FFC) + +/** + * enum xsdfec_code - Code Type. + * @XSDFEC_TURBO_CODE: Driver is configured for Turbo mode. + * @XSDFEC_LDPC_CODE: Driver is configured for LDPC mode. + * + * This enum is used to indicate the mode of the driver. The mode is determined + * by checking which codes are set in the driver. Note that the mode cannot be + * changed by the driver. + */ +enum xsdfec_code { + XSDFEC_TURBO_CODE = 0, + XSDFEC_LDPC_CODE, +}; + +/** + * enum xsdfec_order - Order + * @XSDFEC_MAINTAIN_ORDER: Maintain order execution of blocks. + * @XSDFEC_OUT_OF_ORDER: Out-of-order execution of blocks. + * + * This enum is used to indicate whether the order of blocks can change from + * input to output. + */ +enum xsdfec_order { + XSDFEC_MAINTAIN_ORDER = 0, + XSDFEC_OUT_OF_ORDER, +}; + +/** + * enum xsdfec_turbo_alg - Turbo Algorithm Type. + * @XSDFEC_MAX_SCALE: Max Log-Map algorithm with extrinsic scaling. When + * scaling is set to this is equivalent to the Max Log-Map + * algorithm. + * @XSDFEC_MAX_STAR: Log-Map algorithm. + * @XSDFEC_TURBO_ALG_MAX: Used to indicate out of bound Turbo algorithms. + * + * This enum specifies which Turbo Decode algorithm is in use. + */ +enum xsdfec_turbo_alg { + XSDFEC_MAX_SCALE = 0, + XSDFEC_MAX_STAR, + XSDFEC_TURBO_ALG_MAX, +}; + +/** + * enum xsdfec_state - State. + * @XSDFEC_INIT: Driver is initialized. + * @XSDFEC_STARTED: Driver is started. + * @XSDFEC_STOPPED: Driver is stopped. + * @XSDFEC_NEEDS_RESET: Driver needs to be reset. + * @XSDFEC_PL_RECONFIGURE: Programmable Logic needs to be recofigured. + * + * This enum is used to indicate the state of the driver. + */ +enum xsdfec_state { + XSDFEC_INIT = 0, + XSDFEC_STARTED, + XSDFEC_STOPPED, + XSDFEC_NEEDS_RESET, + XSDFEC_PL_RECONFIGURE, +}; + +/** + * enum xsdfec_axis_width - AXIS_WIDTH.DIN Setting for 128-bit width. + * @XSDFEC_1x128b: DIN data input stream consists of a 128-bit lane + * @XSDFEC_2x128b: DIN data input stream consists of two 128-bit lanes + * @XSDFEC_4x128b: DIN data input stream consists of four 128-bit lanes + * + * This enum is used to indicate the AXIS_WIDTH.DIN setting for 128-bit width. + * The number of lanes of the DIN data input stream depends upon the + * AXIS_WIDTH.DIN parameter. + */ +enum xsdfec_axis_width { + XSDFEC_1x128b = 1, + XSDFEC_2x128b = 2, + XSDFEC_4x128b = 4, +}; + +/** + * enum xsdfec_axis_word_include - Words Configuration. + * @XSDFEC_FIXED_VALUE: Fixed, the DIN_WORDS AXI4-Stream interface is removed + * from the IP instance and is driven with the specified + * number of words. + * @XSDFEC_IN_BLOCK: In Block, configures the IP instance to expect a single + * DIN_WORDS value per input code block. The DIN_WORDS + * interface is present. + * @XSDFEC_PER_AXI_TRANSACTION: Per Transaction, configures the IP instance to + * expect one DIN_WORDS value per input transaction on the DIN interface. The + * DIN_WORDS interface is present. + * @XSDFEC_AXIS_WORDS_INCLUDE_MAX: Used to indicate out of bound Words + * Configurations. + * + * This enum is used to specify the DIN_WORDS configuration. + */ +enum xsdfec_axis_word_include { + XSDFEC_FIXED_VALUE = 0, + XSDFEC_IN_BLOCK, + XSDFEC_PER_AXI_TRANSACTION, + XSDFEC_AXIS_WORDS_INCLUDE_MAX, +}; + +/** + * struct xsdfec_turbo - User data for Turbo codes. + * @alg: Specifies which Turbo decode algorithm to use + * @scale: Specifies the extrinsic scaling to apply when the Max Scale algorithm + * has been selected + * + * Turbo code structure to communicate parameters to XSDFEC driver. + */ +struct xsdfec_turbo { + enum xsdfec_turbo_alg alg; + u8 scale; +}; + +/** + * struct xsdfec_ldpc_params - User data for LDPC codes. + * @n: Number of code word bits + * @k: Number of information bits + * @psize: Size of sub-matrix + * @nlayers: Number of layers in code + * @nqc: Quasi Cyclic Number + * @nmqc: Number of M-sized QC operations in parity check matrix + * @nm: Number of M-size vectors in N + * @norm_type: Normalization required or not + * @no_packing: Determines if multiple QC ops should be performed + * @special_qc: Sub-Matrix property for Circulant weight > 0 + * @no_final_parity: Decide if final parity check needs to be performed + * @max_schedule: Experimental code word scheduling limit + * @sc_off: SC offset + * @la_off: LA offset + * @qc_off: QC offset + * @sc_table: SC Table + * @la_table: LA Table + * @qc_table: QC Table + * @code_id: LDPC Code + * + * This structure describes the LDPC code that is passed to the driver by the + * application. + */ +struct xsdfec_ldpc_params { + u32 n; + u32 k; + u32 psize; + u32 nlayers; + u32 nqc; + u32 nmqc; + u32 nm; + u32 norm_type; + u32 no_packing; + u32 special_qc; + u32 no_final_parity; + u32 max_schedule; + u32 sc_off; + u32 la_off; + u32 qc_off; + u32 sc_table[XSDFEC_LDPC_SC_TABLE_ADDR_HIGH - + XSDFEC_LDPC_SC_TABLE_ADDR_BASE]; + u32 la_table[XSDFEC_LDPC_LA_TABLE_ADDR_HIGH - + XSDFEC_LDPC_LA_TABLE_ADDR_BASE]; + u32 qc_table[XSDFEC_LDPC_QC_TABLE_ADDR_HIGH - + XSDFEC_LDPC_QC_TABLE_ADDR_BASE]; + u16 code_id; +}; + +/** + * struct xsdfec_status - Status of SD-FEC core. + * @fec_id: ID of SD-FEC instance. ID is limited to the number of active + * SD-FEC's in the FPGA and is related to the driver instance + * Minor number. + * @state: State of the SD-FEC core + * @activity: Describes if the SD-FEC instance is Active + */ +struct xsdfec_status { + s32 fec_id; + enum xsdfec_state state; + bool activity; +}; + +/** + * struct xsdfec_irq - Enabling or Disabling Interrupts. + * @enable_isr: If true enables the ISR + * @enable_ecc_isr: If true enables the ECC ISR + */ +struct xsdfec_irq { + bool enable_isr; + bool enable_ecc_isr; +}; + +/** + * struct xsdfec_config - Configuration of SD-FEC core. + * @fec_id: ID of SD-FEC instance. ID is limited to the number of active + * SD-FEC's in the FPGA and is related to the driver instance + * Minor number. + * @code: The codes being used by the SD-FEC instance + * @order: Order of Operation + * @bypass: Is the core being bypassed + * @code_wr_protect: Is write protection of LDPC codes enabled + * @din_width: Width of the DIN AXI4-Stream + * @din_word_include: How DIN_WORDS are inputted + * @dout_width: Width of the DOUT AXI4-Stream + * @dout_word_include: HOW DOUT_WORDS are outputted + * @irq: Enabling or disabling interrupts + */ +struct xsdfec_config { + s32 fec_id; + enum xsdfec_code code; + enum xsdfec_order order; + bool bypass; + bool code_wr_protect; + enum xsdfec_axis_width din_width; + enum xsdfec_axis_word_include din_word_include; + enum xsdfec_axis_width dout_width; + enum xsdfec_axis_word_include dout_word_include; + struct xsdfec_irq irq; +}; + +/** + * struct xsdfec_stats - Stats retrived by ioctl XSDFEC_GET_STATS. Used + * to buffer atomic_t variables from struct + * xsdfec_dev. Counts are accumulated until + * the user clears them. + * @isr_err_count: Count of ISR errors + * @cecc_count: Count of Correctable ECC errors (SBE) + * @uecc_count: Count of Uncorrectable ECC errors (MBE) + */ +struct xsdfec_stats { + u32 isr_err_count; + u32 cecc_count; + u32 uecc_count; +}; + +/** + * struct xsdfec_ldpc_param_table_sizes - Used to store sizes of SD-FEC table + * entries for an individual LPDC code + * parameter. + * @sc_size: Size of SC table used + * @la_size: Size of LA table used + * @qc_size: Size of QC table used + */ +struct xsdfec_ldpc_param_table_sizes { + u32 sc_size; + u32 la_size; + u32 qc_size; +}; + +/** + * xsdfec_calculate_shared_ldpc_table_entry_size - Calculates shared code + * table sizes. + * @ldpc: Pointer to the LPDC Code Parameters + * @table_sizes: Pointer to structure containing the calculated table sizes + * + * Calculates the size of shared LDPC code tables used for a specified LPDC code + * parameters. + */ +inline void xsdfec_calculate_shared_ldpc_table_entry_size( + struct xsdfec_ldpc_params *ldpc, + struct xsdfec_ldpc_param_table_sizes *table_sizes) +{ + /* Calculate the sc_size in 32 bit words */ + table_sizes->sc_size = (ldpc->nlayers + 3) >> 2; + /* Calculate the la_size in 256 bit words */ + table_sizes->la_size = ((ldpc->nlayers << 2) + 15) >> 4; + /* Calculate the qc_size in 256 bit words */ + table_sizes->qc_size = ((ldpc->nqc << 2) + 15) >> 4; +} + +/* + * XSDFEC IOCTL List + */ +#define XSDFEC_MAGIC 'f' +/** + * DOC: XSDFEC_START_DEV + * + * @Description + * + * ioctl to start SD-FEC core + * + * This fails if the XSDFEC_SET_ORDER ioctl has not been previously called + */ +#define XSDFEC_START_DEV _IO(XSDFEC_MAGIC, 0) +/** + * DOC: XSDFEC_STOP_DEV + * + * @Description + * + * ioctl to stop the SD-FEC core + */ +#define XSDFEC_STOP_DEV _IO(XSDFEC_MAGIC, 1) +/** + * DOC: XSDFEC_GET_STATUS + * + * @Description + * + * ioctl that returns status of SD-FEC core + */ +#define XSDFEC_GET_STATUS _IOR(XSDFEC_MAGIC, 2, struct xsdfec_status *) +/** + * DOC: XSDFEC_SET_IRQ + * @Parameters + * + * @struct xsdfec_irq * + * Pointer to the &struct xsdfec_irq that contains the interrupt settings + * for the SD-FEC core + * + * @Description + * + * ioctl to enable or disable irq + */ +#define XSDFEC_SET_IRQ _IOW(XSDFEC_MAGIC, 3, struct xsdfec_irq *) +/** + * DOC: XSDFEC_SET_TURBO + * @Parameters + * + * @struct xsdfec_turbo * + * Pointer to the &struct xsdfec_turbo that contains the Turbo decode + * settings for the SD-FEC core + * + * @Description + * + * ioctl that sets the SD-FEC Turbo parameter values + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_SET_TURBO _IOW(XSDFEC_MAGIC, 4, struct xsdfec_turbo *) +/** + * DOC: XSDFEC_ADD_LDPC_CODE_PARAMS + * @Parameters + * + * @struct xsdfec_ldpc_params * + * Pointer to the &struct xsdfec_ldpc_params that contains the LDPC code + * parameters to be added to the SD-FEC Block + * + * @Description + * ioctl to add an LDPC code to the SD-FEC LDPC codes + * + * This can only be used when: + * + * - Driver is in the XSDFEC_STOPPED state + * + * - SD-FEC core is configured as LPDC + * + * - SD-FEC Code Write Protection is disabled + */ +#define XSDFEC_ADD_LDPC_CODE_PARAMS \ + _IOW(XSDFEC_MAGIC, 5, struct xsdfec_ldpc_params *) +/** + * DOC: XSDFEC_GET_CONFIG + * @Parameters + * + * @struct xsdfec_config * + * Pointer to the &struct xsdfec_config that contains the current + * configuration settings of the SD-FEC Block + * + * @Description + * + * ioctl that returns SD-FEC core configuration + */ +#define XSDFEC_GET_CONFIG _IOR(XSDFEC_MAGIC, 6, struct xsdfec_config *) +/** + * DOC: XSDFEC_GET_TURBO + * @Parameters + * + * @struct xsdfec_turbo * + * Pointer to the &struct xsdfec_turbo that contains the current Turbo + * decode settings of the SD-FEC Block + * + * @Description + * + * ioctl that returns SD-FEC turbo param values + */ +#define XSDFEC_GET_TURBO _IOR(XSDFEC_MAGIC, 7, struct xsdfec_turbo *) +/** + * DOC: XSDFEC_SET_ORDER + * @Parameters + * + * @struct unsigned long * + * Pointer to the unsigned long that contains a value from the + * @enum xsdfec_order + * + * @Description + * + * ioctl that sets order, if order of blocks can change from input to output + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_SET_ORDER _IOW(XSDFEC_MAGIC, 8, unsigned long *) +/** + * DOC: XSDFEC_SET_BYPASS + * @Parameters + * + * @struct bool * + * Pointer to bool that sets the bypass value, where false results in + * normal operation and false results in the SD-FEC performing the + * configured operations (same number of cycles) but output data matches + * the input data + * + * @Description + * + * ioctl that sets bypass. + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_SET_BYPASS _IOW(XSDFEC_MAGIC, 9, bool *) +/** + * DOC: XSDFEC_IS_ACTIVE + * @Parameters + * + * @struct bool * + * Pointer to bool that returns true if the SD-FEC is processing data + * + * @Description + * + * ioctl that determines if SD-FEC is processing data + */ +#define XSDFEC_IS_ACTIVE _IOR(XSDFEC_MAGIC, 10, bool *) +/** + * DOC: XSDFEC_CLEAR_STATS + * + * @Description + * + * ioctl that clears error stats collected during interrupts + */ +#define XSDFEC_CLEAR_STATS _IO(XSDFEC_MAGIC, 11) +/** + * DOC: XSDFEC_GET_STATS + * @Parameters + * + * @struct xsdfec_stats * + * Pointer to the &struct xsdfec_stats that will contain the updated stats + * values + * + * @Description + * + * ioctl that returns SD-FEC core stats + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_GET_STATS _IOR(XSDFEC_MAGIC, 12, struct xsdfec_stats *) +/** + * DOC: XSDFEC_SET_DEFAULT_CONFIG + * + * @Description + * + * ioctl that returns SD-FEC core to default config, use after a reset + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_SET_DEFAULT_CONFIG _IO(XSDFEC_MAGIC, 13) + +#endif /* __XILINX_SDFEC_H__ */ |