diff options
Diffstat (limited to 'include/uapi')
| -rw-r--r-- | include/uapi/drm/drm_fourcc.h | 15 | ||||
| -rw-r--r-- | include/uapi/drm/drm_mode.h | 2 | ||||
| -rw-r--r-- | include/uapi/linux/if_alg.h | 1 | ||||
| -rw-r--r-- | include/uapi/linux/media-bus-format.h | 16 | ||||
| -rw-r--r-- | include/uapi/linux/uio/uio.h | 65 | ||||
| -rw-r--r-- | include/uapi/linux/v4l2-mediabus.h | 3 | ||||
| -rw-r--r-- | include/uapi/linux/v4l2-subdev.h | 23 | ||||
| -rw-r--r-- | include/uapi/linux/videodev2.h | 29 | ||||
| -rw-r--r-- | include/uapi/linux/xilinx-csi2rxss.h | 18 | ||||
| -rw-r--r-- | include/uapi/linux/xilinx-hls.h | 21 | ||||
| -rw-r--r-- | include/uapi/linux/xilinx-sdirxss.h | 66 | ||||
| -rw-r--r-- | include/uapi/linux/xilinx-v4l2-controls.h | 141 | ||||
| -rw-r--r-- | include/uapi/linux/xilinx-v4l2-events.h | 24 | ||||
| -rw-r--r-- | include/uapi/linux/xlnx_ctrl.h | 34 | ||||
| -rw-r--r-- | include/uapi/linux/xlnxsync.h | 111 | ||||
| -rw-r--r-- | include/uapi/linux/zocl_ioctl.h | 125 | ||||
| -rw-r--r-- | include/uapi/misc/xilinx_sdfec.h | 470 |
17 files changed, 1160 insertions, 4 deletions
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3f987a..3193c3c3f5c0 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -145,6 +145,14 @@ extern "C" { #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ /* + * 2 plane 10 bit per component YCbCr + * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian + * index 1 = Cb:Cr plane, [63:0] x:Cb2:Cr2:Cb1:x:Cr1:Cb0:Cr0 2:10:10:10:2:10:10:10 little endian + */ +#define DRM_FORMAT_XV15 fourcc_code('X', 'V', '1', '5') /* 2x2 subsampled Cb:Cr plane 2:10:10:10 */ +#define DRM_FORMAT_XV20 fourcc_code('X', 'V', '2', '0') /* 2x1 subsampled Cb:Cr plane 2:10:10:10 */ + +/* * Floating point 64bpp RGB * IEEE 754-2008 binary16 half-precision float * [15:0] sign:exponent:mantissa 1:5:10 @@ -209,6 +217,13 @@ extern "C" { #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8') #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0') +#define DRM_FORMAT_AVUY fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */ +#define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', '2', '4') /* [31:0] x:Cr:Cb:Y 8:8:8:8 little endian */ +#define DRM_FORMAT_XVUY2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] x:Cr:Cb:Y 2:10:10:10 little endian */ + +/* Grey scale */ +#define DRM_FORMAT_Y8 fourcc_code('G', 'R', 'E', 'Y') /* 8 Greyscale */ +#define DRM_FORMAT_Y10 fourcc_code('Y', '1', '0', ' ') /* 10 Greyscale */ /* * 2 plane RGB + A * index 0 = RGB plane, same format as the corresponding non _A8 format has diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 83cd1636b9be..b35aebf3f8d1 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -475,6 +475,8 @@ struct drm_mode_fb_cmd { #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ #define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ +#define DRM_MODE_FB_ALTERNATE_TOP (1<<2) /* for alternate top field */ +#define DRM_MODE_FB_ALTERNATE_BOTTOM (1<<3) /* for alternate bottom field */ struct drm_mode_fb_cmd2 { __u32 fb_id; diff --git a/include/uapi/linux/if_alg.h b/include/uapi/linux/if_alg.h index bc2bcdec377b..aa31b18ebf0a 100644 --- a/include/uapi/linux/if_alg.h +++ b/include/uapi/linux/if_alg.h @@ -35,6 +35,7 @@ struct af_alg_iv { #define ALG_SET_OP 3 #define ALG_SET_AEAD_ASSOCLEN 4 #define ALG_SET_AEAD_AUTHSIZE 5 +#define ALG_SET_KEY_TYPE 6 /* Operations */ #define ALG_OP_DECRYPT 0 diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index 2a6b253cfb05..7e75f4d8319b 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -34,7 +34,7 @@ #define MEDIA_BUS_FMT_FIXED 0x0001 -/* RGB - next is 0x101c */ +/* RGB - next is 0x101e */ #define MEDIA_BUS_FMT_RGB444_1X12 0x1016 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 @@ -62,8 +62,11 @@ #define MEDIA_BUS_FMT_RGB101010_1X30 0x1018 #define MEDIA_BUS_FMT_RGB121212_1X36 0x1019 #define MEDIA_BUS_FMT_RGB161616_1X48 0x101a +#define MEDIA_BUS_FMT_RBG101010_1X30 0x101b +#define MEDIA_BUS_FMT_RBG121212_1X36 0x101c +#define MEDIA_BUS_FMT_RBG161616_1X48 0x101d -/* YUV (including grey) - next is 0x202d */ +/* YUV (including grey) - next is 0x2035 */ #define MEDIA_BUS_FMT_Y8_1X8 0x2001 #define MEDIA_BUS_FMT_UV8_1X8 0x2015 #define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 @@ -80,11 +83,13 @@ #define MEDIA_BUS_FMT_VYUY10_2X10 0x2019 #define MEDIA_BUS_FMT_YUYV10_2X10 0x200b #define MEDIA_BUS_FMT_YVYU10_2X10 0x200c +#define MEDIA_BUS_FMT_VYYUYY10_4X20 0x2031 #define MEDIA_BUS_FMT_Y12_1X12 0x2013 #define MEDIA_BUS_FMT_UYVY12_2X12 0x201c #define MEDIA_BUS_FMT_VYUY12_2X12 0x201d #define MEDIA_BUS_FMT_YUYV12_2X12 0x201e #define MEDIA_BUS_FMT_YVYU12_2X12 0x201f +#define MEDIA_BUS_FMT_VUY12_1X36 0x2033 #define MEDIA_BUS_FMT_UYVY8_1X16 0x200f #define MEDIA_BUS_FMT_VYUY8_1X16 0x2010 #define MEDIA_BUS_FMT_YUYV8_1X16 0x2011 @@ -102,12 +107,19 @@ #define MEDIA_BUS_FMT_YUYV12_1X24 0x2022 #define MEDIA_BUS_FMT_YVYU12_1X24 0x2023 #define MEDIA_BUS_FMT_YUV10_1X30 0x2016 +#define MEDIA_BUS_FMT_VUY10_1X30 0x2032 #define MEDIA_BUS_FMT_UYYVYY10_0_5X30 0x2027 #define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 #define MEDIA_BUS_FMT_UYYVYY12_0_5X36 0x2028 #define MEDIA_BUS_FMT_YUV12_1X36 0x2029 #define MEDIA_BUS_FMT_YUV16_1X48 0x202a +#define MEDIA_BUS_FMT_VUY16_1X48 0x2034 #define MEDIA_BUS_FMT_UYYVYY16_0_5X48 0x202b +#define MEDIA_BUS_FMT_VYYUYY8_1X24 0x202c +#define MEDIA_BUS_FMT_Y16_1X16 0x202d +#define MEDIA_BUS_FMT_UYYVYY12_4X24 0x202e +#define MEDIA_BUS_FMT_UYYVYY16_4X32 0x202f +#define MEDIA_BUS_FMT_UYVY16_2X32 0x2030 /* Bayer - next is 0x3021 */ #define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001 diff --git a/include/uapi/linux/uio/uio.h b/include/uapi/linux/uio/uio.h new file mode 100644 index 000000000000..db92d311c85f --- /dev/null +++ b/include/uapi/linux/uio/uio.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * The header for UIO driver + * + * Copyright (C) 2019 Xilinx, Inc. + * + * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com> + */ + +#ifndef _UAPI_UIO_UIO_H_ +#define _UAPI_UIO_UIO_H_ + +#include <linux/ioctl.h> +#include <linux/types.h> + +/** + * enum uio_dmabuf_dir - list of dma directions for mapping management + * @UIO_DMABUF_DIR_BIDIR: Bidirectional DMA. To and from device + * @UIO_DMABUF_DIR_TO_DEV: DMA to device + * @UIO_DMABUF_DIR_FROM_DEV: DMA from device + * @UIO_DMABUF_DIR_NONE: Direction not specified + */ +enum uio_dmabuf_dir { + UIO_DMABUF_DIR_BIDIR = 1, + UIO_DMABUF_DIR_TO_DEV = 2, + UIO_DMABUF_DIR_FROM_DEV = 3, + UIO_DMABUF_DIR_NONE = 4, +}; + +/** + * struct uio_dmabuf_args - arguments from userspace to map / unmap dmabuf + * @dbuf_fd: The fd or dma buf + * @dma_addr: The dma address of dmabuf @dbuf_fd + * @size: The size of dmabuf @dbuf_fd + * @dir: direction of dma transfer of dmabuf @dbuf_fd + */ +struct uio_dmabuf_args { + __s32 dbuf_fd; + __u64 dma_addr; + __u64 size; + __u8 dir; +}; + +#define UIO_IOC_BASE 'U' + +/** + * DOC: UIO_IOC_MAP_DMABUF - Map the dma buf to userspace uio application + * + * This takes uio_dmabuf_args, and maps the given dmabuf @dbuf_fd and returns + * information to userspace. + * FIXME: This is experimental and may change at any time. Don't consider this + * as stable ABI. + */ +#define UIO_IOC_MAP_DMABUF _IOWR(UIO_IOC_BASE, 0x1, struct uio_dmabuf_args) + +/** + * DOC: UIO_IOC_UNMAP_DMABUF - Unmap the dma buf + * + * This takes uio_dmabuf_args, and unmaps the previous mapped dmabuf @dbuf_fd. + * FIXME: This is experimental and may change at any time. Don't consider this + * as stable ABI. + */ +#define UIO_IOC_UNMAP_DMABUF _IOWR(UIO_IOC_BASE, 0x2, struct uio_dmabuf_args) + +#endif diff --git a/include/uapi/linux/v4l2-mediabus.h b/include/uapi/linux/v4l2-mediabus.h index 123a231001a8..325c985ed06f 100644 --- a/include/uapi/linux/v4l2-mediabus.h +++ b/include/uapi/linux/v4l2-mediabus.h @@ -68,6 +68,8 @@ enum v4l2_mbus_pixelcode { V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB888_2X12_BE), V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB888_2X12_LE), V4L2_MBUS_FROM_MEDIA_BUS_FMT(ARGB8888_1X32), + V4L2_MBUS_FROM_MEDIA_BUS_FMT(RBG888_1X24), + V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB888_1X32_PADHI), V4L2_MBUS_FROM_MEDIA_BUS_FMT(Y8_1X8), V4L2_MBUS_FROM_MEDIA_BUS_FMT(UV8_1X8), @@ -104,6 +106,7 @@ enum v4l2_mbus_pixelcode { V4L2_MBUS_FROM_MEDIA_BUS_FMT(VYUY12_1X24), V4L2_MBUS_FROM_MEDIA_BUS_FMT(YUYV12_1X24), V4L2_MBUS_FROM_MEDIA_BUS_FMT(YVYU12_1X24), + V4L2_MBUS_FROM_MEDIA_BUS_FMT(VUY8_1X24), V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR8_1X8), V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGBRG8_1X8), diff --git a/include/uapi/linux/v4l2-subdev.h b/include/uapi/linux/v4l2-subdev.h index 03970ce30741..b76f9b4afe05 100644 --- a/include/uapi/linux/v4l2-subdev.h +++ b/include/uapi/linux/v4l2-subdev.h @@ -155,6 +155,27 @@ struct v4l2_subdev_selection { __u32 reserved[8]; }; + +/** + * struct v4l2_subdev_route - A signal route inside a subdev + * @sink: the sink pad + * @source: the source pad + */ +struct v4l2_subdev_route { + __u32 sink; + __u32 source; +}; + +/** + * struct v4l2_subdev_routing - Routing information + * @num_routes: the total number of routes in the routes array + * @routes: the routes array + */ +struct v4l2_subdev_routing { + __u32 num_routes; + struct v4l2_subdev_route *routes; +}; + /* Backwards compatibility define --- to be removed */ #define v4l2_subdev_edid v4l2_edid @@ -181,5 +202,7 @@ struct v4l2_subdev_selection { #define VIDIOC_SUBDEV_ENUM_DV_TIMINGS _IOWR('V', 98, struct v4l2_enum_dv_timings) #define VIDIOC_SUBDEV_QUERY_DV_TIMINGS _IOR('V', 99, struct v4l2_dv_timings) #define VIDIOC_SUBDEV_DV_TIMINGS_CAP _IOWR('V', 100, struct v4l2_dv_timings_cap) +#define VIDIOC_SUBDEV_G_ROUTING _IOWR('V', 38, struct v4l2_subdev_routing) +#define VIDIOC_SUBDEV_S_ROUTING _IOWR('V', 39, struct v4l2_subdev_routing) #endif diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index dcd776e77442..b7f1bcaf37ec 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -546,20 +546,25 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32 BGR-8-8-8-8 */ #define V4L2_PIX_FMT_ABGR32 v4l2_fourcc('A', 'R', '2', '4') /* 32 BGRA-8-8-8-8 */ #define V4L2_PIX_FMT_XBGR32 v4l2_fourcc('X', 'R', '2', '4') /* 32 BGRX-8-8-8-8 */ -#define V4L2_PIX_FMT_BGRA32 v4l2_fourcc('R', 'A', '2', '4') /* 32 ABGR-8-8-8-8 */ -#define V4L2_PIX_FMT_BGRX32 v4l2_fourcc('R', 'X', '2', '4') /* 32 XBGR-8-8-8-8 */ #define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R', 'G', 'B', '4') /* 32 RGB-8-8-8-8 */ #define V4L2_PIX_FMT_RGBA32 v4l2_fourcc('A', 'B', '2', '4') /* 32 RGBA-8-8-8-8 */ #define V4L2_PIX_FMT_RGBX32 v4l2_fourcc('X', 'B', '2', '4') /* 32 RGBX-8-8-8-8 */ #define V4L2_PIX_FMT_ARGB32 v4l2_fourcc('B', 'A', '2', '4') /* 32 ARGB-8-8-8-8 */ +#define V4L2_PIX_FMT_BGRA32 v4l2_fourcc('A', 'B', 'G', 'R') /* 32 ABGR-8-8-8-8 */ #define V4L2_PIX_FMT_XRGB32 v4l2_fourcc('B', 'X', '2', '4') /* 32 XRGB-8-8-8-8 */ +#define V4L2_PIX_FMT_BGRX32 v4l2_fourcc('X', 'B', 'G', 'R') /* 32 XBGR-8-8-8-8 */ +#define V4L2_PIX_FMT_XBGR30 v4l2_fourcc('R', 'X', '3', '0') /* 32 XBGR-2-10-10-10 */ +#define V4L2_PIX_FMT_XBGR40 v4l2_fourcc('R', 'X', '4', '0') /* 40 XBGR-4-12-12-12 */ +#define V4L2_PIX_FMT_BGR48 v4l2_fourcc('R', 'G', '4', '8') /* 32 BGR-16-16-16 */ /* Grey formats */ #define V4L2_PIX_FMT_GREY v4l2_fourcc('G', 'R', 'E', 'Y') /* 8 Greyscale */ #define V4L2_PIX_FMT_Y4 v4l2_fourcc('Y', '0', '4', ' ') /* 4 Greyscale */ #define V4L2_PIX_FMT_Y6 v4l2_fourcc('Y', '0', '6', ' ') /* 6 Greyscale */ #define V4L2_PIX_FMT_Y10 v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */ +#define V4L2_PIX_FMT_XY10 v4l2_fourcc('X', 'Y', '1', '0') /* 10 Greyscale 2-10-10-10 */ #define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */ +#define V4L2_PIX_FMT_XY12 v4l2_fourcc('X', 'Y', '1', '2') /* 12 Greyscale 4-12-12-12 */ #define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */ #define V4L2_PIX_FMT_Y16_BE v4l2_fourcc_be('Y', '1', '6', ' ') /* 16 Greyscale BE */ @@ -581,6 +586,9 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_VYUY v4l2_fourcc('V', 'Y', 'U', 'Y') /* 16 YUV 4:2:2 */ #define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y', '4', '1', 'P') /* 12 YUV 4:1:1 */ #define V4L2_PIX_FMT_YUV444 v4l2_fourcc('Y', '4', '4', '4') /* 16 xxxxyyyy uuuuvvvv */ +#define V4L2_PIX_FMT_XVUY32 v4l2_fourcc('X', 'V', '3', '2') /* 32 XVUY 8:8:8:8 */ +#define V4L2_PIX_FMT_AVUY32 v4l2_fourcc('A', 'V', '3', '2') /* 32 AVUY 8:8:8:8 */ +#define V4L2_PIX_FMT_VUY24 v4l2_fourcc('V', 'U', '2', '4') /* 24 VUY 8:8:8 */ #define V4L2_PIX_FMT_YUV555 v4l2_fourcc('Y', 'U', 'V', 'O') /* 16 YUV-5-5-5 */ #define V4L2_PIX_FMT_YUV565 v4l2_fourcc('Y', 'U', 'V', 'P') /* 16 YUV-5-6-5 */ #define V4L2_PIX_FMT_YUV32 v4l2_fourcc('Y', 'U', 'V', '4') /* 32 YUV-8-8-8-8 */ @@ -591,6 +599,7 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */ #define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ #define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */ +#define V4L2_PIX_FMT_XVUY10 v4l2_fourcc('X', '4', '1', '0') /* 32 XVUY 2-10-10-10 */ /* two planes -- one Y, one Cr + Cb interleaved */ #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ @@ -599,6 +608,14 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ +#define V4L2_PIX_FMT_XV20 v4l2_fourcc('X', 'V', '2', '0') /* 32 XY/UV 4:2:2 10-bit */ +#define V4L2_PIX_FMT_XV15 v4l2_fourcc('X', 'V', '1', '5') /* 32 XY/UV 4:2:0 10-bit */ +#define V4L2_PIX_FMT_X012 v4l2_fourcc('X', '0', '1', '2') /* 40 XY/UV 4:2:0 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X212 v4l2_fourcc('X', '2', '1', '2') /* 40 XY/UV 4:2:2 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X412 v4l2_fourcc('X', '4', '1', '2') /* 40 XY/UV 4:4:4 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X016 v4l2_fourcc('X', '0', '1', '6') /* 32 XY/UV 4:2:0 16-bit */ +#define V4L2_PIX_FMT_X216 v4l2_fourcc('X', '2', '1', '6') /* 32 XY/UV 4:2:2 16-bit */ +#define V4L2_PIX_FMT_X416 v4l2_fourcc('X', '4', '1', '6') /* 32 XY/UV 4:4:4 16-bit */ /* two non contiguous planes - one Y, one Cr + Cb interleaved */ #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */ @@ -606,6 +623,14 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_NV16M v4l2_fourcc('N', 'M', '1', '6') /* 16 Y/CbCr 4:2:2 */ #define V4L2_PIX_FMT_NV61M v4l2_fourcc('N', 'M', '6', '1') /* 16 Y/CrCb 4:2:2 */ #define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 macroblocks */ +#define V4L2_PIX_FMT_XV20M v4l2_fourcc('X', 'M', '2', '0') /* 32 XY/UV 4:2:2 10-bit */ +#define V4L2_PIX_FMT_XV15M v4l2_fourcc('X', 'M', '1', '5') /* 32 XY/UV 4:2:0 10-bit */ +#define V4L2_PIX_FMT_X012M v4l2_fourcc('M', '0', '1', '2') /* 40 XY/UV 4:2:0 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X212M v4l2_fourcc('M', '2', '1', '2') /* 40 XY/UV 4:2:2 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X412M v4l2_fourcc('M', '4', '1', '2') /* 40 XY/UV 4:4:4 12-bit 4-12-12-12 */ +#define V4L2_PIX_FMT_X016M v4l2_fourcc('M', '0', '1', '6') /* 32 XY/UV 4:2:0 16-bit */ +#define V4L2_PIX_FMT_X216M v4l2_fourcc('M', '2', '1', '6') /* 32 XY/UV 4:2:2 16-bit */ +#define V4L2_PIX_FMT_X416M v4l2_fourcc('M', '4', '1', '6') /* 32 XY/UV 4:4:4 16-bit */ #define V4L2_PIX_FMT_NV12MT_16X16 v4l2_fourcc('V', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 16x16 macroblocks */ /* three planes - Y Cb, Cr */ diff --git a/include/uapi/linux/xilinx-csi2rxss.h b/include/uapi/linux/xilinx-csi2rxss.h new file mode 100644 index 000000000000..df64ddc5eed4 --- /dev/null +++ b/include/uapi/linux/xilinx-csi2rxss.h @@ -0,0 +1,18 @@ +#ifndef __UAPI_XILINX_CSI2RXSS_H__ +#define __UAPI_XILINX_CSI2RXSS_H__ + +#include <linux/videodev2.h> + +/* + * Events + * + * V4L2_EVENT_XLNXCSIRX_SPKT: Short packet received + * V4L2_EVENT_XLNXCSIRX_SPKT_OVF: Short packet FIFO overflow + * V4L2_EVENT_XLNXCSIRX_SLBF: Stream line buffer full + */ +#define V4L2_EVENT_XLNXCSIRX_CLASS (V4L2_EVENT_PRIVATE_START | 0x100) +#define V4L2_EVENT_XLNXCSIRX_SPKT (V4L2_EVENT_XLNXCSIRX_CLASS | 0x1) +#define V4L2_EVENT_XLNXCSIRX_SPKT_OVF (V4L2_EVENT_XLNXCSIRX_CLASS | 0x2) +#define V4L2_EVENT_XLNXCSIRX_SLBF (V4L2_EVENT_XLNXCSIRX_CLASS | 0x3) + +#endif /* __UAPI_XILINX_CSI2RXSS_H__ */ diff --git a/include/uapi/linux/xilinx-hls.h b/include/uapi/linux/xilinx-hls.h new file mode 100644 index 000000000000..a7f6447927e0 --- /dev/null +++ b/include/uapi/linux/xilinx-hls.h @@ -0,0 +1,21 @@ +#ifndef __UAPI_XILINX_HLS_H__ +#define __UAPI_XILINX_HLS_H__ + +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/videodev2.h> + +struct xilinx_axi_hls_register { + __u32 offset; + __u32 value; +}; + +struct xilinx_axi_hls_registers { + __u32 num_regs; + struct xilinx_axi_hls_register __user *regs; +}; + +#define XILINX_AXI_HLS_READ _IOWR('V', BASE_VIDIOC_PRIVATE+0, struct xilinx_axi_hls_registers) +#define XILINX_AXI_HLS_WRITE _IOW('V', BASE_VIDIOC_PRIVATE+1, struct xilinx_axi_hls_registers) + +#endif /* __UAPI_XILINX_HLS_H__ */ diff --git a/include/uapi/linux/xilinx-sdirxss.h b/include/uapi/linux/xilinx-sdirxss.h new file mode 100644 index 000000000000..b7a98041f169 --- /dev/null +++ b/include/uapi/linux/xilinx-sdirxss.h @@ -0,0 +1,66 @@ +#ifndef __UAPI_XILINX_SDIRXSS_H__ +#define __UAPI_XILINX_SDIRXSS_H__ + +#include <linux/types.h> +#include <linux/videodev2.h> + +/* + * Events + * + * V4L2_EVENT_XLNXSDIRX_VIDUNLOCK: Video unlock event + * V4L2_EVENT_XLNXSDIRX_UNDERFLOW: Video in to AXI4 Stream core underflowed + * V4L2_EVENT_XLNXSDIRX_OVERFLOW: Video in to AXI4 Stream core overflowed + */ +#define V4L2_EVENT_XLNXSDIRX_CLASS (V4L2_EVENT_PRIVATE_START | 0x200) +#define V4L2_EVENT_XLNXSDIRX_VIDUNLOCK (V4L2_EVENT_XLNXSDIRX_CLASS | 0x1) +#define V4L2_EVENT_XLNXSDIRX_UNDERFLOW (V4L2_EVENT_XLNXSDIRX_CLASS | 0x2) +#define V4L2_EVENT_XLNXSDIRX_OVERFLOW (V4L2_EVENT_XLNXSDIRX_CLASS | 0x3) + +/* + * This enum is used to prepare the bitmask + * of modes to be detected + */ +enum { + XSDIRX_MODE_SD_OFFSET = 0, + XSDIRX_MODE_HD_OFFSET, + XSDIRX_MODE_3G_OFFSET, + XSDIRX_MODE_6G_OFFSET, + XSDIRX_MODE_12GI_OFFSET, + XSDIRX_MODE_12GF_OFFSET, + XSDIRX_MODE_NUM_SUPPORTED, +}; + +#define XSDIRX_DETECT_ALL_MODES (BIT(XSDIRX_MODE_SD_OFFSET) | \ + BIT(XSDIRX_MODE_HD_OFFSET) | \ + BIT(XSDIRX_MODE_3G_OFFSET) | \ + BIT(XSDIRX_MODE_6G_OFFSET) | \ + BIT(XSDIRX_MODE_12GI_OFFSET) | \ + BIT(XSDIRX_MODE_12GF_OFFSET)) + +/* + * EDH Error Types + * ANC - Ancillary Data Packet Errors + * FF - Full Field Errors + * AP - Active Portion Errors + */ + +#define XSDIRX_EDH_ERRCNT_ANC_EDH_ERR BIT(0) +#define XSDIRX_EDH_ERRCNT_ANC_EDA_ERR BIT(1) +#define XSDIRX_EDH_ERRCNT_ANC_IDH_ERR BIT(2) +#define XSDIRX_EDH_ERRCNT_ANC_IDA_ERR BIT(3) +#define XSDIRX_EDH_ERRCNT_ANC_UES_ERR BIT(4) +#define XSDIRX_EDH_ERRCNT_FF_EDH_ERR BIT(5) +#define XSDIRX_EDH_ERRCNT_FF_EDA_ERR BIT(6) +#define XSDIRX_EDH_ERRCNT_FF_IDH_ERR BIT(7) +#define XSDIRX_EDH_ERRCNT_FF_IDA_ERR BIT(8) +#define XSDIRX_EDH_ERRCNT_FF_UES_ERR BIT(9) +#define XSDIRX_EDH_ERRCNT_AP_EDH_ERR BIT(10) +#define XSDIRX_EDH_ERRCNT_AP_EDA_ERR BIT(11) +#define XSDIRX_EDH_ERRCNT_AP_IDH_ERR BIT(12) +#define XSDIRX_EDH_ERRCNT_AP_IDA_ERR BIT(13) +#define XSDIRX_EDH_ERRCNT_AP_UES_ERR BIT(14) +#define XSDIRX_EDH_ERRCNT_PKT_CHKSUM_ERR BIT(15) + +#define XSDIRX_EDH_ALLERR_MASK 0xFFFF + +#endif /* __UAPI_XILINX_SDIRXSS_H__ */ diff --git a/include/uapi/linux/xilinx-v4l2-controls.h b/include/uapi/linux/xilinx-v4l2-controls.h index b6441fe705c5..61a02a326515 100644 --- a/include/uapi/linux/xilinx-v4l2-controls.h +++ b/include/uapi/linux/xilinx-v4l2-controls.h @@ -70,5 +70,146 @@ #define V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH (V4L2_CID_XILINX_TPG + 16) /* Noise level */ #define V4L2_CID_XILINX_TPG_NOISE_GAIN (V4L2_CID_XILINX_TPG + 17) +/* Foreground pattern (HLS)*/ +#define V4L2_CID_XILINX_TPG_HLS_FG_PATTERN (V4L2_CID_XILINX_TPG + 18) +/* + * Xilinx CRESAMPLE Video IP + */ + +#define V4L2_CID_XILINX_CRESAMPLE (V4L2_CID_USER_BASE + 0xc020) + +/* The field parity for interlaced video */ +#define V4L2_CID_XILINX_CRESAMPLE_FIELD_PARITY (V4L2_CID_XILINX_CRESAMPLE + 1) +/* Specify if the first line of video contains the Chroma information */ +#define V4L2_CID_XILINX_CRESAMPLE_CHROMA_PARITY (V4L2_CID_XILINX_CRESAMPLE + 2) + +/* + * Xilinx RGB2YUV Video IPs + */ + +#define V4L2_CID_XILINX_RGB2YUV (V4L2_CID_USER_BASE + 0xc040) + +/* Maximum Luma(Y) value */ +#define V4L2_CID_XILINX_RGB2YUV_YMAX (V4L2_CID_XILINX_RGB2YUV + 1) +/* Minimum Luma(Y) value */ +#define V4L2_CID_XILINX_RGB2YUV_YMIN (V4L2_CID_XILINX_RGB2YUV + 2) +/* Maximum Cb Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CBMAX (V4L2_CID_XILINX_RGB2YUV + 3) +/* Minimum Cb Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CBMIN (V4L2_CID_XILINX_RGB2YUV + 4) +/* Maximum Cr Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CRMAX (V4L2_CID_XILINX_RGB2YUV + 5) +/* Minimum Cr Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CRMIN (V4L2_CID_XILINX_RGB2YUV + 6) +/* The offset compensation value for Luma(Y) */ +#define V4L2_CID_XILINX_RGB2YUV_YOFFSET (V4L2_CID_XILINX_RGB2YUV + 7) +/* The offset compensation value for Cb Chroma */ +#define V4L2_CID_XILINX_RGB2YUV_CBOFFSET (V4L2_CID_XILINX_RGB2YUV + 8) +/* The offset compensation value for Cr Chroma */ +#define V4L2_CID_XILINX_RGB2YUV_CROFFSET (V4L2_CID_XILINX_RGB2YUV + 9) + +/* Y = CA * R + (1 - CA - CB) * G + CB * B */ + +/* CA coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_ACOEF (V4L2_CID_XILINX_RGB2YUV + 10) +/* CB coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_BCOEF (V4L2_CID_XILINX_RGB2YUV + 11) +/* CC coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_CCOEF (V4L2_CID_XILINX_RGB2YUV + 12) +/* CD coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_DCOEF (V4L2_CID_XILINX_RGB2YUV + 13) + +/* + * Xilinx HLS Video IP + */ + +#define V4L2_CID_XILINX_HLS (V4L2_CID_USER_BASE + 0xc060) + +/* The IP model */ +#define V4L2_CID_XILINX_HLS_MODEL (V4L2_CID_XILINX_HLS + 1) + +/* + * Xilinx MIPI CSI2 Rx Subsystem + */ + +/* Base ID */ +#define V4L2_CID_XILINX_MIPICSISS (V4L2_CID_USER_BASE + 0xc080) + +/* Active Lanes */ +#define V4L2_CID_XILINX_MIPICSISS_ACT_LANES (V4L2_CID_XILINX_MIPICSISS + 1) +/* Frames received since streaming is set */ +#define V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER (V4L2_CID_XILINX_MIPICSISS + 2) +/* Reset all event counters */ +#define V4L2_CID_XILINX_MIPICSISS_RESET_COUNTERS (V4L2_CID_XILINX_MIPICSISS + 3) + +/* + * Xilinx Gamma Correction IP + */ + +/* Base ID */ +#define V4L2_CID_XILINX_GAMMA_CORR (V4L2_CID_USER_BASE + 0xc0c0) +/* Adjust Red Gamma */ +#define V4L2_CID_XILINX_GAMMA_CORR_RED_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 1) +/* Adjust Blue Gamma */ +#define V4L2_CID_XILINX_GAMMA_CORR_BLUE_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 2) +/* Adjust Green Gamma */ +#define V4L2_CID_XILINX_GAMMA_CORR_GREEN_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 3) + +/* + * Xilinx Color Space Converter (CSC) VPSS + */ + +/* Base ID */ +#define V4L2_CID_XILINX_CSC (V4L2_CID_USER_BASE + 0xc0a0) +/* Adjust Brightness */ +#define V4L2_CID_XILINX_CSC_BRIGHTNESS (V4L2_CID_XILINX_CSC + 1) +/* Adjust Contrast */ +#define V4L2_CID_XILINX_CSC_CONTRAST (V4L2_CID_XILINX_CSC + 2) +/* Adjust Red Gain */ +#define V4L2_CID_XILINX_CSC_RED_GAIN (V4L2_CID_XILINX_CSC + 3) +/* Adjust Green Gain */ +#define V4L2_CID_XILINX_CSC_GREEN_GAIN (V4L2_CID_XILINX_CSC + 4) +/* Adjust Blue Gain */ +#define V4L2_CID_XILINX_CSC_BLUE_GAIN (V4L2_CID_XILINX_CSC + 5) + +/* + * Xilinx SDI Rx Subsystem + */ + +/* Base ID */ +#define V4L2_CID_XILINX_SDIRX (V4L2_CID_USER_BASE + 0xc100) + +/* Framer Control */ +#define V4L2_CID_XILINX_SDIRX_FRAMER (V4L2_CID_XILINX_SDIRX + 1) +/* Video Lock Window Control */ +#define V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW (V4L2_CID_XILINX_SDIRX + 2) +/* EDH Error Mask Control */ +#define V4L2_CID_XILINX_SDIRX_EDH_ERRCNT_ENABLE (V4L2_CID_XILINX_SDIRX + 3) +/* Mode search Control */ +#define V4L2_CID_XILINX_SDIRX_SEARCH_MODES (V4L2_CID_XILINX_SDIRX + 4) +/* Get Detected Mode control */ +#define V4L2_CID_XILINX_SDIRX_MODE_DETECT (V4L2_CID_XILINX_SDIRX + 5) +/* Get CRC error status */ +#define V4L2_CID_XILINX_SDIRX_CRC (V4L2_CID_XILINX_SDIRX + 6) +/* Get EDH error count control */ +#define V4L2_CID_XILINX_SDIRX_EDH_ERRCNT (V4L2_CID_XILINX_SDIRX + 7) +/* Get EDH status control */ +#define V4L2_CID_XILINX_SDIRX_EDH_STATUS (V4L2_CID_XILINX_SDIRX + 8) +/* Get Transport Interlaced status */ +#define V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED (V4L2_CID_XILINX_SDIRX + 9) +/* Get Active Streams count */ +#define V4L2_CID_XILINX_SDIRX_ACTIVE_STREAMS (V4L2_CID_XILINX_SDIRX + 10) +/* Is Mode 3GB */ +#define V4L2_CID_XILINX_SDIRX_IS_3GB (V4L2_CID_XILINX_SDIRX + 11) + +/* + * Xilinx VIP + */ + +/* Base ID */ +#define V4L2_CID_XILINX_VIP (V4L2_CID_USER_BASE + 0xc120) + +/* Low latency mode */ +#define V4L2_CID_XILINX_LOW_LATENCY (V4L2_CID_XILINX_VIP + 1) #endif /* __UAPI_XILINX_V4L2_CONTROLS_H__ */ diff --git a/include/uapi/linux/xilinx-v4l2-events.h b/include/uapi/linux/xilinx-v4l2-events.h new file mode 100644 index 000000000000..e31e998eba67 --- /dev/null +++ b/include/uapi/linux/xilinx-v4l2-events.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx V4L2 SCD Driver + * + * Copyright (C) 2017-2018 Xilinx, Inc. + * + * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> + * + */ + +#ifndef __UAPI_XILINX_V4L2_EVENTS_H__ +#define __UAPI_XILINX_V4L2_EVENTS_H__ + +#include <linux/videodev2.h> + +/* + * Events + * + * V4L2_EVENT_XLNXSCD: Scene Change Detection + */ +#define V4L2_EVENT_XLNXSCD_CLASS (V4L2_EVENT_PRIVATE_START | 0x300) +#define V4L2_EVENT_XLNXSCD (V4L2_EVENT_XLNXSCD_CLASS | 0x1) + +#endif /* __UAPI_XILINX_V4L2_EVENTS_H__ */ diff --git a/include/uapi/linux/xlnx_ctrl.h b/include/uapi/linux/xlnx_ctrl.h new file mode 100644 index 000000000000..35ff1fdbf65b --- /dev/null +++ b/include/uapi/linux/xlnx_ctrl.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Xilinx Controls Header + * + * Copyright (C) 2019 Xilinx, Inc. + * + * Contacts: Saurabh Sengar <saurabh.singh@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __UAPI_XLNX_CTRL_H__ +#define __UAPI_XLNX_CTRL_H__ + +#define XSET_FB_CAPTURE 16 +#define XSET_FB_CONFIGURE 17 +#define XSET_FB_ENABLE 18 +#define XSET_FB_DISABLE 19 +#define XSET_FB_RELEASE 20 +#define XSET_FB_ENABLE_SNGL 21 +#define XSET_FB_POLL 22 +#define XVPSS_SET_CONFIGURE 16 +#define XVPSS_SET_ENABLE 17 +#define XVPSS_SET_DISABLE 18 + +#endif /* __UAPI_XLNX_CTRL_H__ */ + diff --git a/include/uapi/linux/xlnxsync.h b/include/uapi/linux/xlnxsync.h new file mode 100644 index 000000000000..989b2f1ef93c --- /dev/null +++ b/include/uapi/linux/xlnxsync.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __XLNXSYNC_H__ +#define __XLNXSYNC_H__ + +/* Bit offset in channel status byte */ +/* x = channel */ +#define XLNXSYNC_CHX_FB0_MASK(x) BIT(0 + ((x) << 3)) +#define XLNXSYNC_CHX_FB1_MASK(x) BIT(1 + ((x) << 3)) +#define XLNXSYNC_CHX_FB2_MASK(x) BIT(2 + ((x) << 3)) +#define XLNXSYNC_CHX_ENB_MASK(x) BIT(3 + ((x) << 3)) +#define XLNXSYNC_CHX_SYNC_ERR_MASK(x) BIT(4 + ((x) << 3)) +#define XLNXSYNC_CHX_WDG_ERR_MASK(x) BIT(5 + ((x) << 3)) + +/* + * This is set in the fb_id or channel_id of struct xlnxsync_chan_config when + * configuring the channel. This makes the driver auto search for the free + * framebuffer or channel slot. + */ +#define XLNXSYNC_AUTO_SEARCH 0xFF + +#define XLNXSYNC_MAX_ENC_CHANNEL 4 +#define XLNXSYNC_MAX_DEC_CHANNEL 2 +#define XLNXSYNC_BUF_PER_CHANNEL 3 + +/** + * struct xlnxsync_chan_config - Synchronizer channel configuration struct + * @luma_start_address: Start address of Luma buffer + * @chroma_start_address: Start address of Chroma buffer + * @luma_end_address: End address of Luma buffer + * @chroma_end_address: End address of Chroma buffer + * @luma_margin: Margin for Luma buffer + * @chroma_margin: Margin for Chroma buffer + * @fb_id: Framebuffer index. Valid values 0/1/2/XLNXSYNC_AUTO_SEARCH + * @channel_id: Channel index to be configured. + * Valid 0..3 & XLNXSYNC_AUTO_SEARCH + * @ismono: Flag to indicate if buffer is Luma only. + * + * This structure contains the configuration for monitoring a particular + * framebuffer on a particular channel. + */ +struct xlnxsync_chan_config { + u64 luma_start_address; + u64 chroma_start_address; + u64 luma_end_address; + u64 chroma_end_address; + u32 luma_margin; + u32 chroma_margin; + u8 fb_id; + u8 channel_id; + u8 ismono; +}; + +/** + * struct xlnxsync_clr_err - Clear channel error + * @channel_id: Channel id whose error needs to be cleared + * @sync_err: Set this to clear sync error + * @wdg_err: Set this to clear watchdog error + */ +struct xlnxsync_clr_err { + u8 channel_id; + u8 sync_err; + u8 wdg_err; +}; + +/** + * struct xlnxsync_fbdone - Framebuffer Done + * @status: Framebuffer Done status + */ +struct xlnxsync_fbdone { + u8 status[XLNXSYNC_MAX_ENC_CHANNEL][XLNXSYNC_BUF_PER_CHANNEL]; +}; + +/** + * struct xlnxsync_config - Synchronizer IP configuration + * @encode: true if encoder type, false for decoder type + * @max_channels: Maximum channels this IP supports + */ +struct xlnxsync_config { + u8 encode; + u8 max_channels; +}; + +#define XLNXSYNC_MAGIC 'X' + +/* + * This ioctl is used to get the IP config (i.e. encode / decode) + * and max number of channels + */ +#define XLNXSYNC_GET_CFG _IOR(XLNXSYNC_MAGIC, 1,\ + struct xlnxsync_config *) +/* This ioctl is used to get the channel status */ +#define XLNXSYNC_GET_CHAN_STATUS _IOR(XLNXSYNC_MAGIC, 2, u32 *) +/* This is used to set the framebuffer address for a channel */ +#define XLNXSYNC_SET_CHAN_CONFIG _IOW(XLNXSYNC_MAGIC, 3,\ + struct xlnxsync_chan_config *) +/* Enable a channel. The argument is channel number between 0 and 3 */ +#define XLNXSYNC_CHAN_ENABLE _IOR(XLNXSYNC_MAGIC, 4, u8) +/* Enable a channel. The argument is channel number between 0 and 3 */ +#define XLNXSYNC_CHAN_DISABLE _IOR(XLNXSYNC_MAGIC, 5, u8) +/* This is used to clear the Sync and Watchdog errors for a channel */ +#define XLNXSYNC_CLR_CHAN_ERR _IOW(XLNXSYNC_MAGIC, 6,\ + struct xlnxsync_clr_err *) +/* This is used to get the framebuffer done status for a channel */ +#define XLNXSYNC_GET_CHAN_FBDONE_STAT _IOR(XLNXSYNC_MAGIC, 7,\ + struct xlnxsync_fbdone *) +/* This is used to clear the framebuffer done status for a channel */ +#define XLNXSYNC_CLR_CHAN_FBDONE_STAT _IOW(XLNXSYNC_MAGIC, 8,\ + struct xlnxsync_fbdone *) + +#endif diff --git a/include/uapi/linux/zocl_ioctl.h b/include/uapi/linux/zocl_ioctl.h new file mode 100644 index 000000000000..ee1f1e289cd8 --- /dev/null +++ b/include/uapi/linux/zocl_ioctl.h @@ -0,0 +1,125 @@ +/* + * A GEM style CMA backed memory manager for ZynQ based OpenCL accelerators. + * + * Copyright (C) 2016 Xilinx, Inc. All rights reserved. + * + * Authors: + * Sonal Santan <sonal.santan@xilinx.com> + * Umang Parekh <umang.parekh@xilinx.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _XCL_ZOCL_IOCTL_H_ +#define _XCL_ZOCL_IOCTL_H_ + +enum { + DRM_ZOCL_CREATE_BO = 0, + DRM_ZOCL_MAP_BO, + DRM_ZOCL_SYNC_BO, + DRM_ZOCL_INFO_BO, + DRM_ZOCL_PWRITE_BO, + DRM_ZOCL_PREAD_BO, + DRM_ZOCL_NUM_IOCTLS +}; + +enum drm_zocl_sync_bo_dir { + DRM_ZOCL_SYNC_BO_TO_DEVICE, + DRM_ZOCL_SYNC_BO_FROM_DEVICE +}; + +#define DRM_ZOCL_BO_FLAGS_COHERENT 0x00000001 +#define DRM_ZOCL_BO_FLAGS_CMA 0x00000002 + +struct drm_zocl_create_bo { + uint64_t size; + uint32_t handle; + uint32_t flags; +}; + +struct drm_zocl_map_bo { + uint32_t handle; + uint32_t pad; + uint64_t offset; +}; + +/** + * struct drm_zocl_sync_bo - used for SYNQ_BO IOCTL + * @handle: GEM object handle + * @dir: DRM_ZOCL_SYNC_DIR_XXX + * @offset: Offset into the object to write to + * @size: Length of data to write + */ +struct drm_zocl_sync_bo { + uint32_t handle; + enum drm_zocl_sync_bo_dir dir; + uint64_t offset; + uint64_t size; +}; + +/** + * struct drm_zocl_info_bo - used for INFO_BO IOCTL + * @handle: GEM object handle + * @size: Size of BO + * @paddr: physical address + */ +struct drm_zocl_info_bo { + uint32_t handle; + uint64_t size; + uint64_t paddr; +}; + +/** + * struct drm_zocl_pwrite_bo - used for PWRITE_BO IOCTL + * @handle: GEM object handle + * @pad: Padding + * @offset: Offset into the object to write to + * @size: Length of data to write + * @data_ptr: Pointer to read the data from (pointers not 32/64 compatible) + */ +struct drm_zocl_pwrite_bo { + uint32_t handle; + uint32_t pad; + uint64_t offset; + uint64_t size; + uint64_t data_ptr; +}; + +/** + * struct drm_zocl_pread_bo - used for PREAD_BO IOCTL + * @handle: GEM object handle + * @pad: Padding + * @offset: Offset into the object to read from + * @size: Length of data to wrreadite + * @data_ptr: Pointer to write the data into (pointers not 32/64 compatible) + */ +struct drm_zocl_pread_bo { + uint32_t handle; + uint32_t pad; + uint64_t offset; + uint64_t size; + uint64_t data_ptr; +}; + +#define DRM_IOCTL_ZOCL_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_CREATE_BO, \ + struct drm_zocl_create_bo) +#define DRM_IOCTL_ZOCL_MAP_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_MAP_BO, struct drm_zocl_map_bo) +#define DRM_IOCTL_ZOCL_SYNC_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_SYNC_BO, struct drm_zocl_sync_bo) +#define DRM_IOCTL_ZOCL_INFO_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_INFO_BO, struct drm_zocl_info_bo) +#define DRM_IOCTL_ZOCL_PWRITE_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_PWRITE_BO, \ + struct drm_zocl_pwrite_bo) +#define DRM_IOCTL_ZOCL_PREAD_BO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_ZOCL_PREAD_BO, struct drm_zocl_pread_bo) +#endif diff --git a/include/uapi/misc/xilinx_sdfec.h b/include/uapi/misc/xilinx_sdfec.h new file mode 100644 index 000000000000..13c4a9f9c360 --- /dev/null +++ b/include/uapi/misc/xilinx_sdfec.h @@ -0,0 +1,470 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Xilinx SD-FEC + * + * Copyright (C) 2016 - 2017 Xilinx, Inc. + * + * Description: + * This driver is developed for SDFEC16 IP. It provides a char device + * in sysfs and supports file operations like open(), close() and ioctl(). + */ +#ifndef __XILINX_SDFEC_H__ +#define __XILINX_SDFEC_H__ + +/* Shared LDPC Tables */ +#define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000) +#define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x103FC) +#define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000) +#define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x18FFC) +#define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000) +#define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x27FFC) + +/** + * enum xsdfec_code - Code Type. + * @XSDFEC_TURBO_CODE: Driver is configured for Turbo mode. + * @XSDFEC_LDPC_CODE: Driver is configured for LDPC mode. + * + * This enum is used to indicate the mode of the driver. The mode is determined + * by checking which codes are set in the driver. Note that the mode cannot be + * changed by the driver. + */ +enum xsdfec_code { + XSDFEC_TURBO_CODE = 0, + XSDFEC_LDPC_CODE, +}; + +/** + * enum xsdfec_order - Order + * @XSDFEC_MAINTAIN_ORDER: Maintain order execution of blocks. + * @XSDFEC_OUT_OF_ORDER: Out-of-order execution of blocks. + * + * This enum is used to indicate whether the order of blocks can change from + * input to output. + */ +enum xsdfec_order { + XSDFEC_MAINTAIN_ORDER = 0, + XSDFEC_OUT_OF_ORDER, +}; + +/** + * enum xsdfec_turbo_alg - Turbo Algorithm Type. + * @XSDFEC_MAX_SCALE: Max Log-Map algorithm with extrinsic scaling. When + * scaling is set to this is equivalent to the Max Log-Map + * algorithm. + * @XSDFEC_MAX_STAR: Log-Map algorithm. + * @XSDFEC_TURBO_ALG_MAX: Used to indicate out of bound Turbo algorithms. + * + * This enum specifies which Turbo Decode algorithm is in use. + */ +enum xsdfec_turbo_alg { + XSDFEC_MAX_SCALE = 0, + XSDFEC_MAX_STAR, + XSDFEC_TURBO_ALG_MAX, +}; + +/** + * enum xsdfec_state - State. + * @XSDFEC_INIT: Driver is initialized. + * @XSDFEC_STARTED: Driver is started. + * @XSDFEC_STOPPED: Driver is stopped. + * @XSDFEC_NEEDS_RESET: Driver needs to be reset. + * @XSDFEC_PL_RECONFIGURE: Programmable Logic needs to be recofigured. + * + * This enum is used to indicate the state of the driver. + */ +enum xsdfec_state { + XSDFEC_INIT = 0, + XSDFEC_STARTED, + XSDFEC_STOPPED, + XSDFEC_NEEDS_RESET, + XSDFEC_PL_RECONFIGURE, +}; + +/** + * enum xsdfec_axis_width - AXIS_WIDTH.DIN Setting for 128-bit width. + * @XSDFEC_1x128b: DIN data input stream consists of a 128-bit lane + * @XSDFEC_2x128b: DIN data input stream consists of two 128-bit lanes + * @XSDFEC_4x128b: DIN data input stream consists of four 128-bit lanes + * + * This enum is used to indicate the AXIS_WIDTH.DIN setting for 128-bit width. + * The number of lanes of the DIN data input stream depends upon the + * AXIS_WIDTH.DIN parameter. + */ +enum xsdfec_axis_width { + XSDFEC_1x128b = 1, + XSDFEC_2x128b = 2, + XSDFEC_4x128b = 4, +}; + +/** + * enum xsdfec_axis_word_include - Words Configuration. + * @XSDFEC_FIXED_VALUE: Fixed, the DIN_WORDS AXI4-Stream interface is removed + * from the IP instance and is driven with the specified + * number of words. + * @XSDFEC_IN_BLOCK: In Block, configures the IP instance to expect a single + * DIN_WORDS value per input code block. The DIN_WORDS + * interface is present. + * @XSDFEC_PER_AXI_TRANSACTION: Per Transaction, configures the IP instance to + * expect one DIN_WORDS value per input transaction on the DIN interface. The + * DIN_WORDS interface is present. + * @XSDFEC_AXIS_WORDS_INCLUDE_MAX: Used to indicate out of bound Words + * Configurations. + * + * This enum is used to specify the DIN_WORDS configuration. + */ +enum xsdfec_axis_word_include { + XSDFEC_FIXED_VALUE = 0, + XSDFEC_IN_BLOCK, + XSDFEC_PER_AXI_TRANSACTION, + XSDFEC_AXIS_WORDS_INCLUDE_MAX, +}; + +/** + * struct xsdfec_turbo - User data for Turbo codes. + * @alg: Specifies which Turbo decode algorithm to use + * @scale: Specifies the extrinsic scaling to apply when the Max Scale algorithm + * has been selected + * + * Turbo code structure to communicate parameters to XSDFEC driver. + */ +struct xsdfec_turbo { + enum xsdfec_turbo_alg alg; + u8 scale; +}; + +/** + * struct xsdfec_ldpc_params - User data for LDPC codes. + * @n: Number of code word bits + * @k: Number of information bits + * @psize: Size of sub-matrix + * @nlayers: Number of layers in code + * @nqc: Quasi Cyclic Number + * @nmqc: Number of M-sized QC operations in parity check matrix + * @nm: Number of M-size vectors in N + * @norm_type: Normalization required or not + * @no_packing: Determines if multiple QC ops should be performed + * @special_qc: Sub-Matrix property for Circulant weight > 0 + * @no_final_parity: Decide if final parity check needs to be performed + * @max_schedule: Experimental code word scheduling limit + * @sc_off: SC offset + * @la_off: LA offset + * @qc_off: QC offset + * @sc_table: SC Table + * @la_table: LA Table + * @qc_table: QC Table + * @code_id: LDPC Code + * + * This structure describes the LDPC code that is passed to the driver by the + * application. + */ +struct xsdfec_ldpc_params { + u32 n; + u32 k; + u32 psize; + u32 nlayers; + u32 nqc; + u32 nmqc; + u32 nm; + u32 norm_type; + u32 no_packing; + u32 special_qc; + u32 no_final_parity; + u32 max_schedule; + u32 sc_off; + u32 la_off; + u32 qc_off; + u32 sc_table[XSDFEC_LDPC_SC_TABLE_ADDR_HIGH - + XSDFEC_LDPC_SC_TABLE_ADDR_BASE]; + u32 la_table[XSDFEC_LDPC_LA_TABLE_ADDR_HIGH - + XSDFEC_LDPC_LA_TABLE_ADDR_BASE]; + u32 qc_table[XSDFEC_LDPC_QC_TABLE_ADDR_HIGH - + XSDFEC_LDPC_QC_TABLE_ADDR_BASE]; + u16 code_id; +}; + +/** + * struct xsdfec_status - Status of SD-FEC core. + * @fec_id: ID of SD-FEC instance. ID is limited to the number of active + * SD-FEC's in the FPGA and is related to the driver instance + * Minor number. + * @state: State of the SD-FEC core + * @activity: Describes if the SD-FEC instance is Active + */ +struct xsdfec_status { + s32 fec_id; + enum xsdfec_state state; + bool activity; +}; + +/** + * struct xsdfec_irq - Enabling or Disabling Interrupts. + * @enable_isr: If true enables the ISR + * @enable_ecc_isr: If true enables the ECC ISR + */ +struct xsdfec_irq { + bool enable_isr; + bool enable_ecc_isr; +}; + +/** + * struct xsdfec_config - Configuration of SD-FEC core. + * @fec_id: ID of SD-FEC instance. ID is limited to the number of active + * SD-FEC's in the FPGA and is related to the driver instance + * Minor number. + * @code: The codes being used by the SD-FEC instance + * @order: Order of Operation + * @bypass: Is the core being bypassed + * @code_wr_protect: Is write protection of LDPC codes enabled + * @din_width: Width of the DIN AXI4-Stream + * @din_word_include: How DIN_WORDS are inputted + * @dout_width: Width of the DOUT AXI4-Stream + * @dout_word_include: HOW DOUT_WORDS are outputted + * @irq: Enabling or disabling interrupts + */ +struct xsdfec_config { + s32 fec_id; + enum xsdfec_code code; + enum xsdfec_order order; + bool bypass; + bool code_wr_protect; + enum xsdfec_axis_width din_width; + enum xsdfec_axis_word_include din_word_include; + enum xsdfec_axis_width dout_width; + enum xsdfec_axis_word_include dout_word_include; + struct xsdfec_irq irq; +}; + +/** + * struct xsdfec_stats - Stats retrived by ioctl XSDFEC_GET_STATS. Used + * to buffer atomic_t variables from struct + * xsdfec_dev. Counts are accumulated until + * the user clears them. + * @isr_err_count: Count of ISR errors + * @cecc_count: Count of Correctable ECC errors (SBE) + * @uecc_count: Count of Uncorrectable ECC errors (MBE) + */ +struct xsdfec_stats { + u32 isr_err_count; + u32 cecc_count; + u32 uecc_count; +}; + +/** + * struct xsdfec_ldpc_param_table_sizes - Used to store sizes of SD-FEC table + * entries for an individual LPDC code + * parameter. + * @sc_size: Size of SC table used + * @la_size: Size of LA table used + * @qc_size: Size of QC table used + */ +struct xsdfec_ldpc_param_table_sizes { + u32 sc_size; + u32 la_size; + u32 qc_size; +}; + +/** + * xsdfec_calculate_shared_ldpc_table_entry_size - Calculates shared code + * table sizes. + * @ldpc: Pointer to the LPDC Code Parameters + * @table_sizes: Pointer to structure containing the calculated table sizes + * + * Calculates the size of shared LDPC code tables used for a specified LPDC code + * parameters. + */ +inline void xsdfec_calculate_shared_ldpc_table_entry_size( + struct xsdfec_ldpc_params *ldpc, + struct xsdfec_ldpc_param_table_sizes *table_sizes) +{ + /* Calculate the sc_size in 32 bit words */ + table_sizes->sc_size = (ldpc->nlayers + 3) >> 2; + /* Calculate the la_size in 256 bit words */ + table_sizes->la_size = ((ldpc->nlayers << 2) + 15) >> 4; + /* Calculate the qc_size in 256 bit words */ + table_sizes->qc_size = ((ldpc->nqc << 2) + 15) >> 4; +} + +/* + * XSDFEC IOCTL List + */ +#define XSDFEC_MAGIC 'f' +/** + * DOC: XSDFEC_START_DEV + * + * @Description + * + * ioctl to start SD-FEC core + * + * This fails if the XSDFEC_SET_ORDER ioctl has not been previously called + */ +#define XSDFEC_START_DEV _IO(XSDFEC_MAGIC, 0) +/** + * DOC: XSDFEC_STOP_DEV + * + * @Description + * + * ioctl to stop the SD-FEC core + */ +#define XSDFEC_STOP_DEV _IO(XSDFEC_MAGIC, 1) +/** + * DOC: XSDFEC_GET_STATUS + * + * @Description + * + * ioctl that returns status of SD-FEC core + */ +#define XSDFEC_GET_STATUS _IOR(XSDFEC_MAGIC, 2, struct xsdfec_status *) +/** + * DOC: XSDFEC_SET_IRQ + * @Parameters + * + * @struct xsdfec_irq * + * Pointer to the &struct xsdfec_irq that contains the interrupt settings + * for the SD-FEC core + * + * @Description + * + * ioctl to enable or disable irq + */ +#define XSDFEC_SET_IRQ _IOW(XSDFEC_MAGIC, 3, struct xsdfec_irq *) +/** + * DOC: XSDFEC_SET_TURBO + * @Parameters + * + * @struct xsdfec_turbo * + * Pointer to the &struct xsdfec_turbo that contains the Turbo decode + * settings for the SD-FEC core + * + * @Description + * + * ioctl that sets the SD-FEC Turbo parameter values + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_SET_TURBO _IOW(XSDFEC_MAGIC, 4, struct xsdfec_turbo *) +/** + * DOC: XSDFEC_ADD_LDPC_CODE_PARAMS + * @Parameters + * + * @struct xsdfec_ldpc_params * + * Pointer to the &struct xsdfec_ldpc_params that contains the LDPC code + * parameters to be added to the SD-FEC Block + * + * @Description + * ioctl to add an LDPC code to the SD-FEC LDPC codes + * + * This can only be used when: + * + * - Driver is in the XSDFEC_STOPPED state + * + * - SD-FEC core is configured as LPDC + * + * - SD-FEC Code Write Protection is disabled + */ +#define XSDFEC_ADD_LDPC_CODE_PARAMS \ + _IOW(XSDFEC_MAGIC, 5, struct xsdfec_ldpc_params *) +/** + * DOC: XSDFEC_GET_CONFIG + * @Parameters + * + * @struct xsdfec_config * + * Pointer to the &struct xsdfec_config that contains the current + * configuration settings of the SD-FEC Block + * + * @Description + * + * ioctl that returns SD-FEC core configuration + */ +#define XSDFEC_GET_CONFIG _IOR(XSDFEC_MAGIC, 6, struct xsdfec_config *) +/** + * DOC: XSDFEC_GET_TURBO + * @Parameters + * + * @struct xsdfec_turbo * + * Pointer to the &struct xsdfec_turbo that contains the current Turbo + * decode settings of the SD-FEC Block + * + * @Description + * + * ioctl that returns SD-FEC turbo param values + */ +#define XSDFEC_GET_TURBO _IOR(XSDFEC_MAGIC, 7, struct xsdfec_turbo *) +/** + * DOC: XSDFEC_SET_ORDER + * @Parameters + * + * @struct unsigned long * + * Pointer to the unsigned long that contains a value from the + * @enum xsdfec_order + * + * @Description + * + * ioctl that sets order, if order of blocks can change from input to output + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_SET_ORDER _IOW(XSDFEC_MAGIC, 8, unsigned long *) +/** + * DOC: XSDFEC_SET_BYPASS + * @Parameters + * + * @struct bool * + * Pointer to bool that sets the bypass value, where false results in + * normal operation and false results in the SD-FEC performing the + * configured operations (same number of cycles) but output data matches + * the input data + * + * @Description + * + * ioctl that sets bypass. + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_SET_BYPASS _IOW(XSDFEC_MAGIC, 9, bool *) +/** + * DOC: XSDFEC_IS_ACTIVE + * @Parameters + * + * @struct bool * + * Pointer to bool that returns true if the SD-FEC is processing data + * + * @Description + * + * ioctl that determines if SD-FEC is processing data + */ +#define XSDFEC_IS_ACTIVE _IOR(XSDFEC_MAGIC, 10, bool *) +/** + * DOC: XSDFEC_CLEAR_STATS + * + * @Description + * + * ioctl that clears error stats collected during interrupts + */ +#define XSDFEC_CLEAR_STATS _IO(XSDFEC_MAGIC, 11) +/** + * DOC: XSDFEC_GET_STATS + * @Parameters + * + * @struct xsdfec_stats * + * Pointer to the &struct xsdfec_stats that will contain the updated stats + * values + * + * @Description + * + * ioctl that returns SD-FEC core stats + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_GET_STATS _IOR(XSDFEC_MAGIC, 12, struct xsdfec_stats *) +/** + * DOC: XSDFEC_SET_DEFAULT_CONFIG + * + * @Description + * + * ioctl that returns SD-FEC core to default config, use after a reset + * + * This can only be used when the driver is in the XSDFEC_STOPPED state + */ +#define XSDFEC_SET_DEFAULT_CONFIG _IO(XSDFEC_MAGIC, 13) + +#endif /* __XILINX_SDFEC_H__ */ |