diff options
Diffstat (limited to 'include/uapi/linux/xilinx-v4l2-controls.h')
| -rw-r--r-- | include/uapi/linux/xilinx-v4l2-controls.h | 161 |
1 files changed, 161 insertions, 0 deletions
diff --git a/include/uapi/linux/xilinx-v4l2-controls.h b/include/uapi/linux/xilinx-v4l2-controls.h index b6441fe705c5..23d1574c6d55 100644 --- a/include/uapi/linux/xilinx-v4l2-controls.h +++ b/include/uapi/linux/xilinx-v4l2-controls.h @@ -70,5 +70,166 @@ #define V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH (V4L2_CID_XILINX_TPG + 16) /* Noise level */ #define V4L2_CID_XILINX_TPG_NOISE_GAIN (V4L2_CID_XILINX_TPG + 17) +/* Foreground pattern (HLS)*/ +#define V4L2_CID_XILINX_TPG_HLS_FG_PATTERN (V4L2_CID_XILINX_TPG + 18) +/* + * Xilinx CRESAMPLE Video IP + */ + +#define V4L2_CID_XILINX_CRESAMPLE (V4L2_CID_USER_BASE + 0xc020) + +/* The field parity for interlaced video */ +#define V4L2_CID_XILINX_CRESAMPLE_FIELD_PARITY (V4L2_CID_XILINX_CRESAMPLE + 1) +/* Specify if the first line of video contains the Chroma information */ +#define V4L2_CID_XILINX_CRESAMPLE_CHROMA_PARITY (V4L2_CID_XILINX_CRESAMPLE + 2) + +/* + * Xilinx RGB2YUV Video IPs + */ + +#define V4L2_CID_XILINX_RGB2YUV (V4L2_CID_USER_BASE + 0xc040) + +/* Maximum Luma(Y) value */ +#define V4L2_CID_XILINX_RGB2YUV_YMAX (V4L2_CID_XILINX_RGB2YUV + 1) +/* Minimum Luma(Y) value */ +#define V4L2_CID_XILINX_RGB2YUV_YMIN (V4L2_CID_XILINX_RGB2YUV + 2) +/* Maximum Cb Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CBMAX (V4L2_CID_XILINX_RGB2YUV + 3) +/* Minimum Cb Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CBMIN (V4L2_CID_XILINX_RGB2YUV + 4) +/* Maximum Cr Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CRMAX (V4L2_CID_XILINX_RGB2YUV + 5) +/* Minimum Cr Chroma value */ +#define V4L2_CID_XILINX_RGB2YUV_CRMIN (V4L2_CID_XILINX_RGB2YUV + 6) +/* The offset compensation value for Luma(Y) */ +#define V4L2_CID_XILINX_RGB2YUV_YOFFSET (V4L2_CID_XILINX_RGB2YUV + 7) +/* The offset compensation value for Cb Chroma */ +#define V4L2_CID_XILINX_RGB2YUV_CBOFFSET (V4L2_CID_XILINX_RGB2YUV + 8) +/* The offset compensation value for Cr Chroma */ +#define V4L2_CID_XILINX_RGB2YUV_CROFFSET (V4L2_CID_XILINX_RGB2YUV + 9) + +/* Y = CA * R + (1 - CA - CB) * G + CB * B */ + +/* CA coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_ACOEF (V4L2_CID_XILINX_RGB2YUV + 10) +/* CB coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_BCOEF (V4L2_CID_XILINX_RGB2YUV + 11) +/* CC coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_CCOEF (V4L2_CID_XILINX_RGB2YUV + 12) +/* CD coefficient */ +#define V4L2_CID_XILINX_RGB2YUV_DCOEF (V4L2_CID_XILINX_RGB2YUV + 13) + +/* + * Xilinx HLS Video IP + */ + +#define V4L2_CID_XILINX_HLS (V4L2_CID_USER_BASE + 0xc060) + +/* The IP model */ +#define V4L2_CID_XILINX_HLS_MODEL (V4L2_CID_XILINX_HLS + 1) + +/* + * Xilinx MIPI CSI2 Rx Subsystem + */ + +/* Base ID */ +#define V4L2_CID_XILINX_MIPICSISS (V4L2_CID_USER_BASE + 0xc080) + +/* Active Lanes */ +#define V4L2_CID_XILINX_MIPICSISS_ACT_LANES (V4L2_CID_XILINX_MIPICSISS + 1) +/* Frames received since streaming is set */ +#define V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER (V4L2_CID_XILINX_MIPICSISS + 2) +/* Reset all event counters */ +#define V4L2_CID_XILINX_MIPICSISS_RESET_COUNTERS (V4L2_CID_XILINX_MIPICSISS + 3) + +/* + * Xilinx Gamma Correction IP + */ + +/* Base ID */ +#define V4L2_CID_XILINX_GAMMA_CORR (V4L2_CID_USER_BASE + 0xc0c0) +/* Adjust Red Gamma */ +#define V4L2_CID_XILINX_GAMMA_CORR_RED_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 1) +/* Adjust Blue Gamma */ +#define V4L2_CID_XILINX_GAMMA_CORR_BLUE_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 2) +/* Adjust Green Gamma */ +#define V4L2_CID_XILINX_GAMMA_CORR_GREEN_GAMMA (V4L2_CID_XILINX_GAMMA_CORR + 3) + +/* + * Xilinx Color Space Converter (CSC) VPSS + */ + +/* Base ID */ +#define V4L2_CID_XILINX_CSC (V4L2_CID_USER_BASE + 0xc0a0) +/* Adjust Brightness */ +#define V4L2_CID_XILINX_CSC_BRIGHTNESS (V4L2_CID_XILINX_CSC + 1) +/* Adjust Contrast */ +#define V4L2_CID_XILINX_CSC_CONTRAST (V4L2_CID_XILINX_CSC + 2) +/* Adjust Red Gain */ +#define V4L2_CID_XILINX_CSC_RED_GAIN (V4L2_CID_XILINX_CSC + 3) +/* Adjust Green Gain */ +#define V4L2_CID_XILINX_CSC_GREEN_GAIN (V4L2_CID_XILINX_CSC + 4) +/* Adjust Blue Gain */ +#define V4L2_CID_XILINX_CSC_BLUE_GAIN (V4L2_CID_XILINX_CSC + 5) + +/* + * Xilinx SDI Rx Subsystem + */ + +/* Base ID */ +#define V4L2_CID_XILINX_SDIRX (V4L2_CID_USER_BASE + 0xc100) + +/* Framer Control */ +#define V4L2_CID_XILINX_SDIRX_FRAMER (V4L2_CID_XILINX_SDIRX + 1) +/* Video Lock Window Control */ +#define V4L2_CID_XILINX_SDIRX_VIDLOCK_WINDOW (V4L2_CID_XILINX_SDIRX + 2) +/* EDH Error Mask Control */ +#define V4L2_CID_XILINX_SDIRX_EDH_ERRCNT_ENABLE (V4L2_CID_XILINX_SDIRX + 3) +/* Mode search Control */ +#define V4L2_CID_XILINX_SDIRX_SEARCH_MODES (V4L2_CID_XILINX_SDIRX + 4) +/* Get Detected Mode control */ +#define V4L2_CID_XILINX_SDIRX_MODE_DETECT (V4L2_CID_XILINX_SDIRX + 5) +/* Get CRC error status */ +#define V4L2_CID_XILINX_SDIRX_CRC (V4L2_CID_XILINX_SDIRX + 6) +/* Get EDH error count control */ +#define V4L2_CID_XILINX_SDIRX_EDH_ERRCNT (V4L2_CID_XILINX_SDIRX + 7) +/* Get EDH status control */ +#define V4L2_CID_XILINX_SDIRX_EDH_STATUS (V4L2_CID_XILINX_SDIRX + 8) +/* Get Transport Interlaced status */ +#define V4L2_CID_XILINX_SDIRX_TS_IS_INTERLACED (V4L2_CID_XILINX_SDIRX + 9) +/* Get Active Streams count */ +#define V4L2_CID_XILINX_SDIRX_ACTIVE_STREAMS (V4L2_CID_XILINX_SDIRX + 10) +/* Is Mode 3GB */ +#define V4L2_CID_XILINX_SDIRX_IS_3GB (V4L2_CID_XILINX_SDIRX + 11) + +/* + * Xilinx VIP + */ + +/* Base ID */ +#define V4L2_CID_XILINX_VIP (V4L2_CID_USER_BASE + 0xc120) + +/* Low latency mode */ +#define V4L2_CID_XILINX_LOW_LATENCY (V4L2_CID_XILINX_VIP + 1) + +/* Control values to enable/disable low latency capture mode */ +#define XVIP_LOW_LATENCY_ENABLE BIT(1) +#define XVIP_LOW_LATENCY_DISABLE BIT(2) + +/* Control value to start DMA */ +#define XVIP_START_DMA BIT(3) + +/* + * Xilinx SCD + */ + +/* Base ID */ +#define V4L2_CID_XILINX_SCD (V4L2_CID_USER_BASE + 0xc140) + +/* + * SCD Threshold + * User can pass percentage as an integer to tune threshold value + */ +#define V4L2_CID_XILINX_SCD_THRESHOLD (V4L2_CID_XILINX_SCD + 1) #endif /* __UAPI_XILINX_V4L2_CONTROLS_H__ */ |