diff options
Diffstat (limited to 'include/linux/spi/spi.h')
| -rw-r--r-- | include/linux/spi/spi.h | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 7067f85cef0b..ee930fb0b6c1 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -123,6 +123,7 @@ void spi_statistics_add_transfer_stats(struct spi_statistics *stats, * the spi_master. * @cs_gpiod: gpio descriptor of the chipselect line (optional, NULL when * not using a GPIO line) + * @multi_die: Flash device with multiple dies. * @word_delay_usecs: microsecond delay to be inserted between consecutive * words of a transfer * @@ -152,6 +153,7 @@ struct spi_device { #define SPI_MODE_1 (0|SPI_CPHA) #define SPI_MODE_2 (SPI_CPOL|0) #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_MODE_X_MASK (SPI_CPOL|SPI_CPHA) #define SPI_CS_HIGH 0x04 /* chipselect active high? */ #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ #define SPI_3WIRE 0x10 /* SI/SO signals shared */ @@ -172,6 +174,7 @@ struct spi_device { char modalias[SPI_NAME_SIZE]; const char *driver_override; int cs_gpio; /* LEGACY: chip select gpio */ + bool multi_die; /* flash with multiple dies*/ struct gpio_desc *cs_gpiod; /* chip select gpio desc */ uint8_t word_delay_usecs; /* inter-word delay */ @@ -466,6 +469,19 @@ struct spi_controller { #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */ + /* Controller may support data stripe feature when more than one + * chips are present. + * Setting data stripe will send data in following manner: + * -> even bytes i.e. 0, 2, 4,... are transmitted on lower data bus + * -> odd bytes i.e. 1, 3, 5,.. are transmitted on upper data bus + */ +#define SPI_MASTER_QUAD_MODE BIT(6) /* support quad mode */ +#define SPI_MASTER_DATA_STRIPE BIT(7) /* support data stripe */ + /* Controller may support asserting more than one chip select at once. + * This flag will enable that feature. + */ +#define SPI_MASTER_BOTH_CS BIT(8) /* assert both chip selects */ +#define SPI_MASTER_U_PAGE BIT(9) /* select upper flash */ /* flag indicating this is a non-devres managed controller */ bool devm_allocated; @@ -756,6 +772,7 @@ extern void spi_res_release(struct spi_controller *ctlr, * @len: size of rx and tx buffers (in bytes) * @speed_hz: Select a speed other than the device default for this * transfer. If 0 the default (from @spi_device) is used. + * @dummy: number of dummy cycles. * @bits_per_word: select a bits_per_word other than the device default * for this transfer. If 0 the default (from @spi_device) is used. * @cs_change: affects chipselect after this transfer completes @@ -775,6 +792,7 @@ extern void spi_res_release(struct spi_controller *ctlr, * @transfer_list: transfers are sequenced through @spi_message.transfers * @tx_sg: Scatterlist for transmit, currently not for client use * @rx_sg: Scatterlist for receive, currently not for client use + * @stripe: true-> enable stripe, false-> disable stripe. * * SPI transfers always write the same number of bytes as they read. * Protocol drivers should always provide @rx_buf and/or @tx_buf. @@ -861,7 +879,8 @@ struct spi_transfer { #define SPI_DELAY_UNIT_SCK 2 u32 speed_hz; u16 word_delay; - + u32 dummy; + bool stripe; u32 effective_speed_hz; struct list_head transfer_list; @@ -1337,7 +1356,6 @@ struct spi_board_info { /* slower signaling on noisy or low voltage boards */ u32 max_speed_hz; - /* bus_num is board specific and matches the bus_num of some * spi_controller that will probably be registered later. * @@ -1417,6 +1435,9 @@ of_find_spi_device_by_node(struct device_node *node) #endif /* IS_ENABLED(CONFIG_OF) */ +bool +update_stripe(const u8 opcode); + /* Compatibility layer */ #define spi_master spi_controller |