diff options
Diffstat (limited to 'drivers/spi/spi-zynqmp-gqspi.c')
| -rw-r--r-- | drivers/spi/spi-zynqmp-gqspi.c | 403 |
1 files changed, 334 insertions, 69 deletions
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 7412a3042a8d..25266cd3f52b 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -16,6 +16,7 @@ #include <linux/module.h> #include <linux/of_irq.h> #include <linux/of_address.h> +#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/spi/spi.h> @@ -33,6 +34,7 @@ #define GQSPI_RXD_OFST 0x00000120 #define GQSPI_TX_THRESHOLD_OFST 0x00000128 #define GQSPI_RX_THRESHOLD_OFST 0x0000012C +#define IOU_TAPDLY_BYPASS_OFST 0x0000003C #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138 #define GQSPI_GEN_FIFO_OFST 0x00000140 #define GQSPI_SEL_OFST 0x00000144 @@ -47,6 +49,7 @@ #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820 #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828 +#define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 /* GQSPI register bit masks */ #define GQSPI_SEL_MASK 0x00000001 @@ -132,12 +135,45 @@ #define GQSPI_SELECT_MODE_QUADSPI 0x4 #define GQSPI_DMA_UNALIGN 0x3 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */ +#define GQSPI_RX_BUS_WIDTH_QUAD 0x4 +#define GQSPI_RX_BUS_WIDTH_DUAL 0x2 +#define GQSPI_RX_BUS_WIDTH_SINGLE 0x1 +#define GQSPI_TX_BUS_WIDTH_QUAD 0x4 +#define GQSPI_TX_BUS_WIDTH_DUAL 0x2 +#define GQSPI_TX_BUS_WIDTH_SINGLE 0x1 +#define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 +#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 +#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 +#define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 +#define GQSPI_USE_DATA_DLY 0x1 +#define GQSPI_USE_DATA_DLY_SHIFT 31 +#define GQSPI_DATA_DLY_ADJ_VALUE 0x2 +#define GQSPI_DATA_DLY_ADJ_SHIFT 28 +#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1 +#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 + +/* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */ +#define QSPI_QUIRK_HAS_TAPDELAY BIT(0) + +#define GQSPI_FREQ_37_5MHZ 37500000 +#define GQSPI_FREQ_40MHZ 40000000 +#define GQSPI_FREQ_100MHZ 100000000 +#define GQSPI_FREQ_150MHZ 150000000 +#define IOU_TAPDLY_BYPASS_MASK 0x7 #define SPI_AUTOSUSPEND_TIMEOUT 3000 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; static const struct zynqmp_eemi_ops *eemi_ops; /** + * struct zynq_platform_data - zynqmp qspi platform data structure + * @quirks: Flags is used to identify the platform + */ +struct qspi_platform_data { + u32 quirks; +}; + +/** * struct zynqmp_qspi - Defines qspi driver instance * @regs: Virtual address of the QSPI controller registers * @refclk: Pointer to the peripheral clock @@ -152,8 +188,14 @@ static const struct zynqmp_eemi_ops *eemi_ops; * @genfifobus: Used to select the upper or lower bus * @dma_rx_bytes: Remaining bytes to receive by DMA mode * @dma_addr: DMA address after mapping the kernel buffer + * @tx_bus_width: Used to represent number of data wires for tx + * @rx_bus_width: Used to represent number of data wires * @genfifoentry: Used for storing the genfifoentry instruction. + * @isinstr: To determine whether the transfer is instruction * @mode: Defines the mode in which QSPI is operating + * @speed_hz: Current SPI bus clock speed in hz + * @io_mode: Defines the operating mode, either IO or dma + * @has_tapdelay: Used for tapdelay register available in qspi */ struct zynqmp_qspi { void __iomem *regs; @@ -169,14 +211,22 @@ struct zynqmp_qspi { u32 genfifobus; u32 dma_rx_bytes; dma_addr_t dma_addr; + u32 rx_bus_width; + u32 tx_bus_width; u32 genfifoentry; + bool isinstr; enum mode_type mode; + u32 speed_hz; + bool io_mode; + bool has_tapdelay; }; /** - * zynqmp_gqspi_read: For GQSPI controller read operation + * zynqmp_gqspi_read - For GQSPI controller read operation * @xqspi: Pointer to the zynqmp_qspi structure * @offset: Offset from where to read + * + * Return: Value read from the qspi register */ static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset) { @@ -184,7 +234,7 @@ static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset) } /** - * zynqmp_gqspi_write: For GQSPI controller write operation + * zynqmp_gqspi_write - For GQSPI controller write operation * @xqspi: Pointer to the zynqmp_qspi structure * @offset: Offset where to write * @val: Value to be written @@ -196,10 +246,10 @@ static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset, } /** - * zynqmp_gqspi_selectslave: For selection of slave device + * zynqmp_gqspi_selectslave - For selection of slave device * @instanceptr: Pointer to the zynqmp_qspi structure - * @flashcs: For chip select - * @flashbus: To check which bus is selected- upper or lower + * @slavecs: For chip select + * @slavebus: To check which bus is selected- upper or lower */ static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr, u8 slavecs, u8 slavebus) @@ -243,7 +293,76 @@ static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr, } /** - * zynqmp_qspi_init_hw: Initialize the hardware + * zynqmp_qspi_set_tapdelay - To configure qspi tap delays + * @xqspi: Pointer to the zynqmp_qspi structure + * @baudrateval: Buadrate to configure + */ +static void zynqmp_qspi_set_tapdelay(struct zynqmp_qspi *xqspi, u32 baudrateval) +{ + u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate; + u32 reqhz = 0; + + if (!eemi_ops->ioctl) + return; + + clk_rate = clk_get_rate(xqspi->refclk); + reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval)); + + if (!xqspi->has_tapdelay) { + if (reqhz <= GQSPI_FREQ_40MHZ) { + eemi_ops->ioctl(NODE_QSPI, IOCTL_SET_TAPDELAY_BYPASS, + PM_TAPDELAY_QSPI, + PM_TAPDELAY_BYPASS_ENABLE, + NULL); + } else if (reqhz <= GQSPI_FREQ_100MHZ) { + eemi_ops->ioctl(NODE_QSPI, IOCTL_SET_TAPDELAY_BYPASS, + PM_TAPDELAY_QSPI, + PM_TAPDELAY_BYPASS_ENABLE, + NULL); + lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK); + datadlyadj |= ((GQSPI_USE_DATA_DLY << + GQSPI_USE_DATA_DLY_SHIFT) + | (GQSPI_DATA_DLY_ADJ_VALUE << + GQSPI_DATA_DLY_ADJ_SHIFT)); + } else if (reqhz <= GQSPI_FREQ_150MHZ) { + lpbkdlyadj |= GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK; + } + } else { + if (reqhz <= GQSPI_FREQ_37_5MHZ) { + tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT); + } else if (reqhz <= GQSPI_FREQ_100MHZ) { + tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE << + TAP_DLY_BYPASS_LQSPI_RX_SHIFT); + lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK); + datadlyadj |= (GQSPI_USE_DATA_DLY << + GQSPI_USE_DATA_DLY_SHIFT); + } else if (reqhz <= GQSPI_FREQ_150MHZ) { + lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK + | (GQSPI_LPBK_DLY_ADJ_DLY_1 << + GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT)); + } + zynqmp_gqspi_write(xqspi, + IOU_TAPDLY_BYPASS_OFST, tapdlybypass); + } + + zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, lpbkdlyadj); + zynqmp_gqspi_write(xqspi, GQSPI_DATA_DLY_ADJ_OFST, datadlyadj); +} + +static u32 zynqmp_disable_intr(struct zynqmp_qspi *xqspi) +{ + u32 value; + + zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK); + value = zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST); + zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK); + + return value; +} + +/** + * zynqmp_qspi_init_hw - Initialize the hardware * @xqspi: Pointer to the zynqmp_qspi structure * * The default settings of the QSPI controller's configurable parameters on @@ -267,9 +386,7 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) /* Select the GQSPI mode */ zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK); /* Clear and disable interrupts */ - zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, - zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) | - GQSPI_ISR_WR_TO_CLR_MASK); + zynqmp_disable_intr(xqspi); /* Clear the DMA STS */ zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST, zynqmp_gqspi_read(xqspi, @@ -321,17 +438,18 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) zynqmp_gqspi_selectslave(xqspi, GQSPI_SELECT_FLASH_CS_LOWER, GQSPI_SELECT_FLASH_BUS_LOWER); - /* Initialize DMA */ - zynqmp_gqspi_write(xqspi, + if (!xqspi->io_mode) { + /* Initialize DMA */ + zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_CTRL_OFST, GQSPI_QSPIDMA_DST_CTRL_RESET_VAL); - + } /* Enable the GQSPI */ zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK); } /** - * zynqmp_qspi_copy_read_data: Copy data to RX buffer + * zynqmp_qspi_copy_read_data - Copy data to RX buffer * @xqspi: Pointer to the zynqmp_qspi structure * @data: The variable where data is stored * @size: Number of bytes to be copied from data to RX buffer @@ -345,7 +463,7 @@ static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi, } /** - * zynqmp_prepare_transfer_hardware: Prepares hardware for transfer. + * zynqmp_prepare_transfer_hardware - Prepares hardware for transfer. * @master: Pointer to the spi_master structure which provides * information about the controller. * @@ -362,7 +480,7 @@ static int zynqmp_prepare_transfer_hardware(struct spi_master *master) } /** - * zynqmp_unprepare_transfer_hardware: Relaxes hardware after transfer + * zynqmp_unprepare_transfer_hardware - Relaxes hardware after transfer * @master: Pointer to the spi_master structure which provides * information about the controller. * @@ -379,7 +497,7 @@ static int zynqmp_unprepare_transfer_hardware(struct spi_master *master) } /** - * zynqmp_qspi_chipselect: Select or deselect the chip select line + * zynqmp_qspi_chipselect - Select or deselect the chip select line * @qspi: Pointer to the spi_device structure * @is_high: Select(0) or deselect (1) the chip select line */ @@ -390,11 +508,27 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) u32 genfifoentry = 0x0, statusreg; genfifoentry |= GQSPI_GENFIFO_MODE_SPI; + + if (qspi->master->flags & SPI_MASTER_BOTH_CS) { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_BOTH, + GQSPI_SELECT_FLASH_BUS_BOTH); + } else if (qspi->master->flags & SPI_MASTER_U_PAGE) { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_UPPER, + GQSPI_SELECT_FLASH_BUS_LOWER); + } else { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_LOWER, + GQSPI_SELECT_FLASH_BUS_LOWER); + } + genfifoentry |= xqspi->genfifobus; if (!is_high) { genfifoentry |= xqspi->genfifocs; genfifoentry |= GQSPI_GENFIFO_CS_SETUP; + xqspi->isinstr = true; } else { genfifoentry |= GQSPI_GENFIFO_CS_HOLD; } @@ -415,8 +549,7 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) && (statusreg & GQSPI_ISR_TXEMPTY_MASK)) break; - else - cpu_relax(); + cpu_relax(); } while (!time_after_eq(jiffies, timeout)); if (time_after_eq(jiffies, timeout)) @@ -424,7 +557,7 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) } /** - * zynqmp_qspi_setup_transfer: Configure QSPI controller for specified + * zynqmp_qspi_setup_transfer - Configure QSPI controller for specified * transfer * @qspi: Pointer to the spi_device structure * @transfer: Pointer to the spi_transfer structure which provides @@ -457,33 +590,39 @@ static int zynqmp_qspi_setup_transfer(struct spi_device *qspi, else req_hz = qspi->max_speed_hz; - /* Set the clock frequency */ - /* If req_hz == 0, default to lowest speed */ - clk_rate = clk_get_rate(xqspi->refclk); + if (xqspi->speed_hz != req_hz) { + /* Set the clock frequency */ + /* If req_hz == 0, default to lowest speed */ + clk_rate = clk_get_rate(xqspi->refclk); - while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) && - (clk_rate / - (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz) - baud_rate_val++; + while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) && + (clk_rate / + (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz) + baud_rate_val++; - config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); + config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); - /* Set the QSPI clock phase and clock polarity */ - config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK); + /* Set the QSPI clock phase and clock polarity */ + config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & + (~GQSPI_CFG_CLK_POL_MASK); - if (qspi->mode & SPI_CPHA) - config_reg |= GQSPI_CFG_CLK_PHA_MASK; - if (qspi->mode & SPI_CPOL) - config_reg |= GQSPI_CFG_CLK_POL_MASK; + if (qspi->mode & SPI_CPHA) + config_reg |= GQSPI_CFG_CLK_PHA_MASK; + if (qspi->mode & SPI_CPOL) + config_reg |= GQSPI_CFG_CLK_POL_MASK; + config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; + config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT); + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); + xqspi->speed_hz = clk_rate / (GQSPI_BAUD_DIV_SHIFT << + baud_rate_val); + zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val); + } - config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; - config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT); - zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); return 0; } /** - * zynqmp_qspi_setup: Configure the QSPI controller + * zynqmp_qspi_setup - Configure the QSPI controller * @qspi: Pointer to the spi_device structure * * Sets the operational mode of QSPI controller for the next QSPI transfer, @@ -499,7 +638,7 @@ static int zynqmp_qspi_setup(struct spi_device *qspi) } /** - * zynqmp_qspi_filltxfifo: Fills the TX FIFO as long as there is room in + * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in * the FIFO or the bytes required to be * transmitted. * @xqspi: Pointer to the zynqmp_qspi structure @@ -525,7 +664,7 @@ static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size) } /** - * zynqmp_qspi_readrxfifo: Fills the RX FIFO as long as there is room in + * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in * the FIFO. * @xqspi: Pointer to the zynqmp_qspi structure * @size: Number of bytes to be copied from RX buffer to RX FIFO @@ -538,7 +677,7 @@ static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size) while ((count < size) && (xqspi->bytes_to_receive > 0)) { if (xqspi->bytes_to_receive >= 4) { (*(u32 *) xqspi->rxbuf) = - zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST); + zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST); xqspi->rxbuf += 4; xqspi->bytes_to_receive -= 4; count += 4; @@ -553,7 +692,40 @@ static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size) } /** - * zynqmp_process_dma_irq: Handler for DMA done interrupt of QSPI + * zynqmp_qspi_preparedummy - Prepares the dummy entry + * + * @xqspi: Pointer to the zynqmp_qspi structure + * @transfer: It is a pointer to the structure containing transfer data. + * @genfifoentry: genfifoentry is pointer to the variable in which + * GENFIFO mask is returned to calling function + */ +static void zynqmp_qspi_preparedummy(struct zynqmp_qspi *xqspi, + struct spi_transfer *transfer, + u32 *genfifoentry) +{ + /* For dummy Tx and Rx are NULL */ + *genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX); + + /* SPI mode */ + *genfifoentry &= ~GQSPI_GENFIFO_MODE_QUADSPI; + if (xqspi->rx_bus_width == GQSPI_RX_BUS_WIDTH_QUAD || + xqspi->tx_bus_width == GQSPI_TX_BUS_WIDTH_QUAD) + *genfifoentry |= GQSPI_GENFIFO_MODE_QUADSPI; + else if (xqspi->rx_bus_width == GQSPI_RX_BUS_WIDTH_DUAL || + xqspi->tx_bus_width == GQSPI_TX_BUS_WIDTH_DUAL) + *genfifoentry |= GQSPI_GENFIFO_MODE_DUALSPI; + else + *genfifoentry |= GQSPI_GENFIFO_MODE_SPI; + + /* Immediate data */ + *genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK; + + if (transfer->dummy) + *genfifoentry |= transfer->dummy; +} + +/** + * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI * controller * @xqspi: zynqmp_qspi instance pointer * @@ -601,7 +773,7 @@ static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi) } /** - * zynqmp_qspi_irq: Interrupt service routine of the QSPI controller + * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller * @irq: IRQ number * @dev_id: Pointer to the xqspi structure * @@ -639,23 +811,29 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id) if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) { zynqmp_process_dma_irq(xqspi); ret = IRQ_HANDLED; - } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) && - (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) { + } else if ((mask & GQSPI_IER_RXNEMPTY_MASK)) { + zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL); + ret = IRQ_HANDLED; + } + if (!(mask & GQSPI_IER_RXEMPTY_MASK) && + (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) { zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL); ret = IRQ_HANDLED; } if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0) && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) { - zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK); + zynqmp_disable_intr(xqspi); + xqspi->isinstr = false; spi_finalize_current_transfer(master); ret = IRQ_HANDLED; } + return ret; } /** - * zynqmp_qspi_selectspimode: Selects SPI mode - x1 or x2 or x4. + * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4. * @xqspi: xqspi is a pointer to the GQSPI instance * @spimode: spimode - SPI or DUAL or QUAD. * Return: Mask to set desired SPI mode in GENFIFO entry. @@ -683,7 +861,7 @@ static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, } /** - * zynq_qspi_setuprxdma: This function sets up the RX DMA operation + * zynq_qspi_setuprxdma - This function sets up the RX DMA operation * @xqspi: xqspi is a pointer to the GQSPI instance. */ static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi) @@ -692,8 +870,9 @@ static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi) dma_addr_t addr; u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf; - if ((xqspi->bytes_to_receive < 8) || - ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) { + if (((xqspi->bytes_to_receive < 8) || (xqspi->io_mode)) || + ((dma_align & GQSPI_DMA_UNALIGN) != 0x0) || + is_vmalloc_addr(xqspi->rxbuf)) { /* Setting to IO mode */ config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); config_reg &= ~GQSPI_CFG_MODE_EN_MASK; @@ -708,8 +887,10 @@ static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi) addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf, rx_bytes, DMA_FROM_DEVICE); - if (dma_mapping_error(xqspi->dev, addr)) + if (dma_mapping_error(xqspi->dev, addr)) { dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n"); + return; + } xqspi->dma_rx_bytes = rx_bytes; xqspi->dma_addr = addr; @@ -733,7 +914,7 @@ static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi) } /** - * zynqmp_qspi_txrxsetup: This function checks the TX/RX buffers in + * zynqmp_qspi_txrxsetup - This function checks the TX/RX buffers in * the transfer and sets up the GENFIFO entries, * TX FIFO as required. * @xqspi: xqspi is a pointer to the GQSPI instance. @@ -755,7 +936,7 @@ static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi, *genfifoentry |= GQSPI_GENFIFO_TX; *genfifoentry |= zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits); - xqspi->bytes_to_transfer = transfer->len; + xqspi->bytes_to_transfer = transfer->len - (transfer->dummy/8); if (xqspi->mode == GQSPI_MODE_DMA) { config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); @@ -784,7 +965,7 @@ static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi, } /** - * zynqmp_qspi_start_transfer: Initiates the QSPI transfer + * zynqmp_qspi_start_transfer - Initiates the QSPI transfer * @master: Pointer to the spi_master structure which provides * information about the controller. * @qspi: Pointer to the spi_device structure @@ -811,18 +992,28 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master, genfifoentry |= xqspi->genfifocs; genfifoentry |= xqspi->genfifobus; + if (!xqspi->isinstr && (master->flags & SPI_MASTER_DATA_STRIPE)) { + if (transfer->stripe) + genfifoentry |= GQSPI_GENFIFO_STRIPE; + } zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry); if (xqspi->mode == GQSPI_MODE_DMA) transfer_len = xqspi->dma_rx_bytes; else - transfer_len = transfer->len; + transfer_len = transfer->len - (transfer->dummy/8); xqspi->genfifoentry = genfifoentry; if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) { genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK; genfifoentry |= transfer_len; zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); + if (transfer->dummy || transfer->tx_nbits >= 1) { + zynqmp_qspi_preparedummy(xqspi, transfer, + &genfifoentry); + zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, + genfifoentry); + } } else { int tempcount = transfer_len; u32 exponent = 8; /* 2^8 = 256 */ @@ -849,6 +1040,12 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master, if (imm_data != 0) { genfifoentry &= ~GQSPI_GENFIFO_EXP; genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK; + if (imm_data % 4 != 0) { + if (((imm_data + 4 - (imm_data % 4)) & 0xFF) == 0x00) + imm_data = 0xFF; + else + imm_data = imm_data + 4 - (imm_data % 4); + } genfifoentry |= (u8) (imm_data & 0xFF); zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); @@ -869,7 +1066,6 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master, if (xqspi->txbuf != NULL) /* Enable interrupts for TX */ zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, - GQSPI_IER_TXEMPTY_MASK | GQSPI_IER_GENFIFOEMPTY_MASK | GQSPI_IER_TXNOT_FULL_MASK); @@ -883,8 +1079,7 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master, } else { zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, GQSPI_IER_GENFIFOEMPTY_MASK | - GQSPI_IER_RXNEMPTY_MASK | - GQSPI_IER_RXEMPTY_MASK); + GQSPI_IER_RXNEMPTY_MASK); } } @@ -892,8 +1087,8 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master, } /** - * zynqmp_qspi_suspend: Suspend method for the QSPI driver - * @_dev: Address of the platform_device structure + * zynqmp_qspi_suspend - Suspend method for the QSPI driver + * @dev: Address of the platform_device structure * * This function stops the QSPI driver queue and disables the QSPI controller * @@ -911,7 +1106,7 @@ static int __maybe_unused zynqmp_qspi_suspend(struct device *dev) } /** - * zynqmp_qspi_resume: Resume method for the QSPI driver + * zynqmp_qspi_resume - Resume method for the QSPI driver * @dev: Address of the platform_device structure * * The function starts the QSPI driver queue and initializes the QSPI @@ -938,10 +1133,12 @@ static int __maybe_unused zynqmp_qspi_resume(struct device *dev) return ret; } + zynqmp_qspi_init_hw(xqspi); spi_master_resume(master); clk_disable(xqspi->refclk); clk_disable(xqspi->pclk); + return 0; } @@ -994,14 +1191,38 @@ static int __maybe_unused zynqmp_runtime_resume(struct device *dev) return 0; } +static int __maybe_unused zynqmp_runtime_idle(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct spi_master *master = platform_get_drvdata(pdev); + struct zynqmp_qspi *xqspi = spi_master_get_devdata(master); + u32 value; + + value = zynqmp_gqspi_read(xqspi, GQSPI_EN_OFST); + if (value) + return -EBUSY; + + return 0; +} + static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = { SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend, - zynqmp_runtime_resume, NULL) + zynqmp_runtime_resume, zynqmp_runtime_idle) SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume) }; +static const struct qspi_platform_data versal_qspi_def = { + .quirks = QSPI_QUIRK_HAS_TAPDELAY, +}; + +static const struct of_device_id zynqmp_qspi_of_match[] = { + { .compatible = "xlnx,zynqmp-qspi-1.0"}, + { .compatible = "xlnx,versal-qspi-1.0", .data = &versal_qspi_def }, + { /* End of table */ } +}; + /** - * zynqmp_qspi_probe: Probe method for the QSPI driver + * zynqmp_qspi_probe - Probe method for the QSPI driver * @pdev: Pointer to the platform_device structure * * This function initializes the driver data structures and the hardware. @@ -1014,6 +1235,11 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) struct spi_master *master; struct zynqmp_qspi *xqspi; struct device *dev = &pdev->dev; + struct device_node *nc; + const struct of_device_id *match; + u32 num_cs; + u32 rx_bus_width; + u32 tx_bus_width; eemi_ops = zynqmp_pm_get_eemi_ops(); if (IS_ERR(eemi_ops)) @@ -1027,6 +1253,14 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) master->dev.of_node = pdev->dev.of_node; platform_set_drvdata(pdev, master); + match = of_match_node(zynqmp_qspi_of_match, pdev->dev.of_node); + if (match) { + const struct qspi_platform_data *p_data = match->data; + + if (p_data && (p_data->quirks & QSPI_QUIRK_HAS_TAPDELAY)) + xqspi->has_tapdelay = true; + } + xqspi->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(xqspi->regs)) { ret = PTR_ERR(xqspi->regs); @@ -1064,11 +1298,16 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); + + if (of_property_read_bool(pdev->dev.of_node, "has-io-mode")) + xqspi->io_mode = true; + /* QSPI controller initializations */ zynqmp_qspi_init_hw(xqspi); pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); + xqspi->irq = platform_get_irq(pdev, 0); if (xqspi->irq <= 0) { ret = -ENXIO; @@ -1082,8 +1321,37 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) goto clk_dis_all; } - master->num_chipselect = GQSPI_DEFAULT_NUM_CS; + xqspi->rx_bus_width = GQSPI_RX_BUS_WIDTH_SINGLE; + for_each_available_child_of_node(pdev->dev.of_node, nc) { + ret = of_property_read_u32(nc, "spi-rx-bus-width", + &rx_bus_width); + if (!ret) { + xqspi->rx_bus_width = rx_bus_width; + break; + } + } + if (ret) + dev_err(dev, "rx bus width not found\n"); + + xqspi->tx_bus_width = GQSPI_TX_BUS_WIDTH_SINGLE; + for_each_available_child_of_node(pdev->dev.of_node, nc) { + ret = of_property_read_u32(nc, "spi-tx-bus-width", + &tx_bus_width); + if (!ret) { + xqspi->tx_bus_width = tx_bus_width; + break; + } + } + if (ret) + dev_err(dev, "tx bus width not found\n"); + + ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); + if (ret < 0) + master->num_chipselect = GQSPI_DEFAULT_NUM_CS; + else + master->num_chipselect = num_cs; + dma_set_mask(&pdev->dev, DMA_BIT_MASK(44)); master->setup = zynqmp_qspi_setup; master->set_cs = zynqmp_qspi_chipselect; master->transfer_one = zynqmp_qspi_start_transfer; @@ -1094,6 +1362,8 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) master->bits_per_word_mask = SPI_BPW_MASK(8); master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; + xqspi->speed_hz = master->max_speed_hz; + master->auto_runtime_pm = true; if (master->dev.parent == NULL) master->dev.parent = &master->dev; @@ -1117,7 +1387,7 @@ remove_master: } /** - * zynqmp_qspi_remove: Remove method for the QSPI driver + * zynqmp_qspi_remove - Remove method for the QSPI driver * @pdev: Pointer to the platform_device structure * * This function is called if a device is physically removed from the system or @@ -1142,11 +1412,6 @@ static int zynqmp_qspi_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id zynqmp_qspi_of_match[] = { - { .compatible = "xlnx,zynqmp-qspi-1.0", }, - { /* End of table */ } -}; - MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match); static struct platform_driver zynqmp_qspi_driver = { |