diff options
Diffstat (limited to 'drivers/pci/controller/pcie-xilinx-nwl.c')
| -rw-r--r-- | drivers/pci/controller/pcie-xilinx-nwl.c | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 11b046b20b92..b51ce573c963 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -38,6 +38,11 @@ #define E_ECAM_CONTROL 0x00000228 #define E_ECAM_BASE_LO 0x00000230 #define E_ECAM_BASE_HI 0x00000234 +#define E_DREG_CTRL 0x00000288 +#define E_DREG_BASE_LO 0x00000290 + +#define DREG_DMA_EN BIT(0) +#define DREG_DMA_BASE_LO 0xFD0F0000 /* Ingress - address translations */ #define I_MSII_CAPABILITIES 0x00000300 @@ -56,6 +61,10 @@ #define MSGF_MSI_STATUS_HI 0x00000444 #define MSGF_MSI_MASK_LO 0x00000448 #define MSGF_MSI_MASK_HI 0x0000044C +/* Root DMA Interrupt register */ +#define MSGF_DMA_MASK 0x00000464 + +#define MSGF_INTR_EN BIT(0) /* Msg filter mask bits */ #define CFG_ENABLE_PM_MSG_FWD BIT(1) @@ -493,7 +502,7 @@ static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, for (i = 0; i < nr_irqs; i++) { irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip, - domain->host_data, handle_simple_irq, + domain->host_data, handle_simple_irq, NULL, NULL); } mutex_unlock(&msi->lock); @@ -501,7 +510,7 @@ static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, } static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs) + unsigned int nr_irqs) { struct irq_data *data = irq_domain_get_irq_data(domain, virq); struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); @@ -755,7 +764,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) /* Enable all misc interrupts */ nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); - /* Disable all legacy interrupts */ nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); @@ -763,6 +771,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); + /* Enabling DREG translations */ + nwl_bridge_writel(pcie, DREG_DMA_EN, E_DREG_CTRL); + nwl_bridge_writel(pcie, DREG_DMA_BASE_LO, E_DREG_BASE_LO); + /* Enabling Root DMA interrupts */ + nwl_bridge_writel(pcie, MSGF_INTR_EN, MSGF_DMA_MASK); + /* Enable all legacy interrupts */ nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); @@ -844,12 +858,7 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie->clk = devm_clk_get(dev, NULL); if (IS_ERR(pcie->clk)) return PTR_ERR(pcie->clk); - - err = clk_prepare_enable(pcie->clk); - if (err) { - dev_err(dev, "can't enable PCIe ref clock\n"); - return err; - } + clk_prepare_enable(pcie->clk); err = nwl_pcie_bridge_init(pcie); if (err) { |