diff options
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-tmc.h')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-tmc.h | 52 |
1 files changed, 50 insertions, 2 deletions
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index b91ec7dde7bc..f7ed954a241d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -13,6 +13,8 @@ #include <linux/mutex.h> #include <linux/refcount.h> +#include "coresight-quirks.h" + #define TMC_RSZ 0x004 #define TMC_STS 0x00c #define TMC_RRD 0x010 @@ -70,7 +72,8 @@ #define TMC_AXICTL_PROT_CTL_B0 BIT(0) #define TMC_AXICTL_PROT_CTL_B1 BIT(1) #define TMC_AXICTL_SCT_GAT_MODE BIT(7) -#define TMC_AXICTL_WR_BURST_16 0xF00 +#define TMC_AXICTL_WR_BURST(v) (((v) & 0xf) << 8) +#define TMC_AXICTL_WR_BURST_16 0xf /* Write-back Read and Write-allocate */ #define TMC_AXICTL_AXCACHE_OS (0xf << 2) #define TMC_AXICTL_ARCACHE_OS (0xf << 16) @@ -92,6 +95,7 @@ #define TMC_DEVID_AXIAW_MASK 0x7f #define TMC_AUTH_NSID_MASK GENMASK(1, 0) +#define TMC_AUTH_SID_MASK GENMASK(5, 4) enum tmc_config_type { TMC_CONFIG_TYPE_ETB, @@ -130,10 +134,14 @@ enum tmc_mem_intf_width { #define CORESIGHT_SOC_600_ETR_CAPS \ (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) +/* Marvell OcteonTx CN9xxx TMC-ETR unadvertised capabilities */ +#define OCTEONTX_CN9XXX_ETR_CAPS (TMC_ETR_SAVE_RESTORE) + enum etr_mode { ETR_MODE_FLAT, /* Uses contiguous flat buffer */ ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ ETR_MODE_CATU, /* Use SG mechanism in CATU */ + ETR_MODE_SECURE, /* Use Secure buffer */ }; struct etr_buf_operations; @@ -163,6 +171,20 @@ struct etr_buf { }; /** + * struct etr_tsync_data - Timer based sync insertion data management + * @syncs_per_fill: syncs inserted per buffer wrap + * @prev_rwp: writepointer for the last sync insertion + * @len_thold: Buffer length threshold for inserting syncs + * @tick: Tick interval in ns + */ +struct etr_tsync_data { + int syncs_per_fill; + u64 prev_rwp; + u64 len_thold; + u64 tick; +}; + +/** * struct tmc_drvdata - specifics associated to an TMC component * @base: memory mapped base address for this component. * @csdev: component vitals needed by the framework. @@ -174,6 +196,8 @@ struct etr_buf { * @etr_buf: details of buffer used in TMC-ETR * @len: size of the available trace for ETF/ETB. * @size: trace buffer size for this TMC (common for all modes). + * @max_burst_size: The maximum burst size that can be initiated by + * TMC-ETR on AXI bus. * @mode: how this TMC is being used. * @config_type: TMC variant, must be of type @tmc_config_type. * @memwidth: width of the memory interface databus, in bytes. @@ -198,7 +222,11 @@ struct tmc_drvdata { }; u32 len; u32 size; + u32 max_burst_size; u32 mode; + u32 etr_quirks; + int cpu; + int rc_cpu; enum tmc_config_type config_type; enum tmc_mem_intf_width memwidth; u32 trigger_cntr; @@ -207,6 +235,9 @@ struct tmc_drvdata { struct mutex idr_mutex; struct etr_buf *sysfs_buf; struct etr_buf *perf_buf; + void *etm_source; + struct etr_tsync_data tsync_data; + struct hrtimer timer; }; struct etr_buf_operations { @@ -288,7 +319,24 @@ tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \ TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI) TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI) -TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI) + +static inline u64 tmc_read_dba(struct tmc_drvdata *drvdata) +{ + if (drvdata->etr_quirks & CORESIGHT_QUIRK_ETR_FORCE_64B_DBA_RW) + return readq(drvdata->base + TMC_DBALO); + + return coresight_read_reg_pair(drvdata->base, TMC_DBALO, TMC_DBAHI); +} + +static inline void tmc_write_dba(struct tmc_drvdata *drvdata, u64 val) +{ + if (drvdata->etr_quirks & CORESIGHT_QUIRK_ETR_FORCE_64B_DBA_RW) { + writeq(val, drvdata->base + TMC_DBALO); + return; + } + + coresight_write_reg_pair(drvdata->base, val, TMC_DBALO, TMC_DBAHI); +} /* Initialise the caps from unadvertised static capabilities of the device */ static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps) |