diff options
Diffstat (limited to 'arch/arm64/Kconfig')
| -rw-r--r-- | arch/arm64/Kconfig | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 861a8aad9a17..f02465ce8e25 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -761,6 +761,45 @@ config HISILICON_ERRATUM_161600802 If unsure, say Y. +config CAVIUM_ERRATUM_36890 + bool "Cavium erratum 36890" + default y + help + Enable workaround for erratum 36890. On all ThunderX T88xx and + OcteonTX1 T81/T83 and some OcteonTX2 chips, the "dc zva" instruction + does not work all the time. This happens when there are two VAs + that match up with one PA; including when the two VAs match but have + different asids. The fix is to disable "dc zva" in userspace. + + If unsure, say Y. + +config MRVL_ERRATUM_38500 + bool "Marvell erratum 38500" + default y + help + Enable workaround for erratum 38500. T8x ARM CPU can incorrectly + forward data from an older store to a younger load. When this happens + L1 Dcache parity error occurs in hardware and Synchronous parity error + abort is raised to software. To workaround this erratum, nops are + introduced in between loads and stores. + + If unsure, say Y. + +config MRVL_ERRATUM_38545 + bool "Marvell erratum 38545" + default y + help + On some OcteonTX2 chips, an issue exists wherein when an interrupt + is pending and a second interrupt arrives at the core under certain + stall conditions, a read of interrpt acknowledge register will return + the first interrupt but not acknowledge it. A second read of IAR will + return the first interrupt again, not the second interrupt. To + workaround, software checks the active interrupt priorities before + and after PE acknowledges interrupt in sw. The PE ignores interrupt + if there was no change in acitive priorities. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y @@ -814,6 +853,14 @@ config SOCIONEXT_SYNQUACER_PREITS endmenu +config MRVL_OCTEONTX_EL0_INTR + bool "Handle interrupts in EL0 via EL3" + default y + help + Handle certain interrupts in EL0 with the help of EL3 firmware to achieve + low latency and also not break task isolation. + Generally implemented and tested on OcteonTx and its successive + generation CPUs. choice prompt "Page size" @@ -1175,6 +1222,7 @@ config FORCE_MAX_ZONEORDER config UNMAP_KERNEL_AT_EL0 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT default y + depends on !GTI_WATCHDOG help Speculation attacks against some high-performance processors can be used to bypass MMU permission checks and leak kernel data to |