diff options
Diffstat (limited to 'Documentation/devicetree')
117 files changed, 5355 insertions, 90 deletions
diff --git a/Documentation/devicetree/bindings/arm/zynq/zynq-efuse.txt b/Documentation/devicetree/bindings/arm/zynq/zynq-efuse.txt new file mode 100644 index 000000000000..39817e9750c3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zynq/zynq-efuse.txt @@ -0,0 +1,15 @@ +Device tree bindings for Zynq's eFuse Controller + +The Zynq eFuse controller provides the access to the chip efuses which contain +information about device DNA, security settings and also device status. + +Required properties: + compatible: Compatibility string. Must be "xlnx,zynq-efuse". + reg: Specify the base and size of the EFUSE controller registers + in the memory map. E.g.: reg = <0xf800d000 0x20>; + +Example: +efuse: efuse@f800d000 { + compatible = "xlnx,zynq-efuse"; + reg = <0xf800d000 0x20>; +}; diff --git a/Documentation/devicetree/bindings/arm/zynq/zynq-ocmc.txt b/Documentation/devicetree/bindings/arm/zynq/zynq-ocmc.txt new file mode 100644 index 000000000000..b6dbf05b4eb5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zynq/zynq-ocmc.txt @@ -0,0 +1,17 @@ +Device tree bindings for Zynq's OCM Controller + +The OCM is divided to 4 64kB segments which can be separately configured +to low or high location. Location is controlled via SLCR. + +Required properties: + compatible: Compatibility string. Must be "xlnx,zynq-ocmc-1.0". + reg: Specify the base and size of the OCM controller registers + in the memory map. E.g.: reg = <0xf800c000 0x1000>; + +Example: +ocmc: ocmc@f800c000 { + compatible = "xlnx,zynq-ocmc-1.0"; + interrupt-parent = <&intc>; + interrupts = <0 3 4>; + reg = <0xf800c000 0x1000>; +} ; diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt index 7561cc4de371..d34f11771d5f 100644 --- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt +++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt @@ -38,6 +38,8 @@ Required properties: Optional properties: - ceva,broken-gen2: limit to gen1 speed instead of gen2. + - dma-coherent: Enable this flag if CCI is enabled in design. + Adding this flag configures AXI cache control register. Examples: ahci@fd0c0000 { @@ -56,4 +58,5 @@ Examples: ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; ceva,broken-gen2; + dma-coherent; }; diff --git a/Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt b/Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt new file mode 100644 index 000000000000..8b52017cf1c3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt @@ -0,0 +1,156 @@ +Binding for IDT 8T49N24x Universal Frequency Translator + +The 8T49N241 has one fractional-feedback PLL that can be used as a +jitter attenuator and frequency translator. It is equipped with one +integer and three fractional output dividers, allowing the generation +of up to four different output frequencies, ranging from 8kHz to 1GHz. +These frequencies are completely independent of each other, the input +reference frequencies and the crystal reference frequency. The device +places virtually no constraints on input to output frequency conversion, +supporting all FEC rates, including the new revision of ITU-T +Recommendation G.709 (2009), most with 0ppm conversion error. +The outputs may select among LVPECL, LVDS, HCSL or LVCMOS output levels. + +The driver can read a full register map from the DT, and will use that +register map to initialize the attached part (via I2C) when the system +boots. Any configuration not supported by the common clock framework +must be done via the full register map, including optimized settings. + +The 8T49N241 accepts up to two differential or single-ended input clocks +and a fundamental-mode crystal input. The internal PLL can lock to either +of the input reference clocks or just to the crystal to behave as a +frequency synthesizer. The PLL can use the second input for redundant +backup of the primary input reference, but in this case, both input clock +references must be related in frequency. + +All outputs are currently assumed to be LVDS, unless overridden in the +full register map in the DT. + +==I2C device node== + +Required properties: +- compatible: shall be one of "idt,idt8t49n241" +- reg: i2c device address, shall be one of 0x7C, 0x6C, 0x7D, 0x6D, + 0x7E, 0x6E, 0x7F, 0x6F. +- #clock-cells: From common clock bindings: Shall be 1. + +- clocks: from common clock binding; input clock handle. Required. +- clock-names: from common clock binding; clock input names, shall be + one of "input-clk0", "input-clk1", "input-xtal". Required. + +==Mapping between clock specifier and physical pins== + +When referencing the provided clock in the DT using phandle and +clock specifier, the following mapping applies: + +8T49N241: + 0 -- Q0 + 1 -- Q1 + 2 -- Q2 + 3 -- Q3 + +==Example== + +/* Example1: 25MHz input clock (via CLK0) */ + +ref25: ref25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; +}; + +i2c-master-node { + + /* IDT 8T49N241 i2c universal frequency translator */ + i2c241: clock-generator@6a { + compatible = "idt,idt8t49n241"; + reg = <0x6c>; + #clock-cells = <1>; + + /* Connect input-clk0 to 25MHz reference */ + clocks = <&ref25m>; + clock-names = "input-clk0"; + }; +}; + +/* Consumer referencing the 8T49N241 pin Q1 */ +consumer { + ... + clocks = <&i2c241 1>; + ... +} + +/* Example2: 40MHz xtal frequency, specify all settings */ + +ref40: ref40m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; +}; + +i2c-master-node { + + /* IDT 8T49N241 i2c universal frequency translator */ + i2c241: clock-generator@6a { + compatible = "idt,idt8t49n241"; + reg = <0x6c>; + #clock-cells = <1>; + + /* Connect input-xtal to 40MHz reference */ + clocks = <&ref40m>; + clock-names = "input-xtal"; + + settings=[ +09 50 00 60 67 C5 6C FF 03 00 30 00 00 01 00 00 +01 07 00 00 07 00 00 77 6D 06 00 00 00 00 00 FF +FF FF FF 00 3F 00 2A 00 16 33 33 00 01 00 00 D0 +00 00 00 00 00 00 00 00 00 04 00 00 00 02 00 00 +00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 D7 0A 2B 20 00 00 00 0B +00 00 00 00 00 00 00 00 00 00 27 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +C3 00 08 01 00 00 00 00 00 00 00 00 00 30 00 00 +00 0A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 85 00 00 9C 01 D4 02 71 07 00 00 00 +00 83 00 10 02 08 8C +]; + }; +}; diff --git a/Documentation/devicetree/bindings/clock/silabs,si5324.txt b/Documentation/devicetree/bindings/clock/silabs,si5324.txt new file mode 100644 index 000000000000..642af113aa6e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si5324.txt @@ -0,0 +1,78 @@ +Binding for Silicon Labs si5324, si5328 and si5319 programmable +I2C clock generator. + +Reference +This binding uses the common clock binding[1]. +The si5324 is programmable i2c low-bandwidth, jitter-attenuating, precision +clock multiplier with up to 2 output clocks. The internal structure can be +found in [2]. +The internal pin structure of si5328 and si5319 can be found in [3]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Si5324 Data Sheet + http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5324.pdf +[3] Si53xx Reference Manual + http://www.silabs.com/Support%20Documents/TechnicalDocs/ + Si53xxReferenceManual.pdf + +==I2C device node== + +Required properties: +- compatible: should be one of + "silabs,si5324" + "silabs,si5319" + "silabs,si5328" +- reg: i2c device address. +- #clock-cells: from common clock binding; shall be set to 1. +- clocks: from common clock binding; list of parent clock + handles, clock name should be one of + "xtal" + "clkin1" + "clkin2" +- #address-cells: shall be set to 1. +- #size-cells: shall be set to 0. + +Optional properties: +- silabs,pll-source: pair of (number, source) for each pll. Allows + to overwrite clock source of pll. + +==Child nodes== + +Each of the clock outputs can be overwritten individually by +using a child node to the I2C device node. If a child node for a clock +output is not set, the eeprom configuration is not overwritten. + +Required child node properties: +- reg: number of clock output. +- clock-frequency: default output frequency at power on + +Optional child node properties: +- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. + +Example: +Following example describes the ZCU102 board with hdmi design which +uses si5319 as clock generator. XTAL is hard-wired on the board to act +as input clock with a frequency of 114.285MHz. + +refhdmi: refhdmi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <114285000>; +}; + +/* Si5319 i2c clock generator */ +si5319: clock-generator@68 { + status = "okay"; + compatible = "silabs,si5319"; + reg = <0x68>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + clocks = <&refhdmi>; + clock-names = "xtal"; + + clk0 { + reg = <0>; + clock-frequency = <27000000>; + }; +}; diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt new file mode 100644 index 000000000000..94a27f65bcac --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.txt @@ -0,0 +1,48 @@ +-------------------------------------------------------------------------- +Device Tree Clock bindings for the Xilinx Versal +-------------------------------------------------------------------------- +The clock controller is a h/w block of Xilinx versal clock tree. It reads +required input clock frequencies from the devicetree and acts as clock provider +for all clock consumers of PS clocks. + +See clock_bindings.txt for more information on the generic clock bindings. + +Required properties: + - #clock-cells: Must be 1 + - compatible: Must contain: "xlnx,versal-clk" + - clocks: List of clock specifiers which are external input + clocks to the given clock controller. Please refer + the next section to find the input clocks for a + given controller. + - clock-names: List of clock names which are exteral input clocks + to the given clock controller. Please refer to the + clock bindings for more details. + +Input clocks for Xilinx Versal clock controller: + +The Xilinx Versal has one primary and two alternative reference clock inputs. +These required clock inputs are: + - ref_clk + - alt_ref_clk + - pl_alt_ref_clk + +Output clocks are registered based on clock information received +from firmware. Output clocks indexes are mentioned in +include/dt-bindings/clock/xlnx-versal-clk.h. + +------- +Example +------- + +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + versal_clk: clock-controller { + #clock-cells = <1>; + compatible = "xlnx,versal-clk"; + clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; + clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt new file mode 100644 index 000000000000..226bfb9261d7 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.txt @@ -0,0 +1,12 @@ +Xilinx ZynqMP AES hw acceleration support + +The ZynqMP PS-AES hw accelerator is used to encrypt/decrypt +the given user data. + +Required properties: +- compatible: should contain "xlnx,zynqmp-aes" + +Example: + zynqmp_aes { + compatible = "xlnx,zynqmp-aes"; + }; diff --git a/Documentation/devicetree/bindings/crypto/zynqmp-rsa.txt b/Documentation/devicetree/bindings/crypto/zynqmp-rsa.txt new file mode 100644 index 000000000000..6b4c0e0446fc --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/zynqmp-rsa.txt @@ -0,0 +1,12 @@ +Xilinx ZynqMP RSA hw acceleration support + +The zynqmp PS-RSA hw accelerator is used to encrypt/decrypt +the given user data. + +Required properties: +- compatible: should contain "xlnx,zynqmp-rsa" + +Example: + xlnx_rsa: zynqmp_rsa { + compatible = "xlnx,zynqmp-rsa"; + }; diff --git a/Documentation/devicetree/bindings/crypto/zynqmp-sha.txt b/Documentation/devicetree/bindings/crypto/zynqmp-sha.txt new file mode 100644 index 000000000000..c7be6e2ce246 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/zynqmp-sha.txt @@ -0,0 +1,12 @@ +Xilinx ZynqMP SHA3(keccak-384) hw acceleration support. + +The ZynqMp PS-SHA hw accelerator is used to calculate the +SHA3(keccak-384) hash value on the given user data. + +Required properties: +- compatible: should contain "xlnx,zynqmp-keccak-384" + +Example: + xlnx_keccak_384: sha384 { + compatible = "xlnx,zynqmp-keccak-384"; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/bridge.txt b/Documentation/devicetree/bindings/display/xlnx/bridge.txt new file mode 100644 index 000000000000..c5f7c0a1dea0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/bridge.txt @@ -0,0 +1,29 @@ +Xilinx DRM bridge +----------------- + +The Xilinx DRM provides the interface layer called Xilinx bridge to bridge +multiple components with a series of functions. It models a simple +unidirectional communication, single client -> single bridge. The client +is not limited to DRM compatible drivers, but can be any subsystem driver, +but the client driver should call the bridge functions explicitly. + +Provider +-------- + +The bridge provider should assign a corresponding of_node to struct xlnx_bridge. +For example, if its own node is used, + + provider_node: provider_node { + }; + + bridge.of_node = provider_device->of_node; + +Client +------ + +The bridge client should have a phandle to the bridge device node. The bridge +device node should be passed to get a bridge instance, + + client_node { + xlnx,bridge = <&provider_node>; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt new file mode 100644 index 000000000000..55508167e606 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt @@ -0,0 +1,73 @@ +Device-Tree bindings for Xilinx MIPI DSI Tx IP core + +The IP core supports transmission of video data in MIPI DSI protocol. + +Required properties: + - compatible: Should be "xlnx,dsi". + + - reg: Base address and size of the IP core. + + - xlnx,dsi-datatype: Color format. The value should be one of "MIPI_DSI_FMT_RGB888", + "MIPI_DSI_FMT_RGB666", "MIPI_DSI_FMT_RGB666_PACKED" or "MIPI_DSI_FMT_RGB565". + + - simple_panel: The subnode for connected panel. This represents the + DSI peripheral connected to the DSI host node. Please refer to + Documentation/devicetree/bindings/display/mipi-dsi-bus.txt. The + simple-panel driver has auo,b101uan01 panel timing parameters added along + with other existing panels. DSI driver derive the required Tx IP controller + timing values from the panel timing parameters. + + - port: Logical block can be used / connected independently with + external device. In the display controller port nodes, topology + for entire pipeline should be described using the DT bindings defined in + Documentation/devicetree/bindings/graph.txt. + + - xlnx,dsi-num-lanes: Possible number of DSI lanes for the Tx controller. + The values should be 1, 2, 3 or 4. Based on xlnx,dsi-num-lanes and + line rate for the MIPI D-PHY core in Mbps, the AXI4-stream received by + Xilinx MIPI DSI Tx IP core adds markers as per DSI protocol and the packet + thus framed is convered to serial data by MIPI D-PHY core. Please refer + Xilinx pg238 for more details. This value should be equal to the number + of lanes supported by the connected DSI panel. Panel has to support this + value or has to be programmed to the same value that DSI Tx controller is + configured to. + + - clocks: List of phandles to Video and 200Mhz DPHY clocks. + + - clock-names: Must contain "s_axis_aclk" and "dphy_clk_200M" in same order as + clocks listed in clocks property. + +Required simple_panel properties: + - compatible: Value should be one of the panel names in + Documentation/devicetree/bindings/display/panel/. e.g. "auo,b101uan01". + For available panel compatible strings, please refer to bindings in + Documentation/devicetree/bindings/display/panel/ + +Optional properties: + - xlnx,vpss: vpss phandle + This handle is required only when VPSS is connected to DSI as bridge. + +Example: + +#include <dt-bindings/drm/mipi-dsi.h> + mipi_dsi_tx_subsystem@80000000 { + compatible = "xlnx,dsi"; + reg = <0x0 0x80000000 0x0 0x10000>; + xlnx,dsi-num-lanes = <4>; + xlnx,dsi-data-type = <MIPI_DSI_FMT_RGB888>; + #address-cells = <1>; + #size-cells = <0>; + xlnx,vpss = <&v_proc_ss_0>; + clock-names = "dphy_clk_200M", "s_axis_aclk"; + clocks = <&misc_clk_0>, <&misc_clk_1>; + encoder_dsi_port: port@0 { + reg = <0>; + dsi_encoder: endpoint { + remote-endpoint = <&xyz_port>; + }; + }; + simple_panel: simple-panel@0 { + compatible = "auo,b101uan01"; + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,mixer.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,mixer.txt new file mode 100644 index 000000000000..20f4cec27175 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,mixer.txt @@ -0,0 +1,163 @@ +Device-Tree bindings for Xilinx Video Mixer IP core + +The IP core provides a flexible video processing block for alpha blending +and compositing multiple video and/or graphics layers. +Support for up to sixteen layers based on IP version, with an optional logo +layer, using a combination of video inputs from either frame buffer or +streaming video cores (through AXI4-Stream interfaces) is provided. +The Video Mixer always has one streaming input layer, known as master layer. + +Required properties: + - compatible: Must contain atleast one of + "xlnx,mixer-4.0" (MIXER 4.0 version) + "xlnx,mixer-3.0" (MIXER 3.0 version) + - reg: Base address and size of the IP core. + - interrupts: Interrupt number. + - interrupts-parent: phandle for interrupt controller. + - reset-gpio: gpio to reset the mixer IP + - xlnx,dma-addr-width: dma address width, valid values are 32 and 64 + - xlnx,bpc: bits per component for mixer + - xlnx,ppc: pixel per clock for mixer + - xlnx,num-layers: Total number of layers (excluding logo) + Value ranges from 1-9 for compatible string xlnx,mixer-3.0 and + Value ranges from 1-17 for comptaible string xlnx,mixer-4.0 + - layer_[x]: node for [x] layer + - xlnx,layer-id: layer identifier number + - xlnx,vformat: video format for layer. See list of supported formats below. + - xlnx,layer-max-width: max layer width, mandatory for master layer + for overlay layers if scaling is alowed then this is mandatory otherwise + not required for overlay layers + - xlnx,layer-max-height: max layer height, mandatory for master layer + Not required for overlay layers + - xlnx,layer-primary: denotes the primary layer, should be mentioned in node + of layer which is expected to be constructing the primary plane + +Optional properties: + - dmas: dma attach to layer, mandatory for master layer + for rest other layers its optional + - dma-names: Should be "dma0", for more details on DMA identifier string + refer Documentation/devicetree/bindings/dma/dma.txt + - xlnx,layer-streaming: denotes layer can be streaming, + mandatory for master layer. Streaming layers need external dma, where + as non streaming layers read directly from memory. + - xlnx,layer-alpha: denotes layer can do alpha compositing + - xlnx,layer-scale: denotes layer can be scale to 2x and 4x + - xlnx,logo-layer: denotes logo layer is enable + - logo: logo layer + - xlnx,bridge: phandle to bridge node. + This handle is required only when VTC is connected as bridge. + +Supported Formats: + Mixer IP Format Driver supported Format String + BGR888 "RG24" + RGB888 "BG24" + XBGR2101010 "XB30" + XRGB8888 "XR24" + RGBA8888 "RA24" + ABGR8888 "AB24" + ARGB8888 "AR24" + XBGR8888 "XB24" + YUYV "YUYV" + UYVY "UYVY" + AYUV "AYUV" + NV12 "NV12" + NV16 "NV16" + Y8 "GREY" + Y10 "Y10 " (Note: Space included) + XVUY2101010 "XV30" + VUY888 "VU24" + XVUY8888 "XV24" + XV15 "XV15" + XV20 "XV20" +Note : Format strings are case sensitive. + +Example: + v_mix_0: v_mix@80100000 { + compatible = "xlnx,mixer-3.0"; + interrupt-parent = <&gic>; + interrupts = <0 93 4>; + reg = <0x0 0x80100000 0x0 0x80000>; + + xlnx,dma-addr-width=<32>; + reset-gpios = <&gpio 1 1>; + + xlnx,bpc = <8>; + xlnx,ppc = <2>; + xlnx,num-layers = <8>; + xlnx,logo-layer; + xlnx,bridge = <&v_tc_0>; + + mixer_port: mixer_port@0 { + reg = <0>; + mixer_crtc: endpoint { + remote-endpoint = <&sdi_encoder>; + }; + }; + xv_mix_master: layer_0 { + xlnx,layer-id = <0>; + xlnx,vformat = "YUYV"; + xlnx,layer-max-width = <4096>; + xlnx,layer-height = <2160>; + dmas = <&axi_vdma_0 0>; + dma-names = "dma0"; + xlnx,layer-streaming; + xlnx,layer-primary; + }; + xv_mix_overlay_1: layer_1 { + xlnx,layer-id = <1>; + xlnx,vformat = "NV16"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_2: layer_2 { + xlnx,layer-id = <2>; + xlnx,vformat = "YUYV"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_3: layer_3 { + xlnx,layer-id = <3>; + xlnx,vformat = "AYUV"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_4: layer_4 { + xlnx,layer-id = <4>; + xlnx,vformat = "GREY"; + dmas = <&scaler_v_frmbuf_rd_0 0>; + dma-names = "dma0"; + xlnx,layer-streaming; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_5: layer_5 { + xlnx,layer-id = <5>; + xlnx,vformat = "AB24"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_6: layer_6 { + xlnx,layer-id = <6>; + xlnx,vformat = "XB24"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_7: layer_7 { + xlnx,layer-id = <7>; + xlnx,vformat = "BG24"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_logo: logo { + xlnx,layer-id = <8>; + xlnx,logo-height = <64>; + xlnx,logo-width = <64>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,pl-disp.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,pl-disp.txt new file mode 100644 index 000000000000..c6034bffc64a --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,pl-disp.txt @@ -0,0 +1,41 @@ +Xilinx PL Display driver +------------------------ + +Pl_Display is a logical device to provide completeness to xilinx display +pipeline. This is a software driver for providing drm components crtc +and plane for various IPs using xilinx display pipelines. + +A linear pipeline with multiple blocks: +DMA --> PL_Display --> SDI + +Required properties: + +- compatible: Must be "xlnx,pl-disp" +- dmas: dma attach to pipeline +- dma-names: names for dma +- xlnx,vformat: video format for layer +- port: Logical block can be used / connected independently with + external device. In the display controller port nodes, topology + for entire pipeline should be described using the DT bindings defined in + Documentation/devicetree/bindings/graph.txt. +- reg: Base address and size of device + +Optional properties: + - xlnx,bridge: bridge phandle + This handle is required only when VTC is connected as bridge. + +Example: + + drm-pl-disp-drv { + compatible = "xlnx,pl-disp"; + dmas = <&axi_vdma_0 0>; + dma-names = "dma0"; + xlnx,vformat = "YUYV"; + xlnx,bridge = <&v_tc_0>; + pl_disp_port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&sdi_port>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,sdi-tx.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,sdi-tx.txt new file mode 100644 index 000000000000..971ac5304761 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,sdi-tx.txt @@ -0,0 +1,54 @@ +Device-Tree bindings for Xilinx SDI Tx subsystem + +The IP core supports transmission of video data in SDI Tx protocol + +Required properties: + - compatible: Should be "xlnx,sdi-tx". + - interrupts: Interrupt number. + - interrupts-parent: phandle for interrupt controller. + - reg: Base address and size of the IP core. + - port: Logical block can be used / connected independently with + external device. In the display controller port nodes, topology + for entire pipeline should be described using the DT bindings defined in + Documentation/devicetree/bindings/graph.txt. + Minimum one port is required. At max, 2 ports are present. + The reg index for AXI4 stream port is 0 and for ancillary data is 1. + - clocks: List of phandles to AXI Lite, Video and SDI Tx Clock + - clock-names: Must contain "s_axi_aclk", "video_in_clk" and "sdi_tx_clk" + in same order as clocks listed in clocks property. + +Optional properties: + - xlnx,vpss: vpss phandle + This handle is required only when VPSS is connected to SDI as bridge. + - xlnx,tx-insert-c-str-st352: Insert ST352 payload in Chroma stream. + +Example: + + sdi_tx_subsystem@80000000 { + compatible = "xlnx,sdi-tx"; + reg = <0x0 0x80000000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 90 4>; + #address-cells = <1>; + #size-cells = <0>; + xlnx,vpss = <&v_proc_ss_0>; + clock-names = "s_axi_aclk", "video_in_clk", "sdi_tx_clk"; + clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>; + ports { + #address-cells = <1>; + #size-cells = <0>; + encoder_sdi_port: port@0 { + reg = <0>; + sdi_encoder: endpoint { + remote-endpoint = <&pl_disp_crtc>; + }; + }; + + sdi_audio_port: port@1 { + reg = <1>; + sdi_audio_sink_port: endpoint { + remote-endpoint = <&sditx_audio_embed_src_port>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-csc.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-csc.txt new file mode 100644 index 000000000000..cf80d185d429 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-csc.txt @@ -0,0 +1,35 @@ +Xllinx VPSS Color Space Converter +----------------------------------------- +The Xilinx VPSS Color Space Converter is a Video IP that supports +color space conversion from RGB to YUV 444/422/420 and vice versa. + +Required properties: + +- compatible: Must be "xlnx,vpss-csc". + +- reg: Physical base address and length of registers set for the device. + +- xlnx,video-width: This property qualifies the video format with sample + width expressed as a number of bits per pixel component. Supported video + width values are 8/10/12/16. + +-reset-gpios: GPIO specifier to assert/de-assert the reset line. + +- clocks: phandle to IP clock. + +- xlnx,max-width: Maximum number of pixels in a line. + Valid range from 64 to 8192. + +- xlnx,max-height: Maximum number of lines in a frame. + Valid range from 64 to 4320. + +Example: + csc@a0040000 { + compatible = "xlnx,vpss-csc"; + reg = <0x0 0xa0040000 0x0 0x10000>; + reset-gpios = <&gpio 0x0 GPIO_ACTIVE_LOW>; + xlnx,video-width = <8>; + clocks = <&misc_clk_0>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + } diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-scaler.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-scaler.txt new file mode 100644 index 000000000000..8920b81e2779 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-scaler.txt @@ -0,0 +1,51 @@ +Xilinx VPSS Scaler +------------------ +The Xilinx VPSS Scaler is a Video IP that supports up scaling, +down scaling and no scaling functionailty. This supports custom +resolution values between 0 to 4096. + +Required properties: + +- compatible: Must be "xlnx,vpss-scaler". + +- reg: Physical base address and length of registers set for the device. + +- xlnx,num-hori-taps: The number of horizontal taps for scaling filter + supported tap values are 2/4/6/8/10/12. + +- xlnx,num-vert-taps: The number of vertical taps for scaling filter + supported tap values are 2/4/6/8/10/12. + + A value of 2 represents bilinear filters. A value of 4 represents bicubic. + Values 6, 8, 10, 12 represent polyphase filters. + +- xlnx,pix-per-clk : The pixels per clock property of the IP. + supported values are 1 and 2. + +- reset-gpios: GPIO specifier to assert/de-assert the reset line. + +- clocks: List of phandles to AXI Lite and Video clock + +- clock-names: Must contain "aclk_ctrl" and "aclk_axis" in same order as clocks + listed in clocks property. + +- xlnx,max-width: Maximum number of pixels in a line. + Valid range from 64 to 8192. + +- xlnx,max-height: Maximum number of lines in a frame. + Valid range from 64 to 4320. + +Example: + scaler@a0040000 { + compatible = "xlnx,vpss-scaler"; + reg = <0x0 0xa0000000 0x0 0x40000>; + reset-gpios = <&gpio 0x0 GPIO_ACTIVE_LOW>; + xlnx,num-hori-taps = <8>; + xlnx,num-vert-taps = <8>; + xlnx,pix-per-clk = <2>; + clock-names = "aclk_ctrl", "aclk_axis"; + clocks = <&misc_clk_0>, <&misc_clk_1>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + } + diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.txt new file mode 100644 index 000000000000..6a4d5bcc5e59 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.txt @@ -0,0 +1,32 @@ +Device-Tree bindings for Xilinx Video Timing Controller(VTC) + +Xilinx VTC is a general purpose video timing generator and detector. +The input side of this core automatically detects horizontal and +vertical synchronization, pulses, polarity, blanking timing and active pixels. +While on the output, it generates the horizontal and vertical blanking and +synchronization pulses used with a standard video system including support +for programmable pulse polarity. + +The core is commonly used with Video in to AXI4-Stream core to detect the +format and timing of incoming video data or with AXI4-Stream to Video out core +to generate outgoing video timing for downstream sinks like a video monitor. + +For details please refer to +https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_1/pg016_v_tc.pdf + +Required properties: + - compatible: value should be "xlnx,bridge-v-tc-6.1" + - reg: base address and size of the VTC IP + - xlnx,pixels-per-clock: Pixels per clock of the stream. Can be 1, 2 or 4. + - clocks: List of phandles for AXI Lite and Video Clock + - clock-names: Must contain "s_axi_aclk" and "clk" in same order as clocks listed + in clocks property. + +Example: + v_tc_0: v_tc@80030000 { + compatible = "xlnx,bridge-v-tc-6.1"; + reg = <0x0 0x80030000 0x0 0x10000>; + xlnx,pixels-per-clock = <2>; + clock-names = "s_axi_aclk", "clk"; + clocks = <&misc_clk_0>, <&misc_clk_1>; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt new file mode 100644 index 000000000000..46d0c7671ee5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt @@ -0,0 +1,82 @@ +Xilinx ZynqMP DisplayPort subsystem +----------------------------------- + +Required properties: + +- compatible: Must be "xlnx,zynqmp-dpsub-1.7". + +- reg: Physical base address and length of the registers set for the device. +- reg-names: Must be "dp", "blend", "av_buf", and "aud" to map logical register + partitions. + +- interrupts: Interrupt number. +- interrupts-parent: phandle for interrupt controller. + +- clocks: phandles for axi, audio, non-live video, and live video clocks. + axi clock is required. Audio clock is optional. If not present, audio will + be disabled. One of non-live or live video clock should be present. +- clock-names: The identification strings are required. "aclk" for axi clock. + "dp_aud_clk" for audio clock. "dp_vtc_pixel_clk_in" for non-live video clock. + "dp_live_video_in_clk" for live video clock (clock from programmable logic). + +- phys: phandles for phy specifier. The number of lanes is configurable + between 1 and 2. The number of phandles should be 1 or 2. +- phy-names: The identifier strings. "dp-phy" followed by index, 0 or 1. + For single lane, only "dp-phy0" is required. For dual lane, both "dp-phy0" + and "dp-phy1" are required where "dp-phy0" is the primary lane. + +- power-domains: phandle for the corresponding power domain + +- vid-layer, gfx-layer: Required to represent available layers + +Required layer properties + +- dmas: phandles for DMA channels as defined in + Documentation/devicetree/bindings/dma/dma.txt. +- dma-names: The identifier strings are required. "gfx0" for graphics layer + dma channel. "vid" followed by index (0 - 2) for video layer dma channels. + +Optional child node + +- The driver populates any child device node in this node. This can be used, + for example, to populate the sound device from the DisplayPort subsystem + driver. + +Example: + zynqmp-display-subsystem@fd4a0000 { + compatible = "xlnx,zynqmp-dpsub-1.7"; + reg = <0x0 0xfd4a0000 0x0 0x1000>, + <0x0 0xfd4aa000 0x0 0x1000>, + <0x0 0xfd4ab000 0x0 0x1000>, + <0x0 0xfd4ac000 0x0 0x1000>; + reg-names = "dp", "blend", "av_buf", "aud"; + interrupts = <0 119 4>; + interrupt-parent = <&gic>; + + clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk"; + clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>; + + phys = <&lane1>, <&lane0>; + phy-names = "dp-phy0", "dp-phy1"; + + power-domains = <&pd_dp>; + + vid-layer { + dma-names = "vid0", "vid1", "vid2"; + dmas = <&xlnx_dpdma 0>, + <&xlnx_dpdma 1>, + <&xlnx_dpdma 2>; + }; + + gfx-layer { + dma-names = "gfx0"; + dmas = <&xlnx_dpdma 3>; + }; + + dma-names = "vid0", "vid1", "vid2", "gfx0"; + dmas = <&xlnx_dpdma 0>, + <&xlnx_dpdma 1>, + <&xlnx_dpdma 2>, + <&xlnx_dpdma 3>; + }; +}; diff --git a/Documentation/devicetree/bindings/dma/xilinx/axi-cdma.txt b/Documentation/devicetree/bindings/dma/xilinx/axi-cdma.txt new file mode 100644 index 000000000000..6e5c78c5709c --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/axi-cdma.txt @@ -0,0 +1,31 @@ +* Xilinx AXI CDMA Test client + +Required properties: +- compatible: Should be "xlnx,axi-cdma-test-1.00.a" +- dmas: a list of <[CDMA device phandle] [Channel ID]> pairs, + where Channel ID is '0' for write/tx and '1' for read/rx + channel. +- dma-names: a list of CDMA channel names, one per "dmas" entry + +Example: +++++++++ + +cdmatest_0: cdmatest@0 { + compatible ="xlnx,axi-cdma-test-1.00.a"; + dmas = <&axi_cdma_0 0>; + dma-names = "cdma"; +} ; + +Xilinx AXI CDMA Device Node Example +++++++++++++++++++++++++++++++++++++ + +axi_cdma_0: axicdma@7e200000 { + compatible = "xlnx,axi-cdma-1.00.a"; + #dma-cells = <1>; + reg = < 0x7e200000 0x10000 >; + dma-channel@7e200000 { + compatible = "xlnx,axi-cdma-channel"; + interrupts = < 0 55 4 >; + xlnx,datawidth = <0x40>; + } ; +} ; diff --git a/Documentation/devicetree/bindings/dma/xilinx/axi-dma.txt b/Documentation/devicetree/bindings/dma/xilinx/axi-dma.txt new file mode 100644 index 000000000000..f4f5b018dfa5 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/axi-dma.txt @@ -0,0 +1,38 @@ +* Xilinx AXI DMA Test client + +Required properties: +- compatible: Should be "xlnx,axi-dma-test-1.00.a" +- dmas: a list of <[DMA device phandle] [Channel ID]> pairs, + where Channel ID is '0' for write/tx and '1' for read/rx + channel. +- dma-names: a list of DMA channel names, one per "dmas" entry + +Example: +++++++++ + +dmatest_0: dmatest@0 { + compatible ="xlnx,axi-dma-test-1.00.a"; + dmas = <&axi_dma_0 0 + &axi_dma_0 1>; + dma-names = "axidma0", "axidma1"; +} ; + + +Xilinx AXI DMA Device Node Example +++++++++++++++++++++++++++++++++++++ + +axi_dma_0: axidma@40400000 { + compatible = "xlnx,axi-dma-1.00.a"; + #dma-cells = <1>; + reg = < 0x40400000 0x10000 >; + dma-channel@40400000 { + compatible = "xlnx,axi-dma-mm2s-channel"; + interrupts = < 0 59 4 >; + xlnx,datawidth = <0x40>; + } ; + dma-channel@40400030 { + compatible = "xlnx,axi-dma-s2mm-channel"; + interrupts = < 0 58 4 >; + xlnx,datawidth = <0x40>; + } ; +} ; diff --git a/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt new file mode 100644 index 000000000000..acdcc445f01b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt @@ -0,0 +1,67 @@ +* Xilinx PS PCIe Root DMA + +Required properties: +- compatible: Should be "xlnx,ps_pcie_dma-1.00.a" +- reg: Register offset for Root DMA channels +- reg-names: Name for the register. Should be "ps_pcie_regbase" +- interrupts: Interrupt pin for Root DMA +- interrupt-names: Name for the interrupt. Should be "ps_pcie_rootdma_intr" +- interrupt-parent: Should be gic in case of zynqmp +- rootdma: Indicates this platform device is root dma. + This is required as the same platform driver will be invoked by pcie end points too +- dma_vendorid: 16 bit PCIe device vendor id. + This can be later used by dma client for matching while using dma_request_channel +- dma_deviceid: 16 bit PCIe device id + This can be later used by dma client for matching while using dma_request_channel +- numchannels: Indicates number of channels to be enabled for the device. + Valid values are from 1 to 4 for zynqmp +- ps_pcie_channel : One for each channel to be enabled. + This array contains channel specific properties. + Index 0: Direction of channel + Direction of channel can be either PCIe Memory to AXI memory i.e., Host to Card or + AXI Memory to PCIe memory i.e., Card to Host + PCIe to AXI Channel Direction is represented as 0x1 + AXI to PCIe Channel Direction is represented as 0x0 + Index 1: Number of Buffer Descriptors + This number describes number of buffer descriptors to be allocated for a channel + Index 2: Number of Queues + Each Channel has four DMA Buffer Descriptor Queues. + By default All four Queues will be managed by Root DMA driver. + User may choose to have only two queues either Source and it's Status Queue or + Destination and it's Status Queue to be handled by Driver. + The other two queues need to be handled by user logic which will not be part of this driver. + All Queues on Host is represented by 0x4 + Two Queues on Host is represented by 0x2 + Index 3: Coalesce Count + This number indicates the number of transfers after which interrupt needs to + be raised for the particular channel. The allowed range is from 0 to 255 + Index 4: Coalesce Count Timer frequency + This property is used to control the frequency of poll timer. Poll timer is + created for a channel whenever coalesce count value (>= 1) is programmed for the particular + channel. This timer is helpful in draining out completed transactions even though interrupt is + not generated. + +Client Usage: + DMA clients can request for these channels using dma_request_channel API + + +Xilinx PS PCIe Root DMA node Example +++++++++++++++++++++++++++++++++++++ + + pci_rootdma: rootdma@fd0f0000 { + compatible = "xlnx,ps_pcie_dma-1.00.a"; + reg = <0x0 0xfd0f0000 0x0 0x1000>; + reg-names = "ps_pcie_regbase"; + interrupts = <0 117 4>; + interrupt-names = "ps_pcie_rootdma_intr"; + interrupt-parent = <&gic>; + rootdma; + dma_vendorid = /bits/ 16 <0x10EE>; + dma_deviceid = /bits/ 16 <0xD021>; + numchannels = <0x4>; + #size-cells = <0x5>; + ps_pcie_channel0 = <0x1 0x7CF 0x4 0x0 0x3E8>; + ps_pcie_channel1 = <0x0 0x7CF 0x4 0x0 0x3E8>; + ps_pcie_channel2 = <0x1 0x7CF 0x4 0x0 0x3E8>; + ps_pcie_channel3 = <0x0 0x7CF 0x4 0x0 0x3E8>; + }; diff --git a/Documentation/devicetree/bindings/dma/xilinx/vdmatest.txt b/Documentation/devicetree/bindings/dma/xilinx/vdmatest.txt new file mode 100644 index 000000000000..5821fdc3e5e7 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/vdmatest.txt @@ -0,0 +1,39 @@ +* Xilinx Video DMA Test client + +Required properties: +- compatible: Should be "xlnx,axi-vdma-test-1.00.a" +- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, + where Channel ID is '0' for write/tx and '1' for read/rx + channel. +- dma-names: a list of DMA channel names, one per "dmas" entry +- xlnx,num-fstores: Should be the number of framebuffers as configured in + VDMA device node. + +Example: +++++++++ + +vdmatest_0: vdmatest@0 { + compatible ="xlnx,axi-vdma-test-1.00.a"; + dmas = <&axi_vdma_0 0 + &axi_vdma_0 1>; + dma-names = "vdma0", "vdma1"; + xlnx,num-fstores = <0x8>; +} ; + + +Xilinx Video DMA Device Node Example +++++++++++++++++++++++++++++++++++++ +axi_vdma_0: axivdma@44A40000 { + compatible = "xlnx,axi-vdma-1.00.a"; + ... + dma-channel@44A40000 { + ... + xlnx,num-fstores = <0x8>; + ... + } ; + dma-channel@44A40030 { + ... + xlnx,num-fstores = <0x8>; + ... + } ; +} ; diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 93b6d961dd4f..613d775658a2 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -15,7 +15,7 @@ Required properties: - compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or "xlnx,axi-cdma-1.00.a"" - #dma-cells: Should be <1>, see "dmas" property below -- reg: Should contain VDMA registers location and length. +- reg: Should contain DMA registers location and length. - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). - dma-ranges: Should be as the following <dma_addr cpu_addr max_len>. - dma-channel child node: Should have at least one channel and can have up to @@ -38,11 +38,10 @@ Required properties for VDMA: - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. Optional properties for AXI DMA: -- xlnx,sg-length-width: Should be set to the width in bits of the length - register as configured in h/w. Takes values {8...26}. If the property - is missing or invalid then the default value 23 is used. This is the - maximum value that is supported by all IP versions. -- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. +- xlnx,sg-length-width: Should be set to the width of buffer length register as + configured in hardware. If this property is missing or has invalid width + i.e not in range of 8-26, maximum buffer length width (common to all IP + versions) 23 bits is used. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. It takes following values: @@ -69,15 +68,13 @@ Optional child node properties for VDMA: enabled/disabled in hardware. - xlnx,enable-vert-flip: Tells vertical flip is enabled/disabled in hardware(S2MM path). -Optional child node properties for AXI DMA: --dma-channels: Number of dma channels in child node. Example: ++++++++ axi_vdma_0: axivdma@40030000 { compatible = "xlnx,axi-vdma-1.00.a"; - #dma_cells = <1>; + #dma-cells = <1>; reg = < 0x40030000 0x10000 >; dma-ranges = <0x00000000 0x00000000 0x40000000>; xlnx,num-fstores = <0x8>; @@ -104,7 +101,8 @@ axi_vdma_0: axivdma@40030000 { Required properties: - dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, where Channel ID is '0' for write/tx and '1' for read/rx - channel. + channel if both channels are enabled. + If only one channel is enabled either tx or rx the Channel ID is '0'. - dma-names: a list of DMA channel names, one per "dmas" entry Example: diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt new file mode 100644 index 000000000000..5f1e680ffcc2 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dpdma.txt @@ -0,0 +1,91 @@ +Device-Tree bindings for Xilinx ZynqMP DisplayPort Subsystem + +The ZynqMP DisplayPort subsystem handles DMA channel buffer management, +blending, and audio mixing. The DisplayPort subsystem receives display +and audio frames from DPDMA and transmits output to the DisplayPort IP core. + +Required properties: + - compatible: Should be "xlnx,dpdma". + - reg: Base address and size of the IP core. + - interrupts: Interrupt number. + - interrupts-parent: phandle for interrupt controller. + - clocks: phandle for AXI clock + - clock-names: The identification string, "axi_clk", is always required. + +Required child node properties: +- compatible: Should be one of "xlnx,video0", "xlnx,video1", "xlnx,video2", + "xlnx,graphics", "xlnx,audio0", or "xlnx,audio1". + +Example: + + xlnx_dpdma: axidpdma@43c10000 { + compatible = "xlnx,dpdma"; + reg = <0x43c10000 0x1000>; + interrupts = <0 54 4>; + interrupt-parent = <&intc>; + clocks = <&clkc 16>; + clock-names = "axi_clk"; + xlnx,axi-clock-freq = <200000000>; + + dma-channels = <6>; + + #dma-cells = <1>; + dma-video0channel@43c10000 { + compatible = "xlnx,video0"; + }; + dma-video1channel@43c10000 { + compatible = "xlnx,video1"; + }; + dma-video2channel@43c10000 { + compatible = "xlnx,video2"; + }; + dma-graphicschannel@43c10000 { + compatible = "xlnx,graphics"; + }; + dma-audio0channel@43c10000 { + compatible = "xlnx,audio0"; + }; + dma-audio1channel@43c10000 { + compatible = "xlnx,audio1"; + }; + }; + +* DMA client + +Required properties: +- dmas: a list of <[DPDMA device phandle] [Channel ID]> pairs. "Channel ID" + is defined as video0 = 0, video1 = 1, video2 = 2, graphics = 3, audio0 = 4, + and audio1 = 5. + +Example: + + xilinx_drm { + compatible = "xlnx,drm"; + xlnx,encoder-slave = <&xlnx_dp>; + clocks = <&si570 0>; + xlnx,connector-type = "DisplayPort"; + xlnx,dp-sub = <&xlnx_dp_sub>; + planes { + xlnx,pixel-format = "rgb565"; + plane0 { + dmas = <&xlnx_dpdma 3>; + dma-names = "dma"; + }; + plane1 { + dmas = <&xlnx_dpdma 0>; + dma-names = "dma"; + }; + }; + }; + + xlnx_dp_snd_pcm0: dp_snd_pcm0 { + compatible = "xlnx,dp-snd-pcm"; + dmas = <&xlnx_dpdma 4>; + dma-names = "tx"; + }; + + xlnx_dp_snd_pcm1: dp_snd_pcm1 { + compatible = "xlnx,dp-snd-pcm"; + dmas = <&xlnx_dpdma 5>; + dma-names = "tx"; + }; diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt new file mode 100644 index 000000000000..39cb6ff762c2 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt @@ -0,0 +1,123 @@ +The Xilinx framebuffer DMA engine supports two soft IP blocks: one IP +block is used for reading video frame data from memory (FB Read) to the device +and the other IP block is used for writing video frame data from the device +to memory (FB Write). Both the FB Read/Write IP blocks are aware of the +format of the data being written to or read from memory including RGB and +YUV in packed, planar, and semi-planar formats. Because the FB Read/Write +is format aware, only one buffer pointer is needed by the IP blocks even +when planar or semi-planar format are used. + +FB Read Required propertie(s): +- compatible : Should be "xlnx,axi-frmbuf-rd-v2.1". Older string + "xlnx,axi-frmbuf-rd-v2" is now deprecated. + +Note: Compatible string "xlnx,axi-frmbuf-rd" and the hardware it +represented is no longer supported. + +FB Write Required propertie(s): +- compatible : Should be "xlnx,axi-frmbuf-wr-v2.1". Older string + "xlnx,axi-frmbuf-wr-v2" is now deprecated. + +Note: Compatible string "xlnx,axi-frmbuf-wr" and the hardware it +represented is no longer supported. + +Required Properties Common to both FB Read and FB Write: +- #dma-cells : should be 1 +- interrupt-parent : Interrupt controller the interrupt is routed through +- interrupts : Should contain DMA channel interrupt +- reset-gpios : Should contain GPIO reset phandle +- reg : Memory map for module access +- xlnx,dma-addr-width : Size of dma address pointer in IP (either 32 or 64) +- xlnx,vid-formats : A list of strings indicating what video memory + formats the IP has been configured to support. + See VIDEO FORMATS table below and examples. + +Required Properties Common to both FB Read and FB Write for v2.1: +- xlnx,pixels-per-clock : Pixels per clock set in IP (1, 2 or 4) +- clocks: Reference to the AXI Streaming clock feeding the AP_CLK +- clock-names: Must have "ap_clk" + +Optional Properties Common to both FB Read and FB Write for v2.1: +- xlnx,dma-align : DMA alignment required in bytes. + If absent then dma alignment is calculated as + pixels per clock * 8. + If present it should be power of 2 and at least + pixels per clock * 8. + Minimum is 8, 16, 32 when pixels-per-clock is + 1, 2 or 4. +- xlnx,fid : Field ID enabled for interlaced video support. + Can be absent for progressive video. + +Optional properties: +- xlnx,max-height : Maximum number of lines. +- xlnx,max-width : Maximum number of pixels in a line. + +VIDEO FORMATS +The following table describes the legal string values to be used for +the xlnx,vid-formats property. To the left is the string value and the +two columns to the right describe how this is mapped to an equivalent V4L2 +and DRM fourcc code---respectively---by the driver. + +IP FORMAT DTS String V4L2 Fourcc DRM Fourcc +-------------|----------------|----------------------|--------------------- +RGB8 bgr888 V4L2_PIX_FMT_RGB24 DRM_FORMAT_BGR888 +BGR8 rgb888 V4L2_PIX_FMT_BGR24 DRM_FORMAT_RGB888 +RGBX8 xbgr8888 V4L2_PIX_FMT_BGRX32 DRM_FORMAT_XBGR8888 +RGBA8 abgr8888 <not supported> DRM_FORMAT_ABGR8888 +BGRA8 argb8888 <not supported> DRM_FORMAT_ARGB8888 +BGRX8 xrgb8888 V4L2_PIX_FMT_XBGR32 DRM_FORMAT_XRGB8888 +RGBX10 xbgr2101010 V4L2_PIX_FMT_XBGR30 DRM_FORMAT_XBGR2101010 +RGBX12 xbgr2121212 V4L2_PIX_FMT_XBGR40 <not supported> +RGBX16 rgb16 V4L2_PIX_FMT_BGR40 <not supported> +YUV8 vuy888 V4L2_PIX_FMT_VUY24 DRM_FORMAT_VUY888 +YUVX8 xvuy8888 V4L2_PIX_FMT_XVUY32 DRM_FORMAT_XVUY8888 +YUYV8 yuyv V4L2_PIX_FMT_YUYV DRM_FORMAT_YUYV +UYVY8 uyvy V4L2_PIX_FMT_UYVY DRM_FORMAT_UYVY +YUVA8 avuy8888 <not supported> DRM_FORMAT_AVUY +YUVX10 yuvx2101010 V4L2_PIX_FMT_XVUY10 DRM_FORMAT_XVUY2101010 +Y8 y8 V4L2_PIX_FMT_GREY DRM_FORMAT_Y8 +Y10 y10 V4L2_PIX_FMT_Y10 DRM_FORMAT_Y10 +Y_UV8 nv16 V4L2_PIX_FMT_NV16 DRM_FORMAT_NV16 +Y_UV8 nv16 V4L2_PIX_FMT_NV16M DRM_FORMAT_NV16 +Y_UV8_420 nv12 V4L2_PIX_FMT_NV12 DRM_FORMAT_NV12 +Y_UV8_420 nv12 V4L2_PIX_FMT_NV12M DRM_FORMAT_NV12 +Y_UV10 xv20 V4L2_PIX_FMT_XV20M DRM_FORMAT_XV20 +Y_UV10 xv20 V4L2_PIX_FMT_XV20 <not supported> +Y_UV10_420 xv15 V4L2_PIX_FMT_XV15M DRM_FORMAT_XV15 +Y_UV10_420 xv15 V4L2_PIX_FMT_XV20 <not supported> + +Examples: + +FB Read Example: +++++++++ +v_frmbuf_rd_0: v_frmbuf_rd@80000000 { + #dma-cells = <1>; + compatible = "xlnx,axi-frmbuf-rd-v2.1"; + interrupt-parent = <&gic>; + interrupts = <0 92 4>; + reset-gpios = <&gpio 80 1>; + reg = <0x0 0x80000000 0x0 0x10000>; + xlnx,dma-addr-width = <32>; + xlnx,vid-formats = "bgr888","xbgr8888"; + xlnx,pixels-per-clock = <1>; + xlnx,dma-align = <8>; + clocks = <&vid_stream_clk>; + clock-names = "ap_clk" +}; + +FB Write Example: +++++++++ +v_frmbuf_wr_0: v_frmbuf_wr@80000000 { + #dma-cells = <1>; + compatible = "xlnx,axi-frmbuf-wr-v2.1"; + interrupt-parent = <&gic>; + interrupts = <0 92 4>; + reset-gpios = <&gpio 80 1>; + reg = <0x0 0x80000000 0x0 0x10000>; + xlnx,dma-addr-width = <64>; + xlnx,vid-formats = "bgr888","yuyv","nv16","nv12"; + xlnx,pixels-per-clock = <2>; + xlnx,dma-align = <16>; + clocks = <&vid_stream_clk>; + clock-names = "ap_clk" +}; diff --git a/Documentation/devicetree/bindings/drm/xilinx/cresample.txt b/Documentation/devicetree/bindings/drm/xilinx/cresample.txt new file mode 100644 index 000000000000..177ab58bfc9d --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xilinx/cresample.txt @@ -0,0 +1,22 @@ +Device-Tree bindings for Xilinx Chroma Resampler(CRESAMPLE) + +Xilinx CRESAMPLE provides the chroma resampling of YUV formats. + +Required properties: + - compatible: value should be "xlnx,v-cresample-3.01.a" + - reg: base address and size of the CRESAMPLE IP + - xlnx,input-format, xlnx,output-format: the input/output video formats of + CRESAMPLE. The value should be one of following format strings. + + yuv422 + yuv444 + yuv420 + +Example: + + v_cresample_0: v-cresample@40020000 { + compatible = "xlnx,v-cresample-3.01.a"; + reg = <0x40020000 0x10000>; + xlnx,input-format = "yuv444"; + xlnx,output-format = "yuv422"; + }; diff --git a/Documentation/devicetree/bindings/drm/xilinx/dp.txt b/Documentation/devicetree/bindings/drm/xilinx/dp.txt new file mode 100644 index 000000000000..09485a46d78b --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xilinx/dp.txt @@ -0,0 +1,65 @@ +Device-Tree bindings for Xilinx DisplayPort IP core + +The IP core supports transmission of video data in DisplayPort protocol. + +Required properties: + - compatible: Should be "xlnx,v-dp". + - reg: Base address and size of the IP core. + - interrupts: Interrupt number. + - interrupts-parent: phandle for interrupt controller. + - clocks: phandle for aclk and audio clock + - clock-names: The identification string, "aclk", is always required for + the axi clock. "aud_clk" is required only when audio needs to be enabled. + + - xlnx,dp-version: Version of DisplayPort protocol. + - xlnx,max-lanes: Maximum number of lanes of the IP core. The value should + be one of 1, 2, or 4. + - xlnx,max-link-rate: Maximum link rate of the IP core. The value should be + one of 162000, 270000, or 540000. + - xlnx,max-bpc: Maximum bits-per-color. The value should be one of 8, 10, 12, + or 16. + - xlnx,axi-clock: Clock rate of axi4-lite. This is required to provide + the correct clock divider for AUX. + + - xlnx,colormetry: Color format. The value should be one of "rgb", "ycrcb422", + "ycrcb444", or "yonly". These are based on the DisplayPort specification. + - xlnx,bpc: bits-per-color value to be configured. The value should be one of + 6, 8, 10, 12, or 16. + +Optional properties: + - xlnx,enable-yonly: Enable yonly colormetry. + - xlnx,enable-ycrcb: Enable ycrcb colormetry. + - xlnx,enable-sync: Enable synchronous operation with video clock. + - xlnx,max-pclock-frequency: Maximum pixel clock rate(KHz). The value should + specify the maximum pixel clock rate in KHz that the IP core supports. + - xlnx,dp-sub: A phandle referencing the ZynqMP DisplayPort subsystem + which contains additional blocks such as buffer managers, blender, and audio. + - phy-names: Names for each phy lane. The name should be 'dp-phy' with lane + number. For example, 'dp-phy0', 'dp-phy1'. 'dp-phy0' should be the primary + lane, and used for PLL lock. + - phys: The phy phandles for each lane. This should follow the phy-zynqmp + definition in Documentation/devicetree/bindings/phy/phy-zynqmp.txt + +Example: + + xlnx_dp: dp@83c10000 { + compatible = "xlnx,v-dp"; + reg = <0x83c10000 0x10000>; + interrupts = <0 57 4>; + interrupt-parent = <&ps7_scugic_0>; + clocks = <&dp_aclk>, <&dp_aud_clk>; + clock-names = "aclk", "aud_clk"; + + xlnx,dp-version = "v1.2"; + xlnx,max-lanes = <4>; + xlnx,max-link-rate = <270000>; + xlnx,max-bpc = <16>; + xlnx,max-pclock-frequency = <150000>; + xlnx,enable-ycrcb; + + xlnx,colormetry = "rgb"; + xlnx,bpc = <8>; + + phy-names = "dp-phy0", "dp-phy1"; + phys = <&lane1 PHY_TYPE_DP 0 3 27000000>, <&lane0 PHY_TYPE_DP 1 3 27000000>; + }; diff --git a/Documentation/devicetree/bindings/drm/xilinx/dp_sub.txt b/Documentation/devicetree/bindings/drm/xilinx/dp_sub.txt new file mode 100644 index 000000000000..678235355caa --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xilinx/dp_sub.txt @@ -0,0 +1,65 @@ +Device-Tree bindings for Xilinx ZynqMP DisplayPort Subsystem + +The ZynqMP DisplayPort subsystem handles DMA channel buffer management, +blending, and audio mixing. The DisplayPort subsystem receives display +and audio frames from DPDMA and transmits output to the DisplayPort IP core. + +Required properties: + - compatible: Should be one of "xlnx,dp-sub". + - reg: Base address and size of the IP core. + - reg-names: "blend", "av_buf", and "aud" for Blender, AV Buffer manager, and + Audio modules respectively. + - xlnx,output-fmt: Output color format. The value should be one of "rgb", + "ycrcb422", "ycrcb444", or "yonly". These are based on the DisplayPort + specification. The value shall be synced with DP colormetry.. + +Optional properties: + - xlnx,vid-fmt: Video input color format. The value should be one of + "vyuy" + "uyvy" + "yuyv" + "yvyu" + "yuv422" + "yvu422" + "yuv444" + "yvu444" + "nv16" + "nv61 + "bgr888" + "rgb888" + "xbgr8888" + "xrgb8888" + "xbgr2101010" + "xrgb2101010" + "yuv420" + "yvu420" + "nv12" + "nv21". + If nothing is specified, "vyuy" will be selected. + - xlnx,gfx-fmt: Graphics input color format. The value should be one of + "abgr8888" + "argb8888" + "rgba8888" + "bgra8888" + "bgr888" + "rgb888" + "rgba5551" + "bgra5551" + "rgba4444" + "bgra4444" + "rgb565" + "bgr565". + If nothing is specified, "abgr8888" will be selected. + +Optional properties: + - xlnx,vid-clk-pl: Should be used when the pixel clock is coming from PL. + +Example: + + xlnx_dp_sub: dp_sub@43c0a000 { + compatible = "xlnx,dp-sub"; + reg = <0x43c0a000 0x1000>, <0x43c0b000 0x1000>, + <0x43c0c000 0x1000>; + reg-names = "blend", "av_buf", "aud"; + xlnx,output-fmt = "rgb"; + }; diff --git a/Documentation/devicetree/bindings/drm/xilinx/dsi.txt b/Documentation/devicetree/bindings/drm/xilinx/dsi.txt new file mode 100644 index 000000000000..f56db6a0d95b --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xilinx/dsi.txt @@ -0,0 +1,61 @@ +Device-Tree bindings for Xilinx MIPI DSI Tx IP core + +The IP core supports transmission of video data in MIPI DSI protocol. + +Required properties: + - compatible: Should be "xlnx,mipi-dsi-tx-subsystem". + - reg: Base address and size of the IP core. + - xlnx,dsi-datatype: Color format. The value should be one of "MIPI_DSI_FMT_RGB888", + "MIPI_DSI_FMT_RGB666", "MIPI_DSI_FMT_RGB666_PACKED" or "MIPI_DSI_FMT_RGB565". + - simple_panel: The subnode for connected panel. This represents the + DSI peripheral connected to the DSI host node. please refer to + Documentation/devicetree/bindings/display/mipi-dsi-bus.txt. The + simple-panel driver has auo,b101uan01 panel timing parameters added along + with other existing panels. DSI driver derive the required Tx IP controller + timing values from the panel timing parameters. Refer to the + xilinx_dsi_mode_set() in the DSI driver on how to derive the DSI + Tx controller timing paramters. + - ports: Connects to the drm device node through device graph binding. + The port should contain a 'remote-endpoint' subnode that points to the + endpoint in the port of the drm device node. Refer to + Documentation/devicetree/bindings/graph.txt. + - xlnx,dsi-num-lanes: Possible number of DSI lanes for the Tx controller. + The values should be 1, 2, 3 or 4. Based on xlnx,dsi-num-lanes and + line rate for the MIPI D-PHY core in Mbps, the AXI4-stream received by + Xilinx MIPI DSI Tx IP core adds markers as per DSI protocol and the packet + thus framed is convered to serial data by MIPI D-PHY core. Please refer + Xilinx pg238 for more details. This value should be equal to the number + of lanes supported by the connected DSI panel. Panel has to support this + value or has to be programmed to the same value that DSI Tx controller is + configured to. + +Required simple_panel properties: + - compatible: Value should be one of the panel name mentioned in the + of_match_table of simple panel driver drivers/gpu/drm/panel/panel-simple.c + e.g. "auo,b101uan01". + +Example: + +#include <dt-bindings/drm/mipi-dsi.h> + mipi_dsi_tx_subsystem_0: mipi_dsi_tx_subsystem@80000000 { + compatible = "xlnx,mipi-dsi-tx-subsystem"; + reg = <0x0 0x80000000 0x0 0x10000>; + xlnx,dsi-num-lanes = <4>; + xlnx,dsi-data-type = <MIPI_DSI_FMT_RGB888>; + #address-cells = <1>; + #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + mipi_port: endpoint { + remote-endpoint = <&drm_port>; + }; + }; + }; + simple_panel: simple-panel@0 { + compatible = "auo,b101uan01"; + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/drm/xilinx/osd.txt b/Documentation/devicetree/bindings/drm/xilinx/osd.txt new file mode 100644 index 000000000000..9f30706af15d --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xilinx/osd.txt @@ -0,0 +1,19 @@ +Device-Tree bindings for Xilinx Video On Screen Display(OSD) + +Xilinx OSD provides the multiplane support. Some properties can be configured +in IP synthesis. + +Required properties: + - compatible: value should be "xlnx,v-osd-5.01.a" + - reg: base address and size of the OSD IP + - xlnx,num-layers: the number of layers(up to 8) supported by OSD + - xlnx,screen-width: the maximum size(up to 4096) of screen pixel width by OSD + +Example: + + v_osd_0: v-osd@40040000 { + compatible = "xlnx,v-osd-5.01.a"; + reg = <0x40040000 0x10000>; + xlnx,num-layers = <2>; + xlnx,screen-width = <1920>; + }; diff --git a/Documentation/devicetree/bindings/drm/xilinx/rgb2ycrcb.txt b/Documentation/devicetree/bindings/drm/xilinx/rgb2ycrcb.txt new file mode 100644 index 000000000000..6d801d0426d0 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xilinx/rgb2ycrcb.txt @@ -0,0 +1,14 @@ +Device-Tree bindings for Xilinx RGB to YCrCb convertor(RGB2YCRCB) + +Xilinx RGB2YCRCB converts the pixel format from RGB to YCrCb + +Required properties: + - compatible: value should be "xlnx,v-rgb2ycrcb-6.01.a" + - reg: base address and size of the RGB2YCRCB IP + +Example: + + v_rgb2ycrcb_0: v-rgb2ycrcb@40030000 { + compatible = "xlnx,v-rgb2ycrcb-6.01.a"; + reg = <0x40030000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/drm/xilinx/sdi.txt b/Documentation/devicetree/bindings/drm/xilinx/sdi.txt new file mode 100644 index 000000000000..ceb5340364bb --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xilinx/sdi.txt @@ -0,0 +1,34 @@ +Device-Tree bindings for Xilinx SDI Tx IP core + +The IP core supports transmission of video data in SDI Tx: protocol. + +Required properties: + - compatible: Should be "xlnx,v-smpte-uhdsdi-tx-ss". + - interrupts: Interrupt number. + - interrupts-parent: phandle for interrupt controller. + - reg: Base address and size of the IP core. + - ports: Connects to the drm device node through device graph binding. + The port should contain a 'remote-endpoint' subnode that points to the + endpoint in the port of the drm device node. Refer to + Documentation/devicetree/bindings/graph.txt. + - xlnx,vtc: vtc phandle + +Example: + + v_smpte_uhdsdi_tx_ss: v_smpte_uhdsdi_tx_ss@80020000 { + compatible = "xlnx,v-smpte-uhdsdi-tx-ss"; + interrupt-parent = <&gic>; + interrupts = <0 90 4>; + reg = <0x0 0x80020000 0x0 0x10000>; + xlnx,vtc = <&v_tc_0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + sdi_port: endpoint { + remote-endpoint = <&drm_port>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/drm/xilinx/vtc.txt b/Documentation/devicetree/bindings/drm/xilinx/vtc.txt new file mode 100644 index 000000000000..13309048e789 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xilinx/vtc.txt @@ -0,0 +1,18 @@ +Device-Tree bindings for Xilinx Video Timing Controller(VTC) + +Xilinx VTC provides the timings for Video IPs. + +Required properties: + - compatible: value should be "xlnx,v-tc-5.01.a" + - reg: base address and size of the VTC IP + - interrupts: the interrupt number + - interrupts-parent: the phandle for interrupt controller + +Example: + + v_tc_0: v-tc@40010000 { + compatible = "xlnx,v-tc-5.01.a"; + interrupt-parent = <&intc>; + interrupts = <0 54 4>; + reg = <0x40010000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/drm/xilinx/xilinx_drm.txt b/Documentation/devicetree/bindings/drm/xilinx/xilinx_drm.txt new file mode 100644 index 000000000000..25859d47ba85 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/xilinx/xilinx_drm.txt @@ -0,0 +1,162 @@ +Device-Tree bindings for Xilinx DRM + +Xilinx DRM supports the display pipelines with Xilinx soft IPs on FPGA and +IPs on Xilinx boards. + +The example hardware pipeline is depicted below +(*IPs in parentheses() are optional. IPs in brackets[] don't require drivers). +vdma-[remap]-(rgb2yuv)-(cresample)-(osd)-(rgb2yuv)-(cresample)-[axi2vid]-adv7511 +(vdma-[remap]-(rgb2yuv)-(cresample)-|) | + si570 -> vtc + +Required properties: + - compatible: value should be "xlnx,drm". + - xlnx,osd: the phandle for on screen display IP if used in the hardware design + - xlnx,rgb2yuv: the phandle for rgb2ycrcb IP if used in the hardware design + - xlnx,cresample: the phandle for chroma resampler IP if used in the hardware + design + - xlnx,vtc: the phandle for video timing controller IP + - xlnx,encoder-slave: the phandle for the encoder slave. + - clocks: the phandle for the pixel clock + - planes: the subnode for resources for each plane + - xlnx,connector-type: the type of connector. The value should be one of + "HDMIA" or "DisplayPort" depending on which connector type to be used. + +Optional properties: + - xlnx,dp-sub: the phandle to DisplayPort subsystem node for ZynqMP. + - xlnx,sdi: the phandle to SDI node if the pipeline has the SDI IP core. + - ports: device graph binding can be used to define connectivity. The DT + bindings are defined in Documentation/devicetree/bindings/graph.txt. + +Required planes properties: + - xlnx,pixel-format: the format of plane manager. The value should be one of + following format strings. + + "yuv420" + "uvy422" + "vuy422" + "yuv422" + "yv4u22" + "yuv444" + "nv12" + "nv21" + "nv16" + "nv61" + "abgr1555" + "argb1555" + "rgba4444" + "bgra4444" + "bgr565" + "rgb565" + "bgr888" + "rgb888" + "xbgr8888" + "xrgb8888" + "abgr8888" + "argb8888" + "bgra8888" + "rgba8888" + +Required plane properties: + - dmas: the phandle list of DMA specifiers + - dma-names: the identifier strings for DMAs. + - xlnx,rgb2yuv: the phandle for rgb2ycrcb IP if used for plane + - xlnx,cresample: the phandle for chroma resampler IP if used for plane + +The pipeline can be configured as following examples or more. + - Example 1: +vdma - [remap] - rgb2yuv - cresample - [axi2vid] - adv7511 + | + si570 - vtc + xilinx_drm { + compatible = "xlnx,drm"; + xlnx,vtc = <&v_tc_0>; + xlnx,encoder-slave = <&adv7511>; + xlnx,connector-type = "HDMIA"; + clocks = <&si570>; + planes { + xlnx,pixel-format = "yuv422"; + plane0 { + dma = <&axi_vdma_0>; + dma-names = "axi_vdma_0"; + xlnx,rgb2yuv = <&v_rgb2ycrcb_0>; + xlnx,cresample = <&v_cresample_0>; + }; + }; + }; + + - Example 2: +vdma - [remap] --------- osd - cresample - [axi2vid] - adv7511 +vdma - [remap] - rgb2yuv -| | + si570 - vtc + + xilinx_drm { + compatible = "xlnx,drm"; + xlnx,osd = <&v_osd_0>; + xlnx,cresample = <&v_cresample_0>; + xlnx,vtc = <&v_tc_0>; + xlnx,encoder-slave = <&adv7511>; + xlnx,connector-type = "DisplayPort"; + clocks = <&si570>; + planes { + xlnx,pixel-format = "yuv422"; + plane0 { + dma = <&axi_vdma_0>; + dma-names = "axi_vdma_0"; + }; + plane1 { + dma = <&axi_vdma_1>; + dma-names = "axi_vdma_1"; + xlnx,rgb2yuv = <&v_rgb2ycrcb_0>; + }; + }; + }; + + - Example 3: +dpdma - ZynqMP DP subsystem - DP + + xilinx_drm { + compatible = "xlnx,drm"; + xlnx,encoder-slave = <&xlnx_dp>; + clocks = <&si570 0>; + xlnx,connector-type = "DisplayPort"; + xlnx,dp-sub = <&xlnx_dp_sub>; + planes { + xlnx,pixel-format = "rgb565"; + plane0 { + dmas = <&xlnx_dpdma 3>; + dma-names = "xlnx_dpdma"; + }; + plane1 { + dmas = <&xlnx_dpdma 0>, + <&xlnx_dpdma 1>, + <&xlnx_dpdma 2>; + dma-names = "xlnx_dpdma_0", + "xlnx_dpdma_1", + "xlnx_dpdma_2"; + }; + }; + }; + +- Example 4: +vdma - Xilinx MIPI DSI + xilinx_drm: xilinx_drm { + compatible = "xlnx,drm"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + drm_port: endpoint { + remote-endpoint = <&mipi_port>; + }; + }; + }; + planes { + xlnx,pixel-format = "rgb888"; + plane0 { + dmas = <&axi_vdma_0 0>; + dma-names = "axi_vdma_0"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/drm/zocl/zocl_drm.txt b/Documentation/devicetree/bindings/drm/zocl/zocl_drm.txt new file mode 100644 index 000000000000..bb9e30af4afc --- /dev/null +++ b/Documentation/devicetree/bindings/drm/zocl/zocl_drm.txt @@ -0,0 +1,13 @@ +Binding for ZynQ OpenCL DRM driver + +Required properties: +- compatible: should contain "xlnx,zocl" +- reg: base address and size for memory mapped control port for opencl kernel + +Example: + + zocl_drm { + compatible = "xlnx,zocl"; + status = "okay"; + reg = <0x80000000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/edac/cortex-arm64-edac.txt b/Documentation/devicetree/bindings/edac/cortex-arm64-edac.txt new file mode 100644 index 000000000000..552f0c7774b1 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/cortex-arm64-edac.txt @@ -0,0 +1,15 @@ +* ARM Cortex A57 and A53 L1/L2 cache error reporting + +CPU Memory Error Syndrome and L2 Memory Error Syndrome registers can be used +for checking L1 and L2 memory errors. + +The following section describes the Cortex A57/A53 EDAC DT node binding. + +Required properties: +- compatible: Should be "arm,cortex-a57-edac" or "arm,cortex-a53-edac" + +Example: + edac { + compatible = "arm,cortex-a57-edac"; + }; + diff --git a/Documentation/devicetree/bindings/edac/pl310_edac_l2.txt b/Documentation/devicetree/bindings/edac/pl310_edac_l2.txt new file mode 100644 index 000000000000..94fbb8da2d1b --- /dev/null +++ b/Documentation/devicetree/bindings/edac/pl310_edac_l2.txt @@ -0,0 +1,19 @@ +Pl310 L2 Cache EDAC driver, it does reports the data and tag ram parity errors. + +Required properties: +- compatible: Should be "arm,pl310-cache". +- intterupts: Interrupt number to the cpu. +- reg: Physical base address and size of cache controller's memory mapped + registers + +Example: +++++++++ + + L2: cache-controller { + compatible = "arm,pl310-cache"; + interrupts = <0 2 4>; + reg = <0xf8f02000 0x1000>; + }; + +PL310 L2 Cache EDAC driver detects the Parity enable state by reading the +appropriate control register. diff --git a/Documentation/devicetree/bindings/edac/zynqmp_ocm_edac.txt b/Documentation/devicetree/bindings/edac/zynqmp_ocm_edac.txt new file mode 100644 index 000000000000..252bb96bee90 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/zynqmp_ocm_edac.txt @@ -0,0 +1,18 @@ +Xilinx ZynqMP OCM EDAC driver, it does reports the OCM ECC single bit errors +that are corrected and double bit ecc errors that are detected by the OCM +ECC controller. + +Required properties: +- compatible: Should be "xlnx,zynqmp-ocmc-1.0". +- reg: Should contain OCM controller registers location and length. +- interrupt-parent: Should be core interrupt controller. +- interrupts: Property with a value describing the interrupt number. + +Example: +++++++++ +ocm: memory-controller@ff960000 { + compatible = "xlnx,zynqmp-ocmc-1.0"; + reg = <0x0 0xff960000 0x1000>; + interrupt-parent = <&gic>; + interrupts = <0 10 4>; +}; diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt index a4fe136be2ba..56ec638f3976 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt @@ -11,7 +11,9 @@ power management service, FPGA service and other platform management services. Required properties: - - compatible: Must contain: "xlnx,zynqmp-firmware" + - compatible: Must contain any of below: + "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC + "xlnx,versal-firmware-wip" for Versal - method: The method of calling the PM-API firmware layer. Permitted values are: - "smc" : SMC #0, following the SMCCC @@ -21,6 +23,8 @@ Required properties: Example ------- +Zynq Ultrascale+ MPSoC +---------------------- firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; @@ -28,3 +32,13 @@ firmware { ... }; }; + +Versal +------ +firmware { + versal_firmware: versal-firmware { + compatible = "xlnx,versal-firmware-wip"; + method = "smc"; + ... + }; +}; diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index 90c44694a30b..f64d815ec75e 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -196,6 +196,7 @@ Optional properties: - config-complete-timeout-us : The maximum time in microseconds time for the FPGA to go to operating mode after the region has been programmed. - child nodes : devices in the FPGA after programming. +- resets : Phandle and reset specifier for this region In the example below, when an overlay is applied targeting fpga-region0, fpga_mgr is used to program the FPGA. Two bridges are controlled during diff --git a/Documentation/devicetree/bindings/fpga/xlnx,afi-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,afi-fpga.txt new file mode 100644 index 000000000000..85f8970010b9 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,afi-fpga.txt @@ -0,0 +1,61 @@ +Xilinx ZynqMp AFI interface Manager + +The Zynq UltraScale+ MPSoC Processing System core provides access from PL +masters to PS internal peripherals, and memory through AXI FIFO interface +(AFI) interfaces. + +Required properties: +-compatible: Should contain "xlnx,afi-fpga" +-config-afi: Pairs of <regid value > + +The possible values of regid and values are + regid: Regids of the register to be written possible values + 0- AFIFM0_RDCTRL + 1- AFIFM0_WRCTRL + 2- AFIFM1_RDCTRL + 3- AFIFM1_WRCTRL + 4- AFIFM2_RDCTRL + 5- AFIFM2_WRCTRL + 6- AFIFM3_RDCTRL + 7- AFIFM3_WRCTRL + 8- AFIFM4_RDCTRL + 9- AFIFM4_WRCTRL + 10- AFIFM5_RDCTRL + 11- AFIFM5_WRCTRL + 12- AFIFM6_RDCTRL + 13- AFIFM6_WRCTRL + 14- AFIFS + 15- AFIFS_SS2 +- value: Array of values to be written. + for FM0_RDCTRL(0) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM0_WRCTRL(1) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM1_RDCTRL(2) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM1_WRCTRL(3) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM2_RDCTRL(4) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM2_WRCTRL(5) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM3_RDCTRL(6) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM3_WRCTRL(7) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM4_RDCTRL(8) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM4_WRCTRL(9) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM5_RDCTRL(10) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM5_WRCTRL(11) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM6_RDCTRL(12) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for FM6_WRCTRL(13) the valid values-fabric width 2: 32-bit,1 : 64-bit ,0: 128-bit enabled + for AFI_FA(14) + dw_ss1_sel bits (11:10) + dw_ss0_sel bits (9:8) + 0x0: 32-bit AXI data width), + 0x1: 64-bit AXI data width, + 0x2: 128-bit AXI data + All other bits are 0 write ignored. + + for AFI_FA(15) selects for ss2AXI data width valid values + 0x000: 32-bit AXI data width), + 0x100: 64-bit AXI data width, + 0x200: 128-bit AXI data + +Example: +afi0: afi0 { + compatible = "xlnx,afi-fpga"; + config-afi = <0 2>, <1 1>, <2 1>; +}; diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.txt new file mode 100644 index 000000000000..acca970cd341 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.txt @@ -0,0 +1,10 @@ +Device Tree versal-fpga bindings for the Versal SOC, Controlled +using Versal SoC firmware interface. + +Required properties: +- compatible: should contain "xlnx,versal-fpga" + +Example: + versal_fpga: fpga { + compatible = "xlnx,versal-fpga"; + }; diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynq-afi-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynq-afi-fpga.txt new file mode 100644 index 000000000000..e00942cf3091 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynq-afi-fpga.txt @@ -0,0 +1,19 @@ +Xilinx Zynq AFI interface Manager + +The Zynq Processing System core provides access from PL masters to PS +internal peripherals, and memory through AXI FIFO interface +(AFI) interfaces. + +Required properties: +-compatible: Should contain "xlnx,zynq-afi-fpga" +-reg: Physical base address and size of the controller's register area. +-xlnx,afi-buswidth : Size of the afi bus width. + 0: 64-bit AXI data width, + 1: 32-bit AXI data width, + +Example: +afi0: afi0 { + compatible = "xlnx,zynq-afi-fpga"; + reg = <0xf8008000 0x1000>; + xlnx,afi-buswidth = <1>; +}; diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt index 3052bf619dd5..105943a48610 100644 --- a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt @@ -4,11 +4,15 @@ Programmable Logic (PL). The configuration uses the firmware interface. Required properties: - compatible: should contain "xlnx,zynqmp-pcap-fpga" +- clocks: phandle for clocks required operation +- clock-names: name for the clock, should be "ref_clk" Example for full FPGA configuration: fpga-region0 { compatible = "fpga-region"; + clocks = <&clkc 41>; + clock-names = "ref_clk"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <0x1>; #size-cells = <0x1>; diff --git a/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt b/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt index 08eed2335db0..516f4f50b124 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt @@ -8,11 +8,17 @@ local interrupts can be enabled on channel basis. Required properties: - compatible : Should be "xlnx,xps-gpio-1.00.a" - reg : Address and length of the register set for the device -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters (currently unused). +- #gpio-cells : Should be two or three. The first cell is the pin number, + The second cell is used to specify channel offset: + 0 - first channel + 8 - second channel + The third cell is optional and used to specify flags. Use the macros + defined in include/dt-bindings/gpio/gpio.h - gpio-controller : Marks the device node as a GPIO controller. Optional properties: +- clock-names : Should be "s_axi_aclk" +- clocks: Input clock specifier. Refer to common clock bindings. - interrupts : Interrupt mapping for GPIO IRQ. - xlnx,all-inputs : if n-th bit is setup, GPIO-n is input - xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1 @@ -23,6 +29,7 @@ Optional properties: - xlnx,dout-default-2 : as above but the second channel - xlnx,gpio2-width : as above but for the second channel - xlnx,tri-default-2 : as above but for the second channel +- xlnx,no-init : No initialisation at probe Example: @@ -30,6 +37,8 @@ gpio: gpio@40000000 { #gpio-cells = <2>; compatible = "xlnx,xps-gpio-1.00.a"; gpio-controller ; + clock-names = "s_axi_aclk"; + clocks = <&clkc 71>; interrupt-parent = <µblaze_0_intc>; interrupts = < 6 2 >; reg = < 0x40000000 0x10000 >; @@ -44,3 +53,11 @@ gpio: gpio@40000000 { xlnx,tri-default = <0xffffffff>; xlnx,tri-default-2 = <0xffffffff>; } ; + +Example to demonstrate how reset-gpios property is used in drivers: + +driver: driver@80000000 { + compatible = "xlnx,driver"; + reset-gpios = <&gpio 0 0 GPIO_ACTIVE_LOW>; /* gpio phandle, gpio pin-number, channel offset, flag state */ + reg = <0x0 0x80000000 0x0 0x10000>; +}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt b/Documentation/devicetree/bindings/gpio/gpio-zynq.txt index 4fa4eb5507cd..4806d846c0fc 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.txt @@ -6,7 +6,8 @@ Required properties: - First cell is the GPIO line number - Second cell is used to specify optional parameters (unused) -- compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0" +- compatible : Should be "xlnx,zynq-gpio-1.0" or + "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0 - clocks : Clock specifier (see clock bindings for details) - gpio-controller : Marks the device node as a GPIO controller. - interrupts : Interrupt specifier (see interrupt bindings for diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-ams.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-ams.txt new file mode 100644 index 000000000000..3d1e77014865 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/xilinx-ams.txt @@ -0,0 +1,159 @@ +Xilinx AMS device driver + +The AMS includes an ADC as well as on-chip sensors that can be used to +sample external voltages and monitor on-die operating conditions, such as +temperature and supply voltage levels. The AMS has two SYSMON blocks. +PL-SYSMON block is capable of monitoring off chip voltage and temperature. +PL-SYSMON block has DRP, JTAG and I2C interface to enable monitoring from +external master. Out of this interface currenlty only DRP is supported. +Other block PS-SYSMON is memory mapped to PS. Both of block has built-in +alarm generation logic that is used to interrupt the processor based on +condition set. + +All designs should have AMS register, but PS and PL are optional depending on +the design. The driver can work with only PS, only PL and both PS and PL +configurations. Please specify registers according to your design. DTS file +should always have AMS module property. Providing PS & PL module is optional. + +Required properties: + - compatible: Should be "xlnx,zynqmp-ams" + - reg: Should specify AMS register space + - interrupts: Interrupt number for the AMS control interface + - interrupt-names: Interrupt name, must be "ams-irq" + - clocks: Should contain a clock specifier for the device + - ranges: keep the property empty to map child address space + (for PS and/or PL) nodes 1:1 onto the parent address + space + +AMS device tree subnode: + - compatible: Should be "xlnx,zynqmp-ams-ps" or "xlnx,zynqmp-ams-pl" + - reg: Register space for PS or PL + +Optional properties: + +Following optional property only valid for PL. + - xlnx,ext-channels: List of external channels that are connected to the + AMS PL module. + + The child nodes of this node represent the external channels which are + connected to the AMS Module. If the property is not present + no external channels will be assumed to be connected. + + Each child node represents one channel and has the following + properties: + Required properties: + * reg: Pair of pins the channel is connected to. + 0: VP/VN + 1: VUSER0 + 2: VUSER1 + 3: VUSER3 + 4: VUSER4 + 5: VAUXP[0]/VAUXN[0] + 6: VAUXP[1]/VAUXN[1] + ... + 20: VAUXP[15]/VAUXN[15] + Note each channel number should only be used at most + once. + Optional properties: + * xlnx,bipolar: If set the channel is used in bipolar + mode. + + +Example: + xilinx_ams: ams@ffa50000 { + compatible = "xlnx,zynqmp-ams"; + interrupt-parent = <&gic>; + interrupts = <0 56 4>; + interrupt-names = "ams-irq"; + clocks = <&clkc 70>; + reg = <0x0 0xffa50000 0x0 0x800>; + reg-names = "ams-base"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ams_ps: ams_ps@ffa50800 { + compatible = "xlnx,zynqmp-ams-ps"; + reg = <0x0 0xffa50800 0x0 0x400>; + }; + + ams_pl: ams_pl@ffa50c00 { + compatible = "xlnx,zynqmp-ams-pl"; + reg = <0x0 0xffa50c00 0x0 0x400>; + xlnx,ext-channels { + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + xlnx,bipolar; + }; + channel@1 { + reg = <1>; + }; + channel@8 { + reg = <8>; + xlnx,bipolar; + }; + }; + }; + }; + +AMS Channels Details: + +Sysmon Block |Channel| Details |Measurement + Number Type +--------------------------------------------------------------------------------------------------------- +AMS CTRL |0 |System PLLs voltage measurement, VCC_PSPLL. |Voltage + |1 |Battery voltage measurement, VCC_PSBATT. |Voltage + |2 |PL Internal voltage measurement, VCCINT. |Voltage + |3 |Block RAM voltage measurement, VCCBRAM. |Voltage + |4 |PL Aux voltage measurement, VCCAUX. |Voltage + |5 |Voltage measurement for six DDR I/O PLLs, VCC_PSDDR_PLL. |Voltage + |6 |VCC_PSINTFP_DDR voltage measurement. |Voltage +--------------------------------------------------------------------------------------------------------- +PS Sysmon |7 |LPD temperature measurement. |Temperature + |8 |FPD Temperature Measurment (REMOTE). |Temperature + |9 |VCC PS LPD voltage measurement (supply1). |Voltage + |10 |VCC PS FPD voltage measurement (supply2). |Voltage + |11 |PS Aux voltage reference (supply3). |Voltage + |12 |DDR I/O VCC voltage measurement. |Voltage + |13 |PS IO Bank 503 voltage measurement (supply5). |Voltage + |14 |PS IO Bank 500 voltage measurement (supply6). |Voltage + |15 |VCCO_PSIO1 voltage measurement. |Voltage + |16 |VCCO_PSIO2 voltage measurement. |Voltage + |17 |VCC_PS_GTR voltage measurement (VPS_MGTRAVCC). |Voltage + |18 |VTT_PS_GTR voltage measurement (VPS_MGTRAVTT). |Voltage + |19 |VCC_PSADC voltage measurement. |Voltage +--------------------------------------------------------------------------------------------------------- +PL Sysmon |20 |PL Temperature measurement. |Temperature + |21 |PL Internal Voltage Voltage measurement, VCCINT. |Voltage + |22 |PL Auxiliary Voltage measurement, VCCAUX. |Voltage + |23 |ADC Reference P+ Voltage measurement. |Voltage + |24 |ADC Reference N- Voltage measurement. |Voltage + |25 |PL Block RAM Voltage measurement, VCCBRAM. |Voltage + |26 |LPD Internal Voltage measurement, VCC_PSINTLP (supply4). |Voltage + |27 |FPD Internal Voltage measurement, VCC_PSINTFP (supply5). |Voltage + |28 |PS Auxiliary Voltage measurement (supply6). |Voltage + |29 |PL VCCADC Voltage measurement (vccams). |Voltage + |30 |Differencial analog input signal Voltage measurment. |Voltage + |31 |VUser0 Voltage measurement (supply7). |Voltage + |32 |VUser1 Voltage measurement (supply8). |Voltage + |33 |VUser2 Voltage measurement (supply9). |Voltage + |34 |VUser3 Voltage measurement (supply10). |Voltage + |35 |Auxiliary ch 0 Voltage measurement (VAux0). |Voltage + |36 |Auxiliary ch 1 Voltage measurement (VAux1). |Voltage + |37 |Auxiliary ch 2 Voltage measurement (VAux2). |Voltage + |38 |Auxiliary ch 3 Voltage measurement (VAux3). |Voltage + |39 |Auxiliary ch 4 Voltage measurement (VAux4). |Voltage + |40 |Auxiliary ch 5 Voltage measurement (VAux5). |Voltage + |41 |Auxiliary ch 6 Voltage measurement (VAux6). |Voltage + |42 |Auxiliary ch 7 Voltage measurement (VAux7). |Voltage + |43 |Auxiliary ch 8 Voltage measurement (VAux8). |Voltage + |44 |Auxiliary ch 9 Voltage measurement (VAux9). |Voltage + |45 |Auxiliary ch 10 Voltage measurement (VAux10). |Voltage + |46 |Auxiliary ch 11 Voltage measurement (VAux11). |Voltage + |47 |Auxiliary ch 12 Voltage measurement (VAux12). |Voltage + |48 |Auxiliary ch 13 Voltage measurement (VAux13). |Voltage + |49 |Auxiliary ch 14 Voltage measurement (VAux14). |Voltage + |50 |Auxiliary ch 15 Voltage measurement (VAux15). |Voltage +--------------------------------------------------------------------------------------------------------- diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt index e0e0755cabd8..fecb1afdd8c1 100644 --- a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt @@ -15,6 +15,8 @@ Required properties: configuration interface to interface to the XADC hardmacro. * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to interface to the XADC hardmacro. + * "xlnx,axi-sysmon-1.3": When using the axi-sysmon pcore to + interface to the sysmon hardmacro. - reg: Address and length of the register set for the device - interrupts: Interrupt for the XADC control interface. - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock, @@ -110,3 +112,20 @@ Examples: }; }; }; + + xadc@44a00000 { + compatible = "xlnx,axi-sysmon-1.3"; + interrupt-parent = <&axi_intc_0>; + interrupts = <2 2>; + clocks = <&clk_bus_0>; + reg = <0x44a00000 0x10000>; + + xlnx,channels { + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + xlnx,bipolar; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/xilinx,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/xilinx,intc.txt new file mode 100644 index 000000000000..03b39f4b1625 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/xilinx,intc.txt @@ -0,0 +1,56 @@ +Xilinx Interrupt Controller + +The controller is a soft IP core that is configured at build time for the +number of interrupts and the type of each interrupt. These details cannot +be changed at run time. + +Required properties: + +- compatible : should be "xlnx,xps-intc-1.00.a" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be a minimum of 1. + The Xilinx device trees typically use 2 but the 2nd value + is not used. +- xlnx,kind-of-intr : A 32 bit value specifying the interrupt type for each + possible interrupt (1 = edge, 0 = level). The interrupt + type typically comes in thru the device tree node of + the interrupt generating device, but in this case + the interrupt type is determined by the interrupt + controller based on how it was implemented. +- xlnx,num-intr-inputs: Specifies the number of interrupts supported + by the specific implementation of the controller (1-32). + +Optional properties: +- interrupt-parent : Specifies an interrupt controller from which it is + chained (cascaded). +- interrupts : Specifies the interrupt of the parent controller from which + it is chained. + +Example: + +axi_intc_0: interrupt-controller@41800000 { + #interrupt-cells = <2>; + compatible = "xlnx,xps-intc-1.00.a"; + interrupt-controller; + reg = <0x41800000 0x10000>; + xlnx,kind-of-intr = <0x1>; + xlnx,num-intr-inputs = <0x1>; +}; + +Chained Example: + +The interrupt is chained to hardware interrupt 61 (29 + 32) of the GIC +for Zynq. + +axi_intc_0: interrupt-controller@41800000 { + #interrupt-cells = <2>; + compatible = "xlnx,xps-intc-1.00.a"; + interrupt-controller; + interrupt-parent = <&ps7_scugic_0>; + interrupts = <0 29 4>; + reg = <0x41800000 0x10000>; + xlnx,kind-of-intr = <0x1>; + xlnx,num-intr-inputs = <0x1>; +}; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt new file mode 100644 index 000000000000..20460744b4c6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt @@ -0,0 +1,122 @@ + +Xilinx MIPI CSI2 Receiver Subsystem (CSI2RxSS) +---------------------------------------------- + +The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 traffic +from compliant camera sensors and send the output as AXI4 Stream video data +for image processing. The subsystem consists of a MIPI DPHY in slave mode +which captures the data packets. This is passed along the MIPI CSI2 IP which +extracts the packet data. This data is taken in by the Video Format Bridge +(VFB) if selected and converted into AXI4 Stream video data at selected +pixels per clock as per AXI4-Stream Video IP and System Design UG934. + +For more details, please refer to PG232 MIPI CSI-2 Receiver Subsystem v2.0 + +Required properties: + +- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0". The older strings + "xlnx,mipi-csi2-rx-subsystem-2.0" and "xlnx,mipi-csi2-rx-subsystem-3.0" are + deprecated. + +- reg: Physical base address and length of the registers set for the device. + +- xlnx,max-lanes: Maximum active lanes in the design. + +- xlnx,en-active-lanes: Enable Active lanes configuration in Protocol + Configuration Register. + +- xlnx,dphy-present: This is equivalent to whether DPHY register interface is + enabled or not. + +- xlnx,iic-present: This shows whether subsystem's IIC is present or not. This + affects the base address of the DPHY. + +- xlnx,vc: Virtual Channel, specifies virtual channel number to be filtered. + If this is 4 then all virtual channels are allowed. + +- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw design. + Packets other than this data type (except for RAW8 and User defined data + types) will be filtered out. Possible values are RAW6, RAW7, RAW8, RAW10, + RAW12, RAW14, RAW16, RAW20, RGB444, RGB555, RGB565, RGB666, RGB888 and YUV4228bit. + +- xlnx,vfb: Video Format Bridge, Denotes if Video Format Bridge is selected + so that output is as per AXI stream documented in UG934. + +- xlnx,ppc: Pixels per clock, Number of pixels to be transferred per pixel + clock. This is valid only if xlnx,vfb property is set to 1. + +- xlnx,axis-tdata-width: AXI Stream width, This denotes the AXI Stream width. + It depends on Data type chosen, Video Format Bridge enabled/disabled and + pixels per clock. If VFB is disabled then its value is either 0x20 (32 bit) + or 0x40(64 bit) width. + +- xlnx,video-format, xlnx,video-width: Video format and width, as defined in + video.txt. + +- port: Video port, using the DT bindings defined in ../video-interfaces.txt. + The CSI 2 Rx Subsystem has a two ports, one input port for connecting to + camera sensor and other is output port. + +- data-lanes: The number of data lanes through which CSI2 Rx Subsystem is + connected to the camera sensor as per video-interfaces.txt + +- clocks: List of phandles to AXI Lite, Video and 200 MHz DPHY clocks. + +- clock-names: Must contain "lite_aclk", "video_aclk" and "dphy_clk_200M" in + the same order as clocks listed in clocks property. + +Optional Properties + +- xlnx,en-vcx: When present, the max number of virtual channels can be 16 else 4. + +Example: + + csiss_1: csiss@a0020000 { + compatible = "xlnx,mipi-csi2-rx-subsystem-4.0"; + reg = <0x0 0xa0020000 0x0 0x20000>; + interrupt-parent = <&gic>; + interrupts = <0 95 4>; + + reset-gpios = <&gpio 81 1>; + xlnx,max-lanes = <0x4>; + xlnx,en-active-lanes; + xlnx,dphy-present; + xlnx,iic-present; + xlnx,vc = <0x4>; + xlnx,csi-pxl-format = "RAW8"; + xlnx,vfb; + xlnx,ppc = <0x4>; + xlnx,axis-tdata-width = <0x20>; + + clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk"; + clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + csiss_out: endpoint { + remote-endpoint = <&vcap_csiss_in>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + csiss_in: endpoint { + data-lanes = <1 2 3 4>; + /* MIPI CSI2 Camera handle */ + remote-endpoint = <&vs2016_out>; + }; + + }; + + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,mem2mem.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,mem2mem.txt new file mode 100644 index 000000000000..73af77faeb20 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,mem2mem.txt @@ -0,0 +1,25 @@ +Xilinx Video IP MEM2MEM Pipeline (XVIM2M) +---------------------------------------- + +Xilinx video IP mem2mem pipeline processes DMA transfers to achieve memory +copy from one physical memory to other. The data is copied by employing two +DMA transfers memory to device and device to memory transactions one after +the other. The DT node of the XVIM2M represents as a top level node of the +pipeline and defines mappings between DMAs. + +Required properties: + +- compatible: Must be "xlnx,mem2mem". + +- dmas, dma-names: List of two DMA specifier and identifier strings (as + defined in Documentation/devicetree/bindings/dma/dma.txt) per port. + Identifier string of one DMA channel should be "tx" and other should be + "rx". + +Example: + + video_m2m { + compatible = "xlnx,mem2mem"; + dmas = <&dma_1 0>, <&dma_2 0>; + dma-names = "tx", "rx"; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt new file mode 100644 index 000000000000..1e38b7d5c5a9 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt @@ -0,0 +1,66 @@ + +Xilinx SDI Receiver Subsystem +------------------------------ + +The Xilinx SDI Rx Subsystem is used to capture SDI Video in upto 12G mode. +It outputs the video as an AXI4 Stream video data in YUV 422 10bpc mode. +The subsystem consists of the SDI Rx IP whose SDI native output is connected +to a SDI to Native conversion Bridge. The output of the Native bridge is +connected to a Native to AXI4S Bridge which generates the AXI4 Stream of +YUV422 or YUV420 10 bpc in dual pixel per clock. + +Required properties: + +- compatible: Must contain "xlnx,v-smpte-uhdsdi-rx-ss" + +- reg: Physical base address and length of the registers set for the device. + +- interrupts: Contains the interrupt line number. + +- interrupt-parent: phandle to interrupt controller. + +- xlnx,include-edh: Whether the EDH processor is enabled in design or not. + +- xlnx,line-rate: The maximum mode supported by the design. + +- clocks: Input clock specifier. Refer to common clock bindings. + +- clock-names: List of input clocks. + Required elements: "s_axi_aclk", "sdi_rx_clk", "video_out_clk" + +- port: Video port, using the DT bindings defined in ../video-interfaces.txt. + The SDI Rx subsystem has one port configured as output port. + +- xlnx,video-format, xlnx,video-width: Video format and width, as defined in + video.txt. Please note that the video format is fixed to either YUV422 or YUV420 + and the video-width is 10. + +Example: + v_smpte_uhdsdi_rx_ss: v_smpte_uhdsdi_rx_ss@80000000 { + compatible = "xlnx,v-smpte-uhdsdi-rx-ss"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + reg = <0x0 0x80000000 0x0 0x10000>; + xlnx,include-axilite = "true"; + xlnx,include-edh = "true"; + xlnx,include-vid-over-axi = "true"; + xlnx,line-rate = "12G_SDI_8DS"; + clocks = <&clk_1>, <&si570_1>, <&clk_2>; + clock-names = "s_axi_aclk", "sdi_rx_clk", "video_out_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <10>; + + sdirx_out: endpoint { + remote-endpoint = <&vcap_sdirx_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-axi4s-switch.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-axi4s-switch.txt new file mode 100644 index 000000000000..fb5ed47d959a --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-axi4s-switch.txt @@ -0,0 +1,141 @@ +Xilinx AXI4-Stream Switch +------------------------------- + +The AXI4-Stream Switch provides configurable routing between masters and slaves. +It supports up to 16 masters/sources and 16 slaves/sinks and two routing options. +There is atleast one slave/sink port and two master/source ports. + +The two routing options available are TDEST routing and control register routing. +The TDEST based routing uses design parameters and hence there no software control. +Each port is mapped as a pad and has its own format specified. + +Control register routing introduces an AXI4-Lite interface to configure the +routing table. There is one register for each of the master interfaces to +control each of the selectors. This routing mode requires that there is +precisely only one path between master and slave. When attempting to map the +same slave interface to multiple master interfaces, only the lowest master +interface is able to access the slave interface. +Here only the slave/sink ports have formats as master/source ports will inherit +the corresponding slave ports formats. A routing table is maintained in this case. + +Please refer to PG085 AXI4-Stream Infrastructure IP Suite v2.2 for more details. + +Required properties: + + - compatible: Must be "xlnx,axis-switch-1.1". + - xlnx,routing-mode: Can be 0 (TDEST routing) or 1 (Control reg routing) + - xlnx,num-si-slots: Number of slave / input ports. Min 1 Max 16 . + - xlnx,num-mi-slots: Number of master / output ports. Min 1 Max 16. + - ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + - clocks: Reference to the AXI Streaming clock feeding the ACLK and + AXI4 Lite control interface clock when control routing is enabled. + - clock-names: Must have "aclk". + +Optional properties: + - reg: Physical base address and length of the registers set for the device. + This is required only if xlnx,routing-mode is 1. + - clocks: Reference to AXI4 Lite control interface clock when routing-mode is 1. + - clock-names: "s_axi_ctl_clk" clock for AXI4 Lite interface when routing-mode is 1. + +Example: + +For TDEST routing, from 1 slave port to 4 master ports + + axis_switch_0: axis_switch@0 { + compatible = "xlnx,axis-switch-1.1"; + xlnx,routing-mode = <0x0>; + xlnx,num-si-slots = <0x1>; + xlnx,num-mi-slots = <0x4>; + clocks = <&vid_stream_clk>; + clock-names = "aclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + switch_in0: endpoint { + remote-endpoint = <&csirxss_out>; + }; + }; + port@1 { + reg = <1>; + switch_out0: endpoint { + remote-endpoint = <&vcap_csirxss0_in>; + }; + }; + port@2 { + reg = <2>; + switch_out1: endpoint { + remote-endpoint = <&vcap_csirxss1_in>; + }; + }; + port@3 { + reg = <3>; + switch_out2: endpoint { + remote-endpoint = <&vcap_csirxss2_in>; + }; + }; + port@4 { + reg = <4>; + switch_out3: endpoint { + remote-endpoint = <&vcap_csirxss3_in>; + }; + }; + }; + + }; + +For Control reg based routing, from 2 slave ports to 4 master ports + + axis_switch_0: axis_switch@a0050000 { + compatible = "xlnx,axis-switch-1.1"; + reg = <0x0 0xa0050000 0x0 0x1000>; + xlnx,routing-mode = <0x1>; + xlnx,num-si-slots = <0x2>; + xlnx,num-mi-slots = <0x4>; + clocks = <&vid_stream_clk>, <&misc_clk_0>; + clock-names = "aclk", "s_axi_ctl_clk; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + switch_in0: endpoint { + remote-endpoint = <&csirxss_out>; + }; + }; + port@1 { + reg = <1>; + switch_in1: endpoint { + remote-endpoint = <&tpg_out>; + }; + }; + port@2 { + reg = <2>; + switch_out0: endpoint { + remote-endpoint = <&vcap_csirxss0_in>; + }; + }; + port@3 { + reg = <3>; + switch_out1: endpoint { + remote-endpoint = <&vcap_csirxss1_in>; + }; + }; + port@4 { + reg = <4>; + switch_out2: endpoint { + remote-endpoint = <&vcap_csirxss2_in>; + }; + }; + port@5 { + reg = <5>; + switch_out3: endpoint { + remote-endpoint = <&vcap_csirxss3_in>; + }; + }; + }; + + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cfa.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cfa.txt new file mode 100644 index 000000000000..cdb0886cf975 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cfa.txt @@ -0,0 +1,58 @@ +Xilinx Color Filter Array (CFA) +------------------------------- + +Required properties: + +- compatible: Must be "xlnx,v-cfa-7.0". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the video core clock. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The cfa has an input port (0) and an output port (1). + +Required port properties: + +- xlnx,video-format: Must be SENSOR_MONO for the input port (0), and RBG for + the output port (1). + +- xlnx,video-width: Video width as defined in video.txt + +- xlnx, cfa-pattern: Must be one of "rggb", "grbg", "gbrg", and "bggr" for the + input port (0). Must not be specified for the output port (1). + +Example: + + cfa_0: cfa@400b0000 { + compatible = "xlnx,v-cfa-7.0"; + reg = <0x400b0000 0x10000>; + clocks = <&clkc 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_SENSOR_MONO>; + xlnx,video-width = <8>; + xlnx,cfa-pattern = "rggb"; + + cfa0_in: endpoint { + remote-endpoint = <&spc0_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_RBG>; + xlnx,video-width = <8>; + + cfa0_out: endpoint { + remote-endpoint = <&ccm0_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cresample.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cresample.txt new file mode 100644 index 000000000000..f404ee301272 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cresample.txt @@ -0,0 +1,54 @@ +Xilinx Chroma Resampler (CRESAMPLE) +----------------------------------- + +Required properties: + +- compatible: Must be "xlnx,v-cresample-4.0". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the video core clock. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The cresample as han input port (0) and an output port (1). + +Required port properties: + +- xlnx,video-format: Must be one of YUV_444, YUV_422 or YUV_420 for the input + port (0), and one of YUV_422 or YUV_420 for the output port (1). + +- xlnx,video-width: Video width as defined in video.txt + +Example: + + cresample_0: cresample@40120000 { + compatible = "xlnx,v-cresample-4.0"; + reg = <0x40120000 0x10000>; + clocks = <&clkc 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_YUV_444>; + xlnx,video-width = <8>; + + cresample0_in: endpoint { + remote-endpoint = <&rgb2yuv0_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + cresample0_out: endpoint { + remote-endpoint = <&scaler0_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-demosaic.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-demosaic.txt new file mode 100644 index 000000000000..9b3aff413e0e --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-demosaic.txt @@ -0,0 +1,62 @@ +Xilinx Video Demosaic IP +----------------------------- +The Xilinx Video Demosaic IP is used to interface to a Bayer video source. + +The driver set default Sink Pad media bus format to RGGB. +The IP and driver only support RGB as its Source Pad media format. + +Required properties: + +- compatible: Must be "xlnx,v-demosaic". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the AXI Streaming clock feeding the Demosaic ap_clk. + +- xlnx,max-height: Maximum number of lines. Valid range is 64 to 4320. + +- xlnx,max-width: Maximum number of pixels in a line. Valid range is 64 to 8192. + +- reset-gpios: Specifier for GPIO that asserts Demosaic IP (AP_RST_N) reset. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + +Required port properties: + +- reg: This value represents the media pad of the V4L2 sub-device. + A Sink Pad is represented by reg = <0> + A Source Pad is represented by reg = <1> + +- xlnx,video-width: Video width as defined in video.txt + +Example: + demosaic_1: demosaic@a00b0000 { + compatible = "xlnx,v-demosaic"; + reg = <0x0 0xa00b0000 0x0 0x10000>; + clocks = <&vid_stream_clk>; + reset-gpios = <&gpio 87 1>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + xlnx,video-width = <8>; + + demosaic_in: endpoint { + remote-endpoint = <&tpg_out>; + }; + }; + + port@1 { + reg = <1>; + xlnx,video-width = <8>; + + demosaic_out: endpoint { + remote-endpoint = <&gamma_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-gamma-lut.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-gamma-lut.txt new file mode 100644 index 000000000000..7bd750f009b4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-gamma-lut.txt @@ -0,0 +1,63 @@ +Xilinx Video Gamma Correction IP +----------------------------------- +The Xilinx Video Gamma Correction IP is used to provide RGB gamma correction. +The IP provides a look up table for each R,G and B components. + +Required properties: + +- compatible: Must be "xlnx,v-gamma-lut". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the clock that drives the ap_clk + signal of Video Gamma Lookup. + +- xlnx,max-height: Maximum number of lines. Valid range is 64 to 4320. + +- xlnx,max-width: Maximum number of pixels in a line. Valid range is 64 to 8192. + +- reset-gpios: Specifier for a GPIO that asserts Gamma IP (AP_RST_N) reset + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The Gamma LUT IP has an input port (0) and an output port (1). + + +Required port properties: +- reg: This value represents the media pad of the V4L2 sub-device. + A Sink Pad is represented by reg = <0> + A Source Pad is represented by reg = <1> + +- xlnx,video-width: Video width as defined in video.txt. Can be either 8 or 10. + +Example: + + gamma_lut_1: gamma_lut_1@0xa0080000 { + compatible = "xlnx,v-gamma-lut"; + reg = <0x0 0xa0080000 0x0 0x10000>; + clocks = <&vid_stream_clk>; + reset-gpios = <&gpio 83 1>; + xlnx,max-height = <2160>; + xlnx,max-width = <3840>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + xlnx,video-width = <8>; + + gamma_in: endpoint { + remote-endpoint = <&demosaic_out>; + }; + }; + + port@1 { + reg = <1>; + xlnx,video-width = <8>; + + gamma_out: endpoint { + remote-endpoint = <&csc_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-hls.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-hls.txt new file mode 100644 index 000000000000..a6db3040565a --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-hls.txt @@ -0,0 +1,64 @@ +Xilinx High-Level Synthesis Core (HLS) +-------------------------------------- + +High-Level Synthesis cores are synthesized from a high-level function +description developed by the user. As such their functions vary widely, but +they all share a set of common characteristics that allow them to be described +by common bindings. + + +Required properties: + +- compatible: This property must contain "xlnx,v-hls" to indicate that the + core is compatible with the generic Xilinx HLS DT bindings. It can also + contain a more specific string to identify the HLS core implementation. The + value of those implementation-specific strings is out of scope for these DT + bindings. + +- reg: Physical base address and length of the registers sets for the device. + The HLS core has two registers sets, the first one contains the core + standard registers and the second one contains the custom user registers. + +- clocks: Reference to the video core clock. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The HLS core has one input port (0) and one output port (1). + +Required port properties: + +- xlnx,video-format: Video format as defined in video.txt. +- xlnx,video-width: Video width as defined in video.txt. + +Example: + + hls_0: hls@43c00000 { + compatible = "xlnx,v-hls-sobel", "xlnx,v-hls"; + reg = <0x43c00000 0x24>, <0x43c00024 0xa0>; + clocks = <&clkc 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + hls0_in: endpoint { + remote-endpoint = <&vdma_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + hls0_out: endpoint { + remote-endpoint = <&vdma_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-multi-scaler.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-multi-scaler.txt new file mode 100644 index 000000000000..3aea1f36a6ce --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-multi-scaler.txt @@ -0,0 +1,95 @@ +Xilinx mem2mem Multi Video Scaler (XM2MSC) +----------------------------------------- + +Required propertie(s): +- compatible : Should be "xlnx,v-multi-scaler-v1.0" +- clocks : Input clock specifier. Refer to common clk bindings. +- interrupt-parent : Interrupt controller the interrupt is routed through +- interrupts : Should contain MultiScaler interrupt +- reset-gpios : Should contain GPIO reset phandle +- reg : Physical base address and + length of the registers set for the device. +- xlnx,max-chan : Maximum number of supported scaling channels (1 - 8) +- xlnx,max-width : Maximum number of supported column/width (64 - 3840) +- xlnx,max-height : Maximum number of supported row/height (64 - 2160) +- xlnx,dma-addr-width : dma address width (either 32 or 64) +- xlnx,pixels-per-clock : pixels per clock set in IP (1, 2 or 4) +- xlnx,vid-formats : A list of strings indicating what video memory + formats the IP has been configured to support. + See VIDEO FORMATS table below and examples. +- xlnx,num-taps : The number of filter taps for scaling (6, 8, 10, 12) + +VIDEO FORMATS +The following table describes the legal string values to be used for +the xlnx,vid-formats property. To the left is the string value and the +column to the right describes the format. + +IP FORMAT DTS String Description +-------------|----------------|--------------------- +RGB8 bgr888 Packed RGB, 8 bits per component. + Every RGB pixel in memory is represented with + 24 bits. +RGBX8 xbgr8888 Packed RGB, 8 bits per component. Every RGB + pixel in memory is represented with 32 bits. + Bits[31:24] do not contain pixel information. +BGRX8 xrgb8888 Packed BGR, 8 bits per component. Every BGR + pixel in memory is represented with 32 bits. + Bits[31:24] do not contain pixel information. +RGBX10 xbgr2101010 Packed RGB, 10 bits per component. Every RGB + pixel is represented with 32 bits. Bits[31:30] + do not contain any pixel information. +YUV8 vuy888 Packed YUV 4:4:4, 8 bits per component. Every + YUV 4:4:4 pixel in memory is represented with + 24 bits. +YUVX8 xvuy8888 Packed YUV 4:4:4, 8 bits per component. + Every YUV 4:4:4 pixel in memory is represented + with 32 bits. Bits[31:24] do not contain pixel + information. +YUYV8 yuyv Packed YUV 4:2:2, 8 bits per component. Every + two YUV 4:2:2 pixels in memory are represented + with 32 bits. +UYVY8 uyvy Packed YUV 4:2:2, 8 bits per component. + Every two YUV 4:2:2 pixels in memory are + represented with 32 bits. +YUVX10 yuvx2101010 Packed YUV 4:4:4, 10 bits per component. + Every YUV 4:4:4 pixel is represented with 32 bits. + Bits[31:30] do not contain any pixel information. +Y8 y8 Packed Luma-Only, 8 bits per component. Every + luma-only pixel in memory is represented with + 8 bits. Y8 is presented as YUV 4:4:4 on the + AXI4-Stream interface. +Y10 y10 Packed Luma-Only, 10 bits per component. Every + three luma-only pixels in memory is represented + with 32 bits. Y10 is presented as YUV 4:4:4 on + the AXI4-Stream interface. +Y_UV8 nv16 Semi-planar YUV 4:2:2 with 8 bits per component. + Y and UV stored in separate planes. +Y_UV8_420 nv12 Semi-planar YUV 4:2:0 with 8 bits per component. + Y and UV stored in separate planes. +Y_UV10 xv20 Semi-planar YUV 4:2:2 with 10 bits per component. + Every 3 pixels is represented with 32 bits. + Bits[31:30] do not contain any pixel information. + Y and UV stored in separate planes. +Y_UV10_420 xv15 Semi-planar YUV 4:2:0 with 10 bits per component. + Every 3 pixels is represented with 32 bits. + Bits[31:30] do not contain any pixel information. + Y and UV stored in separate planes. + +Example + +v_multi_scaler_0: v_multi_scaler@a0000000 {\ + clocks = <&clk 71>; + compatible = "xlnx,v-multi-scaler-v1.0"; + interrupt-names = "interrupt"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + reg = <0x0 0xa0000000 0x0 0x10000>; + xlnx,vid-formats = "bgr888","vuy888"; + reset-gpios = <&gpio 78 1>; + xlnx,max-chan = <0x01>; + xlnx,dma-addr-width = <0x20>; + xlnx,pixels-per-clock = /bits/ 8 <2>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + xlnx,num-taps = <6>; +}; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-remapper.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-remapper.txt new file mode 100644 index 000000000000..cda02cb97a21 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-remapper.txt @@ -0,0 +1,61 @@ +Xilinx Video Remapper +--------------------- + +The IP core remaps input pixel components to produce an output pixel with +less, more or the same number of components as the input pixel. + +Required properties: + +- compatible: Must be "xlnx,v-remapper". + +- clocks: Reference to the video core clock. + +- xlnx,video-width: Video pixel component width, as defined in video.txt. + +- #xlnx,s-components: Number of components per pixel at the input port + (between 1 and 4 inclusive). + +- #xlnx,m-components: Number of components per pixel at the output port + (between 1 and 4 inclusive). + +- xlnx,component-maps: Remapping configuration represented as an array of + integers. The array contains one entry per output component, in the low to + high order. Each entry corresponds to the zero-based position of the + corresponding input component, or the value 4 to drive a constant value on + the output component. For example, to remap RGB to BGR use <2 1 0>, and to + remap RBG to xRGB use <1 0 2 4>. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The remapper as an input port (0) and and output port (1). + +Example: RBG to xRGB remapper + + remapper_0: remapper { + compatible = "xlnx,v-remapper"; + + clocks = <&clkc 15>; + + xlnx,video-width = <8>; + + #xlnx,s-components = <3>; + #xlnx,m-components = <4>; + xlnx,component-maps = <1 0 2 4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + remap0_in: endpoint { + remote-endpoint = <&tpg0_out>; + }; + }; + port@1 { + reg = <1>; + remap0_out: endpoint { + remote-endpoint = <&sobel0_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-rgb2yuv.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-rgb2yuv.txt new file mode 100644 index 000000000000..ecd10fb31ac1 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-rgb2yuv.txt @@ -0,0 +1,54 @@ +Xilinx RGB to YUV (RGB2YUV) +--------------------------- + +Required properties: + +- compatible: Must be "xlnx,v-rgb2yuv-7.1". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the video core clock. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The rgb2yuv has an input port (0) and an output port (1). + +Required port properties: + +- xlnx,video-format: Must be RBG for the input port (0) and YUV_444 for the + output port (1). + +- xlnx,video-width: Video width as defined in video.txt + +Example: + + rgb2yuv_0: rgb2yuv@40100000 { + compatible = "xlnx,v-rgb2yuv-7.1"; + reg = <0x40100000 0x10000>; + clocks = <&clkc 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_RBG>; + xlnx,video-width = <8>; + + rgb2yuv0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_444>; + xlnx,video-width = <8>; + + rgb2yuv0_out: endpoint { + remote-endpoint = <&cresample0_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scaler.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scaler.txt new file mode 100644 index 000000000000..0bb9c405f5ae --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scaler.txt @@ -0,0 +1,75 @@ +Xilinx Scaler (SCALER) +------------------------------------ + +Required properties: + +- compatible: Must be "xlnx,v-scaler-8.1". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the video core clock. + +- xlnx,num-hori-taps, xlnx,num-vert-taps: The number of horizontal and vertical + taps for scaling filter(range: 2 - 12). + +- xlnx,max-num-phases: The maximum number of phases for scaling filter + (range: 2 - 64). + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The scaler has an input port (0) and an output port (1). + +Optional properties: + +- xlnx,separate-yc-coef: When set, this boolean property specifies that + the hardware uses separate coefficients for the luma and chroma filters. + Otherwise a single set of coefficients is shared for both. + +- xlnx,separate-hv-coef: When set, this boolean property specifies that + the hardware uses separate coefficients for the horizontal and vertical + filters. Otherwise a single set of coefficients is shared for both. + +Required port properties: + +- xlnx,video-format: Must be one of RBG, YUV_422, YUV_422 or YUV_420 for + both input port (0) and output port (1). The two formats must be identical. + +- xlnx,video-width: Video width as defined in video.txt + +Example: + + scaler_0: scaler@43c30000 { + compatible = "xlnx,v-scaler-8.1"; + reg = <0x43c30000 0x10000>; + clocks = <&clkc 15>; + + xlnx,num-hori-taps = <12>; + xlnx,num-vert-taps = <12>; + xlnx,max-num-phases = <4>; + xlnx,separate-hv-coef; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + scaler0_in: endpoint { + remote-endpoint = <&cresample0_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + scaler0_out: endpoint { + remote-endpoint = <&vcap0_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scd.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scd.txt new file mode 100644 index 000000000000..a05e9712c833 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scd.txt @@ -0,0 +1,164 @@ +Xilinx Scene Change Detection IP (SCD) +-------------------------------------- + +The Xilinx Scene Change Detection IP contains two blocks: one IP block is used +for reading video frame data from memory to the device and the other IP block +is used for determining whether there is a scene change between current and the +previous frame. The IP supports YUV planar and semi-planar formats. IP only +needs luma frame to determine the scene change event. The IP supports memory +based model, which means that it will accept a dma buffer address and perform +MEM2DEV transfer followed by statistical based image processing and give the +data back to application if scene change detection is present or not. + +Another version of scene change detection IP which supports streaming model, +which means that IP can be inserted in a capture pipeline. For example, +"hdmirx -> streaming-scd -> fb_wr" is a typical capture pipeline where +streaming SCD can be embedded. The IP accespts the AXI video data and perform +histogram based statistical analysis to detect scene change. The IP supports +single channel. + +Required properties: + +- compatible: Should be "xlnx,v-scd" + +- reg: Physical base address and length of the registers set for the device + +- clocks: Reference to the video core clock. + +- reset-gpios: Specifier for a GPIO that assert SCD (AP_RST_N) reset. + +- xlnx,memory-based: This is to differentiate between memory based and + streaming based IP. The value is 1 for memory based and 0 for streaming + based IPs. + +- xlnx,numstreams: Maximum active streams IP can support is 8 and this is based + on the design. + +- xlnx,addrwidth: Size of dma address pointer in IP (either 32 or 64) + +- subdev: Each channel will have its own subdev node. Each subdev will have its + sink port. + +- port: Video port, using the DT bindings defined in ../video-interfaces.txt. + +Example: + +1. Memory based device tree + +The following example shows how the device tree would look like for a memory +based design where 8 streams are enabled. + + scd: scenechange@a0100000 { + compatible = "xlnx,v-scd"; + reg = <0x0 0xa0100000 0x0 0x1fff>; + clocks = <&misc_clk_0>; + interrupt-parent = <&gic>; + interrupts = <0 90 4>; + reset-gpios = <&gpio 94 1>; + + xlnx,memory-based; + xlnx,numstreams = <8>; + xlnx,addrwidth = <0x20>; + + #address-cells = <1>; + #size-cells = <0>; + #dma-cells = <1>; + + subdev@0 { + port@0 { + reg = <0>; + scd_in0: endpoint { + remote-endpoint = <&vcap0_out0>; + }; + }; + }; + subdev@1 { + port@0 { + reg = <0>; + scd_in1: endpoint { + remote-endpoint = <&vcap0_out1>; + }; + }; + }; + subdev@2 { + port@0 { + reg = <0>; + scd_in2: endpoint { + remote-endpoint = <&vcap0_out2>; + }; + }; + }; + subdev@3 { + port@0 { + reg = <0>; + scd_in3: endpoint { + remote-endpoint = <&vcap0_out3>; + }; + }; + }; + subdev@4 { + port@0 { + reg = <0>; + scd_in4: endpoint { + remote-endpoint = <&vcap0_out4>; + }; + }; + }; + subdev@5 { + port@0 { + reg = <0>; + scd_in5: endpoint { + remote-endpoint = <&vcap0_out5>; + }; + }; + }; + subdev@6 { + port@0 { + reg = <0>; + scd_in6: endpoint { + remote-endpoint = <&vcap0_out6>; + }; + }; + }; + subdev@7 { + port@0 { + reg = <0>; + scd_in7: endpoint { + remote-endpoint = <&vcap0_out7>; + }; + }; + }; + }; + +2. Streaming based device tree + +The following example shows how the device tree would look like for a streaming +based design. + + scd: scenechange@a0280000 { + compatible = "xlnx,v-scd"; + reg = <0x0 0xa0280000 0x0 0x1fff>; + clocks = <&clk 72>; + interrupt-parent = <&gic>; + interrupts = <0 111 4>; + reset-gpios = <&gpio 100 1>; + #address-cells = <1>; + #size-cells = <0>; + xlnx,numstreams = <1>; + + scd { + port@0 { + reg = <0x0>; + scd_in0: endpoint { + remote-endpoint = <&vpss_scaler_out>; + }; + }; + + port@1 { + reg = <0x1>; + scd_out0: endpoint { + remote-endpoint = <&vcap_hdmi_in_1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-switch.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-switch.txt new file mode 100644 index 000000000000..91dc3af4a2b6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-switch.txt @@ -0,0 +1,55 @@ +Xilinx Video Switch +------------------- + +Required properties: + + - compatible: Must be "xlnx,v-switch-1.0". + + - reg: Physical base address and length of the registers set for the device. + + - clocks: Reference to the video core clock. + + - #xlnx,inputs: Number of input ports + - #xlnx,outputs: Number of outputs ports + + - ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + +Example: + + switch: switch@43c10000 { + compatible = "xlnx,v-switch-1.0"; + reg = <0x43c10000 0x10000>; + clocks = <&clkc 15>; + + #xlnx,inputs = <2>; + #xlnx,outputs = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + switch_in0: endpoint { + remote-endpoint = <&tpg_out>; + }; + }; + port@1 { + reg = <1>; + switch_in1: endpoint { + remote-endpoint = <&cresample0_out>; + }; + }; + port@2 { + reg = <2>; + switch_out0: endpoint { + remote-endpoint = <&scaler0_in>; + }; + }; + port@3 { + reg = <3>; + switch_out1: endpoint { + remote-endpoint = <&vcap0_in1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt index 439351ab2a79..4b2126a78a3f 100644 --- a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt @@ -6,7 +6,8 @@ Required properties: - compatible: Must contain at least one of "xlnx,v-tpg-5.0" (TPG version 5.0) - "xlnx,v-tpg-6.0" (TPG version 6.0) + "xlnx,v-tpg-7.0" (TPG version 7.0) + "xlnx,v-tpg-8.0" (TPG version 8.0) TPG versions backward-compatible with previous versions should list all compatible versions in the newer to older order. @@ -23,6 +24,8 @@ Required properties: Optional properties: +- xlnx,ppc: Pixels per clock. Valid values are 1, 2, 4 or 8. + - xlnx,vtc: A phandle referencing the Video Timing Controller that generates video timings for the TPG test patterns. @@ -30,16 +33,26 @@ Optional properties: input. The GPIO active level corresponds to the selection of VTC-generated video timings. +- reset-gpios: Specifier for a GPIO that assert TPG (AP_RST_N) reset. + This property is mandatory for TPG v7.0 and above. + +- xlnx,max-height: Maximum number of lines. + This property is mandatory for TPG v8.0. Value ranges from 64 to 7760. + +- xlnx,max-width: Maximum number of pixels in a line. + This property is mandatory for TPG v8.0. Value ranges from 64 to 10328. + The xlnx,vtc and timing-gpios properties are mandatory when the TPG is synthesized with two ports and forbidden when synthesized with one port. Example: tpg_0: tpg@40050000 { - compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0"; + compatible = "xlnx,v-tpg-5.0"; reg = <0x40050000 0x10000>; clocks = <&clkc 15>; + xlnx,ppc = <2>; xlnx,vtc = <&vtc_3>; timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-csc.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-csc.txt new file mode 100644 index 000000000000..b3627af85e6e --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-csc.txt @@ -0,0 +1,66 @@ +Xilinx VPSS Color Space Converter (CSC) +----------------------------------------- +The Xilinx VPSS Color Space Converter (CSC) is a Video IP that supports +color space conversion from RGB input to YUV output. + +Required properties: + +- compatible: Must be "xlnx,v-vpss-csc". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the clock that drives the ap_clk signal. + +- xlnx,max-height: Maximum number of lines. + Valid range from 64 to 4320. + +- xlnx,max-width: Maximum number of pixels in a line. + Valid range from 64 to 8192. + +- reset-gpios: Specifier for a GPIO that assert VPSS CSC (AP_RST_N) reset. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The scaler has an input port (0) and an output port (1). + +Required port properties: + +- xlnx,video-format: Must be XVIP_VF_RBG, XVIP_VF_YUV_444 or XVIP_VF_YUV_422 + for input port (0) and XVIP_VF_RBG, XVIP_VF_YUV_444 or XVIP_VF_YUV_422 + for output port (1). See <dt-bindings/media/xilinx-vip.h> for more details. + +- xlnx,video-width: Video width as defined in video.txt. Must be either 8 or 10. + +Example: + csc_1:csc@a0040000 { + compatible = "xlnx,v-vpss-csc"; + reg = <0x0 0xa0040000 0x0 0x10000>; + clocks = <&vid_stream_clk>; + reset-gpios = <&gpio 84 1>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + /* Sink Pad */ + port@0 { + reg = <0>; + xlnx,video-format = <XVIP_VF_RBG>; + xlnx,video-width = <8>; + + csc_in: endpoint { + remote-endpoint = <&gamma_out>; + }; + }; + /* Source Pad */ + port@1 { + reg = <1>; + xlnx,video-format = <XVIP_VF_RBG>; + xlnx,video-width = <8>; + + csc_out: endpoint { + remote-endpoint = <&scalar_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-scaler.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-scaler.txt new file mode 100644 index 000000000000..c29b5f487dbf --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-scaler.txt @@ -0,0 +1,93 @@ + Xilinx VPSS Scaler +------------------------ + +Required properties: + +- compatible: Must be "xlnx,v-vpss-scaler-1.0". + The older string "xlnx,v-vpss-scaler" will be deprecated. + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the AXI Streaming clock feeding the VPSS Scaler AP_CLK + and AXI4 Lite control interface clock. + +- clock-names: Must contain "aclk_axis" and "aclk_ctrl" in the same order as + clocks listed in clocks property. + +- xlnx,num-hori-taps, xlnx,num-vert-taps: The number of horizontal and vertical + taps for scaling filter(range: 2,4,6,8,10,12). + + A value of 2 represents bilinear filters. A value of 4 represents bicubic. + Values 6,8,10,12 represent polyphase filters. + +- xlnx,pix-per-clk : The pixels per clock property of the IP + +- reset-gpios: Specifier for a GPIO that assert for VPSS Scaler reset. + This property is mandatory for the Scaler + +- xlnx,max-height: Maximum number of lines. + Valid range from 64 to 4320. + +- xlnx,max-width: Maximum number of pixels in a line. + Valid range from 64 to 8192. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The scaler has an input port (0) and an output port (1). + +Required port properties: + +- xlnx,video-format: Must be one of XVIP_VF_RBG or XVIP_VF_YUV_422 for + input port (0) and must be XVIP_VF_RBG or XVIP_VF_YUV_422 or for + the output port (1). + See <dt-bindings/media/xilinx-vip.h> for more details. + +- reg: This value represents the media pad of the V4L2 sub-device. + A Sink Pad is represented by reg = <0> + A Source Pad is represented by reg = <1> + +- xlnx,video-width: Video width as defined in video.txt + +Example: + + scaler_1:scaler@a0000000 { + compatible = "xlnx,v-vpss-scaler-1.0"; + reg = <0x0 0xa0000000 0x0 0x40000>; + clocks = <&vid_stream_clk>, <&misc_clk_2>; + clock-names = "aclk_axis", "aclk_ctrl"; + xlnx,num-hori-taps = <8>; + xlnx,num-vert-taps = <8>; + xlnx,pix-per-clk = <2>; + reset-gpios = <&gpio 87 1>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + /* Sink Pad */ + reg = <0>; + + xlnx,video-format = <XVIP_VF_RBG>; + xlnx,video-width = <8>; + + scaler_in: endpoint { + remote-endpoint = <&csc_out>; + }; + }; + + port@1 { + /* Source Pad */ + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + scaler_out: endpoint { + remote-endpoint = <&vcap_tpg_in>; + }; + }; + }; + + }; diff --git a/Documentation/devicetree/bindings/misc/jesd-phy.txt b/Documentation/devicetree/bindings/misc/jesd-phy.txt new file mode 100644 index 000000000000..84535cb1e905 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/jesd-phy.txt @@ -0,0 +1,24 @@ +* Xilinx JESD204B Phy + +Description: +The LogiCORE™ IP JESD204 PHY core implements a JESD204B Physical interface supporting +line rates between 1.0 and 12.5 Gb/s on 1 to 12 lanes using GTX, GTH, or GTP transceivers. + +Required properties: +- compatible = "xlnx,jesd204-phy-2.0" +- reg = Should contain JESD204B phy registers location and length +- xlnx,pll-selection = The PLL selection 3 for QPLL and 1 For CPLL +- xlnx,lanes = No of Lanes +- xlnx,gt-refclk-freq = Reference frequency in Hz +- clocks = The phandle to the clock tree + +Example: +++++++++ + jesd204_phycores:phy@41e10000 { + compatible = "xlnx,jesd204-phy-2.0"; + reg = <0x41e10000 0x10000>; + xlnx,gt-refclk-freq = "156250000"; + xlnx,lanes = <0x1>; + xlnx,pll-selection = <0x3>; + clocks = <&si570>; + }; diff --git a/Documentation/devicetree/bindings/misc/jesd204b.txt b/Documentation/devicetree/bindings/misc/jesd204b.txt new file mode 100644 index 000000000000..53f8192c8afa --- /dev/null +++ b/Documentation/devicetree/bindings/misc/jesd204b.txt @@ -0,0 +1,28 @@ +* Xilinx JESD204B core + +Description: +The LogiCORE™ IP JESD204 core implements a JESD204B core + +Required properties: +- compatible = Should be one of + "xlnx,jesd204-5.1"; + "xlnx,jesd204-5.2"; + "xlnx,jesd204-6.1"; +- reg = Should contain JESD204B registers location and length +- xlnx,frames-per-multiframe = No of frames per multiframe +- xlnx,bytes-per-frame = No of bytes per frame +- xlnx,lanes = No of Lanes +- xlnx,subclass = subclass +- xlnx,node-is-transmit = should be present only for transmit nodes + +Example: +++++++++ +jesd_Tx_axi_0: jesd_Tx@44a20000 { + compatible = "xlnx,jesd204-5.1"; + reg = <0x44a20000 0x10000>; + xlnx,frames-per-multiframe = <30>; + xlnx,bytes-per-frame = <2>; + xlnx,subclass = <1>; + xlnx,lanes = <0x2>; + xlnx,node-is-transmit; +}; diff --git a/Documentation/devicetree/bindings/misc/xilinx-axitrafgen.txt b/Documentation/devicetree/bindings/misc/xilinx-axitrafgen.txt new file mode 100644 index 000000000000..6edb8f6a3a10 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xilinx-axitrafgen.txt @@ -0,0 +1,25 @@ +* Xilinx AXI Traffic generator IP + +Required properties: +- compatible: "xlnx,axi-traffic-gen" +- interrupts: Should contain AXI Traffic Generator interrupts. +- interrupt-parent: Must be core interrupt controller. +- reg: Should contain AXI Traffic Generator registers location and length. +- interrupt-names: Should contain both the intr names of device - error + and completion. +- xlnx,device-id: Device instance Id. + +Optional properties: +- clocks: Input clock specifier. Refer to common clock bindings. + +Example: +++++++++ +axi_traffic_gen_1: axi-traffic-gen@76000000 { + compatible = "xlnx,axi-traffic-gen-1.0", "xlnx,axi-traffic-gen"; + clocks = <&clkc 15>; + interrupts = <0 2 2 2>; + interrupt-parent = <&axi_intc_1>; + interrupt-names = "err-out", "irq-out"; + reg = <0x76000000 0x800000>; + xlnx,device-id = <0x0>; +} ; diff --git a/Documentation/devicetree/bindings/misc/xlnx,fclk.txt b/Documentation/devicetree/bindings/misc/xlnx,fclk.txt new file mode 100644 index 000000000000..e1a1acc6c5ec --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,fclk.txt @@ -0,0 +1,12 @@ +* Xilinx fclk clock enable +Temporary solution for enabling the PS_PL clocks. + +Required properties: +- compatible: "xlnx,fclk" + +Example: +++++++++ +fclk0: fclk0 { + compatible = "xlnx,fclk"; + clocks = <&clkc 71>; +}; diff --git a/Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt b/Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt new file mode 100644 index 000000000000..c1c67cbf9935 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt @@ -0,0 +1,58 @@ +* Xilinx SDFEC(16nm) IP * + +The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block +which provides high-throughput LDPC and Turbo Code implementations. +The LDPC decode & encode functionality is capable of covering a range of +customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality +principally covers codes used by LTE. The FEC Engine offers significant +power and area savings versus implementations done in the FPGA fabric. + + +Required properties: +- compatible: Must be "xlnx,sd-fec-1.1” +- clock-names : List of input clock names from the following: + - "core_clk", Main processing clock for processing core (required) + - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required) + - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional) + - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional) + - "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional) + - "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional) + - "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional) + - "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional) +- clocks : Clock phandles (see clock_bindings.txt for details). +- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers + location and length. +- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes + being used. +- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is + driven with a fixed value and is not present on the device, a value of 1 + configures the DIN_WORDS to be block based, while a value of 2 configures the + DIN_WORDS input to be supplied for each AXI transaction. +- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1 + configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width + of "4x128b". +- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is + driven with a fixed value and is not present on the device, a value of 1 + configures the DOUT_WORDS to be block based, while a value of 2 configures the + DOUT_WORDS input to be supplied for each AXI transaction. +- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1 + configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width + of "4x128b". +Optional properties: +- interrupts: should contain SDFEC interrupt number + +Example +--------------------------------------- + sd_fec_0: sd-fec@a0040000 { + compatible = "xlnx,sd-fec-1.1"; + clock-names = "core_clk", "s_axi_aclk", "s_axis_ctrl_aclk", "s_axis_din_aclk", "m_axis_status_aclk", "m_axis_dout_aclk"; + clocks = <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_1>, <&misc_clk_1>, <&misc_clk_1>; + reg = <0x0 0xa0040000 0x0 0x40000>; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + xlnx,sdfec-code = "ldpc"; + xlnx,sdfec-din-words = <0>; + xlnx,sdfec-din-width = <2>; + xlnx,sdfec-dout-words = <0>; + xlnx,sdfec-dout-width = <1>; + }; diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 1edbb049cccb..6b7cd42b8e95 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -14,6 +14,8 @@ Required Properties: - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY + - "xlnx,zynqmp-8.9a": Xilinx ZynqMP Arasan SDHCI 8.9a PHY + - "xlnx,versal-8.9a": Xilinx Versal Arasan SDHCI 8.9a PHY For this device it is strongly suggested to include arasan,soc-ctl-syscon. - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY Note: This binding has been deprecated and moved to [5]. @@ -29,7 +31,13 @@ Required Properties for "arasan,sdhci-5.1": - phys: From PHY bindings: Phandle for the Generic PHY for arasan. - phy-names: MUST be "phy_arasan". +Required Properties for "xlnx,zynqmp-8.9a" and "xlnx,versal-8.9a": + - xlnx,mio_bank: The value will be 0/1/2 depending on MIO bank selection. + - xlnx,device_id: Unique Id of the device, value will be 0/1. + Optional Properties: + - broken-mmc-highspeed: Indicates to force + the controller to use in standard speed. - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) used to access core corecfg registers. Offsets of registers in this syscon are determined based on the main compatible string for the device. @@ -44,6 +52,28 @@ Optional Properties: properly. Test mode can be used to force the controller to function. - xlnx,int-clock-stable-broken: when present, the controller always reports that the internal clock is stable even when it is not. + - pinctrl-0: pin control group to be used for this controller. + - pinctrl-names: must contain a "default" entry. + +Optional Properties for "xlnx,zynqmp-8.9a": + - nvmem-cells: list of phandle to the nvmem data cells. + - nvmem-cell-names: Names for the each nvmem-cells specified. + - xlnx,itap-delay-sd-hsd: Input Tap Delay for SD HS. + - xlnx,itap-delay-sdr25: Input Tap Delay for SDR25. + - xlnx,itap-delay-sdr50: Input Tap Delay for SDR50. + - xlnx,itap-delay-sdr104: Input Tap Delay for SDR104. + - xlnx,itap-delay-sd-ddr50: Input Tap Delay for SD DDR50. + - xlnx,itap-delay-mmc-hsd: Input Tap Delay for MMC HS. + - xlnx,itap-delay-mmc-ddr52: Input Tap Delay for MMC DDR52. + - xlnx,itap-delay-mmc-hs200: Input Tap Delay for MMC HS200. + - xlnx,otap-delay-sd-hsd: Output Tap Delay for SD HS. + - xlnx,otap-delay-sdr25: Output Tap Delay for SDR25. + - xlnx,otap-delay-sdr50: Output Tap Delay for SDR50. + - xlnx,otap-delay-sdr104: Output Tap Delay for SDR104. + - xlnx,otap-delay-sd-ddr50: Output Tap Delay for DDR50. + - xlnx,otap-delay-mmc-hsd: Output Tap Delay for MMC HS. + - xlnx,otap-delay-mmc-ddr52: Output Tap Delay for MMC DDR52. + - xlnx,otap-delay-mmc-hs200: Output Tap Delay for MMC HS200. Example: sdhci@e0100000 { diff --git a/Documentation/devicetree/bindings/mtd/arasan_nand.txt b/Documentation/devicetree/bindings/mtd/arasan_nand.txt new file mode 100644 index 000000000000..546ed98d9777 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/arasan_nand.txt @@ -0,0 +1,33 @@ +Arasan NAND Flash Controller with ONFI 3.1 support + +Required properties: +- compatible: Should be "xlnx,zynqmp-nand", "arasan,nfc-v3p10" +- reg: Memory map for module access +- interrupt-parent: Interrupt controller the interrupt is routed through +- interrupts: Should contain the interrupt for the device +- clock-name: List of input clocks - "sys", "flash" + (See clock bindings for details) +- clocks: Clock phandles (see clock bindings for details) + +Required properties for child node: +- nand-ecc-mode: see nand.txt + +For NAND partition information please refer the below file +Documentation/devicetree/bindings/mtd/partition.txt + +Example: + nfc: nand@ff100000 { + compatible = "xlnx,zynqmp-nand", "arasan,nfc-v3p10" + reg = <0x0 0xff100000 0x1000>; + clock-name = "sys", "flash" + clocks = <&misc_clk &misc_clk>; + interrupt-parent = <&gic>; + interrupts = <0 14 4>; + #address-cells = <1>; + #size-cells = <0> + + nand@0 { + reg = <0> + nand-ecc-mode = "hw"; + }; + }; diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 9c5e94482b5f..199e6f616dc4 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -35,12 +35,19 @@ Optional properties for PHY child node: up via magic packet. - phy-handle : see ethernet.txt file in the same directory +Optional properties: +- tsu-clk: Time stamp unit clock frequency used. +- rx-watermark: Set watermark value for pbuf_rxcutthru reg and enable + rx partial store and forward, only when compatible = "cdns,zynqmp-gem". + Value should be less than 0xFFF. + Examples: macb0: ethernet@fffc4000 { compatible = "cdns,at32ap7000-macb"; reg = <0xfffc4000 0x4000>; interrupts = <21>; + rx-watermark = /bits/ 16 <0x44>; phy-mode = "rmii"; local-mac-address = [3a 0e 03 04 05 06]; clock-names = "pclk", "hclk", "tx_clk"; diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt index 9ef9338aaee1..c6bfaea1336d 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83867.txt +++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt @@ -27,6 +27,10 @@ Optional property: for details. - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h for applicable values. + - ti,6-wire-mode - This denotes the fact that the board has SGMII + 6-wire mode configuration. If this + property is not present default is 4-wire + mode. See data manual for details. Note: ti,min-output-impedance and ti,max-output-impedance are mutually exclusive. When both properties are present ti,max-output-impedance diff --git a/Documentation/devicetree/bindings/net/xilinx-phy.txt b/Documentation/devicetree/bindings/net/xilinx-phy.txt new file mode 100644 index 000000000000..aeb9917497b9 --- /dev/null +++ b/Documentation/devicetree/bindings/net/xilinx-phy.txt @@ -0,0 +1,15 @@ +Xilinx PCS/PMA PHY bindings + +Required properties: + - reg - The ID number for the phy, usually a small integer + +Optional properties: + - xlnx,phy-type - Describes type 1000BaseX (set to 0x5) or + SGMII (set to 0x4) + +Example: + + ethernet-phy@9 { + reg = <9>; + xlnx,phy-type = <0x5>; + }; diff --git a/Documentation/devicetree/bindings/net/xilinx-tsn-ethernet.txt b/Documentation/devicetree/bindings/net/xilinx-tsn-ethernet.txt new file mode 100644 index 000000000000..e66b64bc10e0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/xilinx-tsn-ethernet.txt @@ -0,0 +1,54 @@ +Xilinx TSN (time sensitive networking) TEMAC axi ethernet driver (xilinx_axienet) +----------------------------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,tsn-ethernet-1.00.a". +- reg : Physical base address and size of the TSN registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupts-names : Property denotes the interrupt names. +- interrupt-parent : Must be core interrupt controller. +- phy-handle : See ethernet.txt file [1]. +- local-mac-address : See ethernet.txt file [1]. +- phy-mode : see ethernet.txt file [1]. + +Optional properties: +- xlnx,tsn : Denotes a ethernet with TSN capabilities. +- xlnx,tsn-slave : Denotes a TSN slave port. +- xlnx,txcsum : Tx checksum mode (Full, Partial and None). +- xlnx,rxcsum : Rx checksum mode (Full, Partial and None). +- xlnx,phy-type : Xilinx phy device type. See xilinx-phy.txt [2]. +- xlnx,eth-hasnobuf : Used when 1G MAC is configured in non-processor mode. +- xlnx,num-queue : Number of queue supported in current design, range is + 2 to 5 and default value is 5. +- xlnx,num-tc : Number of traffic class supported in current design, + range is 2,3 and default value is 3. It denotes + the traffic classes based on VLAN-PCP value. +- xlnx,qbv-addr : Denotes mac scheduler physical base address. +- xlnx,qbv-size : Denotes mac scheduler address space size. + +[1] Documentation/devicetree/bindings/net/ethernet.txt +[2] Documentation/devicetree/bindings/net/xilinx-phy.txt + +Example: + + tsn_emac_0: tsn_mac@80040000 { + compatible = "xlnx,tsn-ethernet-1.00.a"; + interrupt-parent = <&gic>; + interrupts = <0 104 4 0 106 4 0 91 4 0 110 4>; + interrupt-names = "interrupt_ptp_rx_1", "interrupt_ptp_tx_1", "mac_irq_1", "interrupt_ptp_timer"; + local-mac-address = [ 00 0A 35 00 01 0e ]; + phy-mode = "rgmii"; + reg = <0x0 0x80040000 0x0 0x14000>; + tsn,endpoint = <&tsn_ep>; + xlnx,tsn; + xlnx,tsn-slave; + xlnx,phy-type = <0x3>; + xlnx,eth-hasnobuf; + xlnx,num-queue = <0x2>; + xlnx,num-tc = <0x3>; + xlnx,qbv-addr = <0x80054000>; + xlnx,qbv-size = <0x2000>; + xlnx,txsum = <0>; + xlnx,rxsum = <0>; + }; diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt index 38f9ec076743..4cb9a50b7d2a 100644 --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt @@ -1,55 +1,104 @@ -XILINX AXI ETHERNET Device Tree Bindings +XILINX AXI ETHERNET driver (xilinx_axienet) -------------------------------------------------------- -Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core -provides connectivity to an external ethernet PHY supporting different -interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two -segments of memory for buffering TX and RX, as well as the capability of -offloading TX/RX checksum calculation off the processor. +This driver supports following MAC configurations- +a) AXI 1G/2.5G Ethernet Subsystem. +b) 10G/25G High Speed Ethernet Subsystem. +c) 10 Gigabit Ethernet Subsystem. +d) USXGMII Ethernet Subsystem. -Management configuration is done through the AXI interface, while payload is -sent and received through means of an AXI DMA controller. This driver -includes the DMA driver code, so this driver is incompatible with AXI DMA -driver. +Management configuration is done through the AXI4-Lite interface. +The transmit and receive data interface is via the AXI4-Stream +interface connected to DMA controller. This driver supports Xilinx +AXI DMA and MCDMA DMA IP's. Programming sequence for these DMA IP's +is included in the xilinx_axienet driver. -For more details about mdio please refer phy.txt file in the same directory. +For details about MDIO please refer phy.txt [1]. Required properties: -- compatible : Must be one of "xlnx,axi-ethernet-1.00.a", - "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a" +- compatible : Must be one of "xlnx,axi-ethernet-1.00.a" or + "xlnx,axi-ethernet-1.01.a" or "xlnx,axi-ethernet-2.01.a" + for 1G MAC, + "xlnx,ten-gig-eth-mac" for 10 Gigabit Ethernet Subsystem, + "xlnx,xxv-ethernet-1.0" for 10G/25G MAC, + "xlnx,axi-2_5-gig-ethernet-1.0" for 2.5G MAC and + "xlnx,xxv-usxgmii-ethernet-1.0" for USXGMII. - reg : Address and length of the IO space. - interrupts : Should be a list of two interrupt, TX and RX. -- phy-handle : Should point to the external phy device. - See ethernet.txt file in the same directory. -- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware +- interrupt-parent : Must be core interrupt controller. +- phy-handle : See ethernet.txt [2]. +- local-mac-address : See ethernet.txt [2]. +- phy-mode : See ethernet.txt [2]. +- axistream-connected : Should contain phandle of DMA node. +Required properties (When AxiEthernet is configured with MCDMA): +- xlnx,channel-ids : Queue Identifier associated with the MCDMA Channel. +- interrupt-names : Should contain the interrupt names. Optional properties: -- phy-mode : See ethernet.txt -- xlnx,phy-type : Deprecated, do not use, but still accepted in preference - to phy-mode. -- xlnx,txcsum : 0 or empty for disabling TX checksum offload, - 1 to enable partial TX checksum offload, - 2 to enable full TX checksum offload -- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload - -Example: - axi_ethernet_eth: ethernet@40c00000 { - compatible = "xlnx,axi-ethernet-1.00.a"; - device_type = "network"; - interrupt-parent = <µblaze_0_axi_intc>; - interrupts = <2 0>; - phy-mode = "mii"; - reg = <0x40c00000 0x40000>; - xlnx,rxcsum = <0x2>; - xlnx,rxmem = <0x800>; - xlnx,txcsum = <0x2>; - phy-handle = <&phy0>; - axi_ethernetlite_0_mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - phy0: phy@0 { - device_type = "ethernet-phy"; - reg = <1>; +- xlnx,rxmem : Max Rx Memory size. +- xlnx,txcsum : Tx checksum mode (Full, Partial and None). +- xlnx,rxcsum : Rx checksum mode (Full, Partial and None). +- xlnx,phy-type : Xilinx phy device type. See xilinx-phy.txt [3]. +- dma-coherent : Present if dma operations are coherent. +- xlnx,eth-hasnobuf : Used when 1G MAC is configured in non-processor mode. +- xlnx,rxtsfifo : Configures the axi fifo for receive timestamping. +- xlnx,eth-hasptp : Tells whether PTP is enabled in h/w or not. +- axififo-connected : Should contain the phandle of AXI stream fifo. +- clocks : Input clock specifier. Refer to common clock bindings. +- clock-names : Input clock names. Refer to IP PG for signal description. + 1G/2.5G: s_axi_lite_clk, axis_clk and ref_clk. + 10G/25G and USXGMII: s_axi_aclk, rx_core_clk and dclk. + 10 Gigabit: s_axi_aclk and dclk. + AXI DMA and MCDMA: m_axi_sg_aclk, m_axi_mm2s_aclk and + m_axi_s2mm_aclk. + +Optional properties (When AxiEthernet is configured with MCDMA): +- xlnx,num-queues : Number of queues/channels configured in h/w. +Optional properties (When USXGMII is in use): +- xlnx,usxgmii-rate : USXGMII PHY speed - can be 10, 100, 1000, 2500, + 5000 or 10000. +Optional properties for connected DMA node: +- xlnx,addrwidth : Specify the width of the DMA address space in bits. + Valid range is 32-64. Default is 32. +- xlnx,include-dre : Tells whether DMA h/w is configured with data + realignment engine(DRE) or not. + +NOTE: Time Sensitive Networking (TSN) related DT bindings are explained in [4]. + +[1] Documentation/devicetree/bindings/net/phy.txt +[2] Documentation/devicetree/bindings/net/ethernet.txt +[3] Documentation/devicetree/bindings/net/xilinx-phy.txt +[4] Documentation/devicetree/bindings/net/xilinx_tsn.txt + +Example: AXI 1G/2.5G Ethernet Subsystem + AXIDMA + + axi_eth_0_dma: dma@80040000 { + #dma-cells = <1>; + compatible = "xlnx,eth-dma"; + <snip> + }; + + axi_eth_0: ethernet@80000000 { + axistream-connected = <&axi_eth_0_dma>; + compatible = "xlnx,axi-ethernet-1.00.a"; + device_type = "network"; + interrupt-names = "interrupt"; + interrupt-parent = <&gic>; + interrupts = <0 91 4>; + phy-handle = <&phy2>; + phy-mode = "sgmii"; + reg = <0x0 0x80000000 0x0 0x40000>; + xlnx,include-dre ; + xlnx,phy-type = <0x5>; + xlnx,rxcsum = <0x0>; + xlnx,rxmem = <0x1000>; + xlnx,txcsum = <0x0>; + axi_eth_0_mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy2: phy@2 { + device_type = "ethernet-phy"; + reg = <2>; + }; }; - }; }; diff --git a/Documentation/devicetree/bindings/net/xilinx_emaclite.txt b/Documentation/devicetree/bindings/net/xilinx_emaclite.txt new file mode 100644 index 000000000000..55965d942f97 --- /dev/null +++ b/Documentation/devicetree/bindings/net/xilinx_emaclite.txt @@ -0,0 +1,34 @@ +Xilinx Axi Ethernetlite controller Device Tree Bindings +--------------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,opb-ethernetlite-1.01.a" or + "xlnx,opb-ethernetlite-1.01.b" or + "xlnx,opb-ethernetlite-1.00.a" or + "xlnx,xps-ethernetlite-2.00.a" or + "xlnx,xps-ethernetlite-2.01.a" or + "xlnx,xps-ethernetlite-3.00.a" or. +- reg : Physical base address and size of the Axi ethernetlite + registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller. +- phy-handle : See ethernet.txt file in the same directory. +- local-mac-address : See ethernet.txt file in the same directory. + +Optional properties: +- xlnx,tx-ping-pong : If present, hardware supports tx ping pong buffer. +- xlnx,rx-ping-pong : If present, hardware supports rx ping pong buffer. + +Example: + axi_ethernetlite_1: ethernet@40e00000 { + compatible = "xlnx,axi-ethernetlite-3.0", "xlnx,xps-ethernetlite-1.00.a"; + device_type = "network"; + interrupt-parent = <&axi_intc_1>; + interrupts = <1 0>; + local-mac-address = [00 0a 35 00 00 00]; + phy-handle = <&phy0>; + reg = <0x40e00000 0x10000>; + xlnx,rx-ping-pong; + xlnx,tx-ping-pong; + } diff --git a/Documentation/devicetree/bindings/net/xilinx_tsn.txt b/Documentation/devicetree/bindings/net/xilinx_tsn.txt new file mode 100644 index 000000000000..8ef9fa9f3968 --- /dev/null +++ b/Documentation/devicetree/bindings/net/xilinx_tsn.txt @@ -0,0 +1,14 @@ +Xilinx TSN (time sensitive networking) IP driver (xilinx_tsn_ip) +----------------------------------------------------------------------- + +Required properties: +- compatible : Should be one of "xlnx,tsn-endpoint-ethernet-mac-1.0", + "xlnx,tsn-endpoint-ethernet-mac-2.0" for TSN. +- reg : Physical base address and size of the TSN registers map. + +Example: + + tsn_endpoint_ip_0: tsn_endpoint_ip_0 { + compatible = "xlnx,tsn-endpoint-ethernet-mac-2.0"; + reg = <0x0 0x80040000 0x0 0x40000>; + }; diff --git a/Documentation/devicetree/bindings/net/xilinx_tsn_ep.txt b/Documentation/devicetree/bindings/net/xilinx_tsn_ep.txt new file mode 100644 index 000000000000..f42e5417d164 --- /dev/null +++ b/Documentation/devicetree/bindings/net/xilinx_tsn_ep.txt @@ -0,0 +1,35 @@ +Xilinx TSN (time sensitive networking) EndPoint Driver (xilinx_tsn_ep) +------------------------------------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,tsn-ep" +- reg : Physical base address and size of the TSN Endpoint + registers map +- interrupts : Property with a value describing the interrupt +- interrupts-names : Property denotes the interrupt names. +- interrupt-parent : Must be core interrupt controller. +- local-mac-address : See ethernet.txt [1]. + +Optional properties: +- xlnx,num-tc : Number of traffic class supported in current design, + range is 2,3 and default value is 3. It denotes + the traffic classes based on VLAN-PCP value. +- xlnx,channel-ids : Queue Identifier associated with the MCDMA Channel, range + is Tx: "1 to 2" and Rx: "2 to 5", default value is "1 to 5". +- xlnx,eth-hasnobuf : Used when 1G MAC is configured in non processor mode. + +[1] Documentation/devicetree/bindings/net/ethernet.txt + +Example: + + tsn_ep: tsn_ep@80056000 { + compatible = "xlnx,tsn-ep"; + reg = <0x0 0x80056000 0x0 0xA000>; + xlnx,num-tc = <0x3>; + interrupt-names = "tsn_ep_scheduler_irq"; + interrupt-parent = <&gic>; + interrupts = <0 111 4>; + local-mac-address = [00 0A 35 00 01 10]; + xlnx,channel-ids = "1","2","3","4","5"; + xlnx,eth-hasnobuf ; + }; diff --git a/Documentation/devicetree/bindings/net/xilinx_tsn_switch.txt b/Documentation/devicetree/bindings/net/xilinx_tsn_switch.txt new file mode 100644 index 000000000000..898e5b7b57e7 --- /dev/null +++ b/Documentation/devicetree/bindings/net/xilinx_tsn_switch.txt @@ -0,0 +1,23 @@ +Xilinx TSN (time sensitive networking) Switch Driver (xilinx_tsn_switch) +----------------------------------------------------------------------------- + +Required properties: +- compatible : Should be "xlnx,tsn-switch" +- reg : Physical base address and size of the TSN registers map. + +Optional properties: +- xlnx,num-tc : Number of traffic class supported in current design, + range is 2,3 and default value is 3. It denotes + the traffic classes based on VLAN-PCP value. +- xlnx,has-hwaddr-learning : Denotes hardware address learning support +- xlnx,has-inband-mgmt-tag : Denotes inband management support + +Example: + + epswitch: tsn_switch@80078000 { + compatible = "xlnx,tsn-switch"; + reg = <0x0 0x80078000 0x0 0x4000>; + xlnx,num-tc = <0x3>; + xlnx,has-hwaddr-learning ; + xlnx,has-inband-mgmt-tag ; + }; diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt index 4881561b3a02..be126ccf4802 100644 --- a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt +++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt @@ -25,9 +25,78 @@ firmware { #size-cells = <1>; /* Data cells */ - soc_revision: soc_revision { + soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; + /* + * efuse memory access: + * all the efuse feilds need to be read + * with the exact size specified in the node + */ + /* DNA */ + efuse_dna: efuse_dna@c { + reg = <0xc 0xc>; + }; + /* User 0 */ + efuse_usr0: efuse_usr0@20 { + reg = <0x20 0x4>; + }; + /* User 1 */ + efuse_usr1: efuse_usr1@24 { + reg = <0x24 0x4>; + }; + /* User 2 */ + efuse_usr2: efuse_usr2@28 { + reg = <0x28 0x4>; + }; + /* User 3 */ + efuse_usr3: efuse_usr3@2c { + reg = <0x2c 0x4>; + }; + /* User 4 */ + efuse_usr4: efuse_usr4@30 { + reg = <0x30 0x4>; + }; + /* User 5 */ + efuse_usr5: efuse_usr5@34 { + reg = <0x34 0x4>; + }; + /* User 6 */ + efuse_usr6: efuse_usr6@38 { + reg = <0x38 0x4>; + }; + /* User 7 */ + efuse_usr7: efuse_usr7@3c { + reg = <0x3c 0x4>; + }; + /* Misc user control bits */ + efuse_miscusr: efuse_miscusr@40 { + reg = <0x40 0x4>; + }; + /* PUF chash */ + efuse_chash: efuse_chash@50 { + reg = <0x50 0x4>; + }; + /* PUF misc */ + efuse_pufmisc: efuse_pufmisc@54 { + reg = <0x54 0x4>; + }; + /* SEC_CTRL */ + efuse_sec: efuse_sec@58 { + reg = <0x58 0x4>; + }; + /* SPK ID */ + efuse_spkid: efuse_spkid@5c { + reg = <0x5c 0x4>; + }; + /* PPK0 hash */ + efuse_ppk0hash: efuse_ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + /* PPK1 hash */ + efuse_ppk1hash: efuse_ppk1hash@d0 { + reg = <0xd0 0x30>; + }; }; }; }; @@ -44,3 +113,22 @@ For example: ... }; + +To program efuse memory, one should request specified bytes of size as below, +NOTE: Efuse bits once programmed cannot be reverted. + + - | TYPE | OFFSET | SIZE(bytes) | + - |User-0 | 0x20 | 0x4 | + - |User-1 | 0x24 | 0x4 | + - |User-2 | 0x28 | 0x4 | + - |User-3 | 0x2C | 0x4 | + - |User-4 | 0x30 | 0x4 | + - |User-5 | 0x34 | 0x4 | + - |User-6 | 0x38 | 0x4 | + - |User-7 | 0x3c | 0x4 | + - |Misc User | 0x40 | 0x4 | + - |SEC_CTRL | 0x58 | 0x4 | + - |SPK ID | 0x5C | 0x4 | + - |AES KEY | 0x60 | 0x20 | + - |PPK0 hash | 0xA0 | 0x30 | + - |PPK1 hash | 0xD0 | 0x30 | diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt index 01bf7fdf4c19..c12bcf0f8947 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt +++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt @@ -18,6 +18,7 @@ Required properties: "msi1, msi0": interrupt asserted when an MSI is received "intx": interrupt asserted when a legacy interrupt is received "misc": interrupt asserted when miscellaneous interrupt is received +- clocks: Should contain a clock specifier for the device - interrupt-map-mask and interrupt-map: standard PCI properties to define the mapping of the PCI interface to interrupt numbers. - ranges: ranges for the PCI memory regions (I/O space region is not @@ -52,6 +53,7 @@ nwl_pcie: pcie@fd0e0000 { <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + clocks = <&clkc 23> msi-parent = <&nwl_pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, diff --git a/Documentation/devicetree/bindings/pci/xilinx-xdma-pl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-xdma-pl-pcie.txt new file mode 100644 index 000000000000..92b7194a2f7f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-xdma-pl-pcie.txt @@ -0,0 +1,87 @@ +* Xilinx XDMA PL PCIe Root Port Bridge DT description + +Required properties: +- #address-cells: Address representation for root ports, set to <3> +- #size-cells: Size representation for root ports, set to <2> +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- compatible: Should contain "xlnx,xdma-host-3.00" +- reg: Should contain XDMA PCIe registers location and length +- device_type: must be "pci" +- interrupts: Should contain AXI PCIe interrupt +- interrupt-map-mask, + interrupt-map: standard PCI properties to define the mapping of the + PCI interface to interrupt numbers. +- ranges: ranges for the PCI memory regions (I/O space region is not + supported by hardware) + Please refer to the standard PCI bus binding document for a more + detailed explanation + +For MSI DECODE mode: +- interrupt-names: Must include the following entries: + "misc": interrupt asserted when legacy or error interrupt is received + "msi1, msi0": interrupt asserted when an MSI is received + +Interrupt controller child node ++++++++++++++++++++++++++++++++ +Required properties: +- interrupt-controller: identifies the node as an interrupt controller +- #address-cells: specifies the number of cells needed to encode an + address. The value must be 0. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. + +NOTE: +The core provides a single interrupt for both INTx/MSI messages. So, +created a interrupt controller node to support 'interrupt-map' DT +functionality. The driver will create an IRQ domain for this map, decode +the four INTx interrupts in ISR and route them to this domain. + + +Example: +++++++++ +MSI FIFO mode: + xdma_0: axi-pcie@a0000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "xlnx,xdma-host-3.00"; + device_type = "pci"; + interrupt-map = <0 0 0 1 &pcie_intc_0 1>, + <0 0 0 2 &pcie_intc_0 2>, + <0 0 0 3 &pcie_intc_0 3>, + <0 0 0 4 &pcie_intc_0 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + ranges = <0x02000000 0x00000000 0xB0000000 0x0 0xB0000000 0x00000000 0x01000000>, + <0x43000000 0x00000005 0x00000000 0x00000005 0x00000000 0x00000000 0x01000000>; + reg = <0x0 0xA0000000 0x0 0x10000000>; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller ; + }; + }; + +MSI DECODE mode: + xdma_0: axi-pcie@a0000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "xlnx,xdma-host-3.00"; + device_type = "pci"; + interrupt-map = <0 0 0 1 &pcie_intc_0 1>, <0 0 0 2 &pcie_intc_0 2>, <0 0 0 3 &pcie_intc_0 3>, <0 0 0 4 &pcie_intc_0 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&gic>; + interrupt-names = "misc", "msi0", "msi1"; + interrupts = <0 89 4>, <0 90 4>, <0 91 4>; + ranges = <0x02000000 0x00000000 0xB0000000 0x0 0xB0000000 0x00000000 0x01000000>, + <0x43000000 0x00000005 0x00000000 0x00000005 0x00000000 0x00000000 0x01000000>; + reg = <0x0 0xA0000000 0x0 0x10000000>; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller ; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt new file mode 100644 index 000000000000..ed080df891a4 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt @@ -0,0 +1,119 @@ +Xilinx ZynqMP PHY binding + +This binding describes a ZynqMP PHY device that is used to control ZynqMP +High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes +and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers. + +Required properties (controller (parent) node): +- compatible : Can be "xlnx,zynqmp-psgtr-v1.1" or "xlnx,zynqmp-psgtr" + "xlnx,zynqmp-psgtr-v1.1" has the lpd address mapping removed + +- reg : Address and length of register sets for each device in + "reg-names" +- reg-names : The names of the register addresses corresponding to the + registers filled in "reg": + - serdes: SERDES block register set + - siou: SIOU block register set + - lpd: Low power domain peripherals reset control + +Required nodes : A sub-node is required for each lane the controller + provides. + +Required properties (port (child) nodes): +lane0: +- #phy-cells : Should be 4 + Cell after port phandle is device type from: + - <PHY_TYPE_PCIE 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_SATA 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_USB3 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_DP 1 LANE_NUM FREQUENCY> + - <PHY_TYPE_SGMII 0 LANE_NUM FREQUENCY> +lane1: +- #phy-cells : Should be 4 + Cell after port phandle is device type from: + - <PHY_TYPE_PCIE 1 LANE_NUM FREQUENCY> + - <PHY_TYPE_SATA 1 LANE_NUM FREQUENCY> + - <PHY_TYPE_USB3 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_DP 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_SGMII 1 LANE_NUM FREQUENCY> +lane2: +- #phy-cells : Should be 4 + Cell after port phandle is device type from: + - <PHY_TYPE_PCIE 2 LANE_NUM FREQUENCY> + - <PHY_TYPE_SATA 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_USB3 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_DP 1 LANE_NUM FREQUENC> + - <PHY_TYPE_SGMII 2 LANE_NUM FREQUENCY> +lane3: +- #phy-cells : Should be 4 + Cell after port phandle is device type from: + - <PHY_TYPE_PCIE 3 LANE_NUM FREQUENCY> + - <PHY_TYPE_SATA 1 LANE_NUM FREQUENCY> + - <PHY_TYPE_USB3 1 LANE_NUM FREQUENCY > + - <PHY_TYPE_DP 0 LANE_NUM FREQUENCY> + - <PHY_TYPE_SGMII 3 LANE_NUM FREQUENCY> + +Note: LANE_NUM : This determines which lane's reference clock is shared by controller. + FREQUENCY: This the clock frequency at which controller wants to operate. + + +Example: + serdes: zynqmp_phy@fd400000 { + compatible = "xlnx,zynqmp-psgtr"; + status = "okay"; + reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>, + <0x0 0xff5e0000 0x0 0x1000>; + reg-names = "serdes", "siou", "lpd"; + + lane0: lane@0 { + #phy-cells = <4>; + }; + lane1: lane@1 { + #phy-cells = <4>; + }; + lane2: lane@2 { + #phy-cells = <4>; + }; + lane3: lane@3 { + #phy-cells = <4>; + }; + }; + +Specifying phy control of devices +================================= + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy port node and a device type. + +phys = <PHANDLE CONTROLLER_TYPE CONTROLLER_INSTANCE LANE_NUM LANE_FREQ>; + +PHANDLE = &lane0 or &lane1 or &lane2 or &lane3 +CONTROLLER_TYPE = PHY_TYPE_PCIE or PHY_TYPE_SATA or PHY_TYPE_USB + or PHY_TYPE_DP or PHY_TYPE_SGMII +CONTROLLER_INSTANCE = Depends on controller type used, can be any of + PHY_TYPE_PCIE : 0 or 1 or 2 or 3 + PHY_TYPE_SATA : 0 or 1 + PHY_TYPE_USB : 0 or 1 + PHY_TYPE_DP : 0 or 1 + PHY_TYPE_SGMII: 0 or 1 or 2 or 3 +LANE_NUM = Depends on which lane clock is used as ref clk, can be + 0 or 1 or 2 or 3 +LANE_FREQ = Frequency that controller can operate, can be any of + 19.2Mhz,20Mhz,24Mhz,26Mhz,27Mhz,28.4Mhz,40Mhz,52Mhz, + 100Mhz,108Mhz,125Mhz,135Mhz,150Mhz + +Example: + +#include <dt-bindings/phy/phy.h> + + usb@fe200000 { + ... + phys = <&lane2 PHY_TYPE_USB3 0 2 2600000>; + ... + }; + + ahci@fd0c0000 { + ... + phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; + ... + }; diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt new file mode 100644 index 000000000000..3007f6f4705d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt @@ -0,0 +1,275 @@ + Binding for Xilinx ZynqMP Pinctrl + +Required properties: +- compatible: "xlnx,zynqmp-pinctrl" + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +ZynqMP's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, slew rate, etc. + +Each configuration node can consist of multiple nodes describing the pinmux and +pinconf options. Those nodes can be pinmux nodes or pinconf nodes. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Required properties for pinmux nodes are: + - groups: A list of pinmux groups. + - function: The name of a pinmux function to activate for the specified set + of groups. + +Required properties for configuration nodes: +One of: + - pins: A list of pin names + - groups: A list of pinmux groups. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinmux subnode: + groups, function + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinconf subnode: + groups, pins, bias-disable, bias-pull-up, bias-pull-down, slew-rate + + Valid arguments for 'slew-rate' are 'SLEW_RATE_SLOW' and 'SLEW_RATE_FAST' to + select between slow and fast respectively. + + Valid values for groups are: + ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp, + ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp, + gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp, + mdio1_1_grp, mdio2_0_grp, mdio3_0_grp, + qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp, + spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp, + spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp, + spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp, + spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp, + spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp, + spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp, + spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp, + spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp, + spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp, + spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp, + spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp, + spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp, + spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp, + spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp, + spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp, + spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp, + sdio0_0_grp, sdio0_1_grp, sdio0_2_grp, + sdio0_3_grp, sdio0_4_grp, sdio0_5_grp, + sdio0_6_grp, sdio0_7_grp, sdio0_8_grp, + sdio0_9_grp, sdio0_10_grp, sdio0_11_grp, + sdio0_12_grp, sdio0_13_grp, sdio0_14_grp, + sdio0_15_grp, sdio0_16_grp, sdio0_17_grp, + sdio0_18_grp, sdio0_19_grp, sdio0_20_grp, + sdio0_21_grp, sdio0_22_grp, sdio0_23_grp, + sdio0_24_grp, sdio0_25_grp, sdio0_26_grp, + sdio0_27_grp, sdio0_28_grp, sdio0_29_grp, + sdio0_30_grp, sdio0_31_grp, sdio0_32_grp, + sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp, + sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp, + sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp, + sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, + sdio1_3_grp, sdio1_4_grp, sdio1_5_grp, + sdio1_6_grp, sdio1_7_grp, sdio1_8_grp, + sdio1_9_grp, sdio1_10_grp, sdio1_11_grp, + sdio1_12_grp, sdio1_13_grp, sdio1_14_grp, + sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp, + sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp, + sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp, + nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp, + nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp, + can0_1_grp, can0_2_grp, can0_3_grp, + can0_4_grp, can0_5_grp, can0_6_grp, + can0_7_grp, can0_8_grp, can0_9_grp, + can0_10_grp, can0_11_grp, can0_12_grp, + can0_13_grp, can0_14_grp, can0_15_grp, + can0_16_grp, can0_17_grp, can0_18_grp, + can1_0_grp, can1_1_grp, can1_2_grp, + can1_3_grp, can1_4_grp, can1_5_grp, + can1_6_grp, can1_7_grp, can1_8_grp, + can1_9_grp, can1_10_grp, can1_11_grp, + can1_12_grp, can1_13_grp, can1_14_grp, + can1_15_grp, can1_16_grp, can1_17_grp, + can1_18_grp, can1_19_grp, uart0_0_grp, + uart0_1_grp, uart0_2_grp, uart0_3_grp, + uart0_4_grp, uart0_5_grp, uart0_6_grp, + uart0_7_grp, uart0_8_grp, uart0_9_grp, + uart0_10_grp, uart0_11_grp, uart0_12_grp, + uart0_13_grp, uart0_14_grp, uart0_15_grp, + uart0_16_grp, uart0_17_grp, uart0_18_grp, + uart1_0_grp, uart1_1_grp, uart1_2_grp, + uart1_3_grp, uart1_4_grp, uart1_5_grp, + uart1_6_grp, uart1_7_grp, uart1_8_grp, + uart1_9_grp, uart1_10_grp, uart1_11_grp, + uart1_12_grp, uart1_13_grp, uart1_14_grp, + uart1_15_grp, uart1_16_grp, uart1_17_grp, + uart1_18_grp, i2c0_0_grp, i2c0_1_grp, + i2c0_2_grp, i2c0_3_grp, i2c0_4_grp, + i2c0_5_grp, i2c0_6_grp, i2c0_7_grp, + i2c0_8_grp, i2c0_9_grp, i2c0_10_grp, + i2c0_11_grp, i2c0_12_grp, i2c0_13_grp, + i2c0_14_grp, i2c0_15_grp, i2c0_16_grp, + i2c0_17_grp, i2c0_18_grp, i2c1_0_grp, + i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, + i2c1_4_grp, i2c1_5_grp, i2c1_6_grp, + i2c1_7_grp, i2c1_8_grp, i2c1_9_grp, + i2c1_10_grp, i2c1_11_grp, i2c1_12_grp, + i2c1_13_grp, i2c1_14_grp, i2c1_15_grp, + i2c1_16_grp, i2c1_17_grp, i2c1_18_grp, + i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp, + ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp, + ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp, + ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp, + ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp, + ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp, + ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp, + ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp, + ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp, + ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp, + ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp, + ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp, + ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp, + ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp, + ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp, + ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp, + ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp, + ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp, + ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp, + ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp, + ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp, + ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp, + ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp, + ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp, + ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp, + swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp, + swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp, + swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp, + swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp, + swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp, + swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp, + swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp, + swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp, + swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp, + swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp, + swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp, + swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp, + swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp, + swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp, + swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp, + swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp, + swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp, + gpio0_1_grp, gpio0_2_grp, gpio0_3_grp, + gpio0_4_grp, gpio0_5_grp, gpio0_6_grp, + gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, + gpio0_10_grp, gpio0_11_grp, gpio0_12_grp, + gpio0_13_grp, gpio0_14_grp, gpio0_15_grp, + gpio0_16_grp, gpio0_17_grp, gpio0_18_grp, + gpio0_19_grp, gpio0_20_grp, gpio0_21_grp, + gpio0_22_grp, gpio0_23_grp, gpio0_24_grp, + gpio0_25_grp, gpio0_26_grp, gpio0_27_grp, + gpio0_28_grp, gpio0_29_grp, gpio0_30_grp, + gpio0_31_grp, gpio0_32_grp, gpio0_33_grp, + gpio0_34_grp, gpio0_35_grp, gpio0_36_grp, + gpio0_37_grp, gpio0_38_grp, gpio0_39_grp, + gpio0_40_grp, gpio0_41_grp, gpio0_42_grp, + gpio0_43_grp, gpio0_44_grp, gpio0_45_grp, + gpio0_46_grp, gpio0_47_grp, gpio0_48_grp, + gpio0_49_grp, gpio0_50_grp, gpio0_51_grp, + gpio0_52_grp, gpio0_53_grp, gpio0_54_grp, + gpio0_55_grp, gpio0_56_grp, gpio0_57_grp, + gpio0_58_grp, gpio0_59_grp, gpio0_60_grp, + gpio0_61_grp, gpio0_62_grp, gpio0_63_grp, + gpio0_64_grp, gpio0_65_grp, gpio0_66_grp, + gpio0_67_grp, gpio0_68_grp, gpio0_69_grp, + gpio0_70_grp, gpio0_71_grp, gpio0_72_grp, + gpio0_73_grp, gpio0_74_grp, gpio0_75_grp, + gpio0_76_grp, gpio0_77_grp, usb0_0_grp, + usb1_0_grp, pmu0_0_grp, pmu0_1_grp, + pmu0_2_grp, pmu0_3_grp, pmu0_4_grp, + pmu0_5_grp, pmu0_6_grp, pmu0_7_grp, + pmu0_8_grp, pmu0_9_grp, pmu0_10_grp, + pmu0_11_grp, pcie0_0_grp, pcie0_1_grp, + pcie0_2_grp, pcie0_3_grp, pcie0_4_grp, + pcie0_5_grp, pcie0_6_grp, pcie0_7_grp, + csu0_0_grp, csu0_1_grp, csu0_2_grp, + csu0_3_grp, csu0_4_grp, csu0_5_grp, + csu0_6_grp, csu0_7_grp, csu0_8_grp, + csu0_9_grp, csu0_10_grp, csu0_11_grp, + dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp, + dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp, + pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp, + pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp, + trace0_1_grp, trace0_clk_1_grp, trace0_2_grp, + trace0_clk_2_grp, testscan0_0_grp + + Valid values for pins are: + MIO0 - MIO77 + + Valid values for function are: + ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0, + mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss, + spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp, + sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1, + i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav, + ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0, + pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0 + +The following driver-specific properties as defined here are valid to specify in +a pin configuration subnode: + - io-standard: Configure the pin to use the selected IO standard. Valid + arguments are 'IO_STANDARD_LVCMOS33' and 'IO_STANDARD_LVCMOS18'. + - schmitt-cmos: Selects either Schmitt or CMOS input for MIO pins. Valid + arguments are 'PIN_INPUT_TYPE_SCHMITT' and 'PIN_INPUT_TYPE_CMOS'. + +Example: + +firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + pinctrl0: pinctrl { + compatible = "xlnx,zynqmp-pinctrl"; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart0_4_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = <SLEW_RATE_SLOW>; + io-standard = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO18"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + schmitt-cmos = <PIN_INPUT_TYPE_CMOS>; + }; + }; + }; + }; +}; + +uart1 { + ... + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; + ... + +}; diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt index d366f1eb623a..450f3a41c717 100644 --- a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt +++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt @@ -8,9 +8,27 @@ Required properties: - compatible: Must contain: "xlnx,zynqmp-power" - interrupts: Interrupt specifier -------- -Example -------- +Optional properties: + - mbox-names : Name given to channels seen in the 'mboxes' property. + "rx" - Mailbox corresponding to receive path + "tx" - Mailbox corresponding to transmit path + - mboxes : Standard property to specify a Mailbox. Each value of + the mboxes property should contain a phandle to the + mailbox controller device node and an args specifier + that will be the phandle to the intended sub-mailbox + child node to be used for communication. See + Documentation/devicetree/bindings/mailbox/mailbox.txt + for more details about the generic mailbox controller + and client driver bindings. Also see + Documentation/devicetree/bindings/mailbox/ \ + xlnx,zynqmp-ipi-mailbox.txt for typical controller that + is used to communicate with this System controllers. + +-------- +Examples +-------- + +Example with interrupt method: firmware { zynqmp_firmware: zynqmp-firmware { @@ -23,3 +41,20 @@ firmware { }; }; }; + +Example with IPI mailbox method: + +firmware { + + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + + zynqmp_power: zynqmp-power { + compatible = "xlnx,zynqmp-power"; + mboxes = <&ipi_mailbox_pmu0 0>, + <&ipi_mailbox_pmu0 1>; + mbox-names = "tx", "rx"; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/remoteproc/xilinx,zynqmp-r5-remoteproc.txt b/Documentation/devicetree/bindings/remoteproc/xilinx,zynqmp-r5-remoteproc.txt new file mode 100644 index 000000000000..de28128c4e5d --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/xilinx,zynqmp-r5-remoteproc.txt @@ -0,0 +1,135 @@ +Xilinx ARM Cortex A53-R5 remoteproc driver +========================================== + +ZynqMP family of devices use two Cortex R5 processors to help with various +low power / real time tasks. + +This driver requires specific ZynqMP hardware design. + +ZynqMP R5 Device Node: +================================= +A ZynqMP R5 device node is used to represent RPU domain +within ZynqMP SoC. This device node contains RPU processor +subnodes. + +Required Properties: +-------------------- + - compatible : Should be "xlnx,zynqmp-r5-remoteproc-1.0" + - core_conf : R5 core configuration (valid string - split or lock-step) + - interrupts : Interrupt mapping for remoteproc IPI. It is required if the + user uses the remoteproc driver with the RPMsg kernel driver. + - interrupt-parent : Phandle for the interrupt controller. It is required if + the user uses the remoteproc driver with the RPMsg kernel + kernel driver. + +ZynqMP R5 Remoteproc Device Node: +================================= +A ZynqMP R5 Remoteproc device node is used to represent a RPU processor. +It is a subnode to the ZynqMP R5 device node. It also contains tightly +coupled memory subnodes. + +Required Properties: +-------------------- + - pnode-id: ZynqMP R5 processor power domain ID which will be used by + ZynqMP power management unit to idetify the processor. + +Optional Properties: +-------------------- + - memory-region: reversed memory which will be used by R5 processor + + +ZynqMP R5 Remoteproc Device Node: +================================= +A ZynqMP R5 Remoteproc device node is used to represent a RPU processor. +It is a subnode to the ZynqMP R5 device node. + +Required Properties: +-------------------- + - pnode-id: ZynqMP R5 processor power domain ID which will be used by + ZynqMP power management unit to idetify the processor. + +Optional Properties: +-------------------- + - memory-region: reversed memory which will be used by R5 processor + - mboxes: Specify tx and rx mailboxes + - mbox-names: List of identifier strings for tx/rx mailbox channel. + +ZynqMP R5 TCM Device Node: +================================= +The ZynqMP R5 TCM device node is used to represent the TCM memory. +It is a subnode to the ZynqMP R5 processor. + +Required Properties: +-------------------- + - reg: TCM address range + - pnode-id: TCM power domain ID + + +Example: +-------- + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* R5 0 firmware memory in DDR */ + rproc_0_fw_reserved: rproc@3ed000000 { + no-map; + reg = <0x0 0x3ed00000 0x0 0x40000>; + }; + /* DMA shared memory between APU and RPU */ + rproc_0_dma_reserved: rproc@3ed400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x0 0x3ed40000 0x0 0x100000>; + }; + }; + + zynqmp-r5-remoteproc@0 { + compatible = "xlnx,zynqmp-r5-remoteproc-1.0"; + core_conf = "split"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + r5-0: r5@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges; + memory-region = <&rproc_0_fw_reserved>, + <&rproc_0_dma_reserved>; + pnode-id = <0x7>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + tcm-a: tcm@0 { + reg = <0x0 0xFFE00000 0x0 0x10000>, + pnode-id = <0xf>; + }; + tcm-b: tcm@1 { + reg = <0x0 0xFFE20000 0x0 0x10000>, + pnode-id = <0x10>; + }; + }; + } ; + + zynqmp_ipi { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 29 4>; + xlnx,ipi-id = <7>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* APU<->RPU0 IPI mailbox controller */ + ipi_mailbox_rpu0: mailbox@ff90600 { + reg = <0xff990600 0x20>, + <0xff990620 0x20>, + <0xff9900c0 0x20>, + <0xff9900e0 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/zynq_remoteproc.txt b/Documentation/devicetree/bindings/remoteproc/zynq_remoteproc.txt new file mode 100644 index 000000000000..1f6a2d729a5a --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/zynq_remoteproc.txt @@ -0,0 +1,36 @@ +Xilinx ARM Cortex A9-A9 remoteproc driver +========================================== + +Zynq family of devices can use one A9 processor to help with various +low power / real time tasks. + +This driver requires specific Zynq hardware design. + +Zynq RemoteProc Device Node: +================================= +A zynq_remoteproc device node is used to represent the 2nd A9 instance +within Zynq SoC. + +Required properties: +-------------------- + - compatible : should be "xlnx,zynq_remoteproc" + - vring0: soft interrupt for kicking from firmware + - vring1: soft interrupt for kicking from Linux kernel + - srams: firmware memories + +Example: +-------- + + amba { + elf_ddr_0: ddr@3ed00000 { + compatible = "mmio-sram"; + reg = <0x100000 0x80000>; + }; + }; + + zynq_remoteproc@0 { + compatible = "xlnx,zynq_remoteproc"; + vring0 = <15>; + vring1 = <14>; + srams = <&elf_ddr_0>; + }; diff --git a/Documentation/devicetree/bindings/serial/uartlite.c b/Documentation/devicetree/bindings/serial/uartlite.c new file mode 100644 index 000000000000..7ae900880d30 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/uartlite.c @@ -0,0 +1,26 @@ +Xilinx Axi Uartlite controller Device Tree Bindings +--------------------------------------------------------- + +Required properties: +- compatible : Can be either of + "xlnx,xps-uartlite-1.00.a" + "xlnx,opb-uartlite-1.00.b" +- reg : Physical base address and size of the Axi Uartlite + registers map. +- interrupts : Property with a value describing the interrupt + number. +- interrupt-parent : Must be core interrupt controller. + +Optional properties: +- port-number : Set Uart port number +- clock-names : Should be "s_axi_aclk" +- clocks : Input clock specifier. Refer to common clock bindings. + +Example: +serial@800C0000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x0 0x800c0000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0x0 0x6e 0x1>; + port-number = <0>; +}; diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine-npi.txt b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine-npi.txt new file mode 100644 index 000000000000..b1c1466a34ee --- /dev/null +++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine-npi.txt @@ -0,0 +1,23 @@ +Xilinx AI Engine NPI +-------------------- + +The Xilinx AI Engine NPI space is where the privileged operations for AI Engine +device are handled, such as reset and pll. The space is typically meant to be +owned by platform management software, and this space is accessible only when +the platform management software grants the access. Thus, this dt binding only +works in such configuration, and in case the platform locks the access, +the non-secure software fails to access the device. + +This is a temporary solution to allow direct access to NPI space. + +Required properties: + +- compatible: Must be "xlnx,ai-engine-npi" +- reg: Physical base address and length of the registers set for the device. + +Example: + + aie-npi@f70a0000 { + compatible = "xlnx,ai-engine-npi"; + reg = <0x0 0xf70a0000 0x0 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai_engine.txt b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai_engine.txt new file mode 100644 index 000000000000..04244a6bc2da --- /dev/null +++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,ai_engine.txt @@ -0,0 +1,28 @@ +Xilinx AI Engine +---------------- + +The Xilinx AI Engine is a tile processor with many cores (up to 400) that +can run in parallel. The data routing between cores is configured through +internal switches, and shim tiles interface with external interconnect, such +as memory or PL. + +Required properties: + +- compatible: Must be "xlnx,ai_engine". +- reg: Physical base address and length of the registers set for the device. +- interrupt-parent: the phandle to the interrupt controller. +- interrupts: the interrupt numbers. +- interrupt-names: Should be "interrupt0", "interrupt1", "interrupt2" or + "interrupt3". + +Example: + + ai_engine@80000000 { + compatible = "xlnx,ai_engine"; + reg = <0x0 0x80000000 0x0 0x20000000>; + interrupt-parent = <&gic>; + interrupts = <0x0 0x94 0x1>, + <0x0 0x95 0x1>, + <0x0 0x96 0x1>; + interrupt-names = "interrupt1", "interrupt2", "interrupt3"; + }; diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt index 6786d6715df0..98474f2accca 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt +++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt @@ -16,16 +16,60 @@ Required properties: 1. vcu slcr 2. Logicore reg-names should contain name for the each register sequence. -- clocks: phandle for aclk and pll_ref clocksource -- clock-names: The identification string, "aclk", is always required for - the axi clock. "pll_ref" is required for pll. +- #clock-cells : Must be 1 +- clocks: phandle for aclk, pll_ref and encoder/decoder clocksources +- clock-names: The identification string, + * "aclk", is always required for the axi clock. + * "pll_ref" is required for pll. + * "vcu_core_enc" is required for VCU core encoder. + * "vcu_core_dec" is required for VCU core decoder. + * "vcu_mcu_enc" is required for MCU core encoder. + * "vcu_mcu_dec" is required for MCU core decoder. +- ranges +- VCU Init driver node define the following child nodes: + * Allegro encoder driver node + - compatible: Must be "al,al5e" + - reg: There is a one set of register. + - interrupts: interrupt number to the cpu. + - interrupt-parent: the phandle for the interrupt controller + that services interrupts for this device. + * Allegro decoder driver node + - compatible: Must be "al,al5d" + - reg: There is a one set of register. + - interrupts: interrupt number to the cpu. + - interrupt-parent: the phandle for the interrupt controller + that services interrupts for this device. + +Optional properties: +- reset-gpios : The GPIO used to reset the VCU, if available. Need use this + reset gpio when in design 'vcu_resetn' is driven by gpio. See + Documentation/devicetree/bindings/gpio/gpio.txt for details. + Example: xlnx_vcu: vcu@a0040000 { compatible = "xlnx,vcu-logicoreip-1.0"; + #address-cells = <2>; + #size-cells = <2>; reg = <0x0 0xa0040000 0x0 0x1000>, <0x0 0xa0041000 0x0 0x1000>; reg-names = "vcu_slcr", "logicore"; - clocks = <&si570_1>, <&clkc 71>; - clock-names = "pll_ref", "aclk"; + reset-gpios = <&gpio 0x4e GPIO_ACTIVE_HIGH>; + #clock-cells = <0x1>; + clock-names = "pll_ref", "aclk", "vcu_core_enc", "vcu_core_dec", "vcu_mcu_enc", "vcu_mcu_dec"; + clocks = <&si570_1>, <&clkc 71>, <&xlnx_vcu 1>, <&xlnx_vcu 2>, <&xlnx_vcu 3>, <&xlnx_vcu 4>; + ranges; + encoder: al5e@a0000000 { + compatible = "al,al5e"; + reg = <0x0 0xa0000000 0x0 0x10000>; + interrupts = <0 89 4>; + interrupt-parent = <&gic>; + }; + + decoder: al5d@a0020000 { + compatible = "al,al5d"; + reg = <0x0 0xa0020000 0x0 0x10000>; + interrupts = <0 89 4>; + interrupt-parent = <&gic>; + }; }; diff --git a/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt b/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt index cbc93c8f4963..6b5e4f762268 100644 --- a/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt +++ b/Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt @@ -14,7 +14,7 @@ Required properties: - interrupts: List of Interrupt numbers. - reg: Base address and size of the IP core instance. - clock-names: List of input clocks. - Required elements: "s_axi_lite_aclk", "aud_mclk" + Required elements: "s_axi_lite_aclk", "m_axis_mm2s_aclk", "aud_mclk", "s_axis_s2mm_aclk" - clocks: Input clock specifier. Refer to common clock bindings. Example: @@ -24,6 +24,6 @@ Example: interrupt-parent = <&gic>; interrupts = <0 104 4>, <0 105 4>; reg = <0x0 0x80010000 0x0 0x1000>; - clock-names = "s_axi_lite_aclk", "aud_mclk"; - clocks = <&clk 71>, <&clk_wiz_1 0>; + clock-names = "s_axi_lite_aclk", "m_axis_mm2s_aclk", "aud_mclk", "s_axis_s2mm_aclk"; + clocks = <&clk 71>, <&audio_ss_0_clk_wiz_0 0>, <&audio_ss_0_clk_wiz_0 0>, <&clk 71>; }; diff --git a/Documentation/devicetree/bindings/sound/xlnx,dp-snd-card.txt b/Documentation/devicetree/bindings/sound/xlnx,dp-snd-card.txt new file mode 100644 index 000000000000..7eb932913983 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/xlnx,dp-snd-card.txt @@ -0,0 +1,17 @@ +Device-Tree bindings for Xilinx ZynqMP DisplayPort Audio Card + +The card driver integrates codec and pcm components and represents as a single +audio device. + +Required properties: + - compatible: Should be "xlnx,dp-snd-card". + - xlnx,dp-snd-pcm: phandle(s) to the ZynqMP DP PCM node. + - xlnx,dp-snd-codec: phandle to the ZynqMP DP card node. + +Example: + + xlnx_dp_snd_card: dp_snd_card { + compatible = "xlnx,dp-snd-card"; + xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; + xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; + }; diff --git a/Documentation/devicetree/bindings/sound/xlnx,dp-snd-codec.txt b/Documentation/devicetree/bindings/sound/xlnx,dp-snd-codec.txt new file mode 100644 index 000000000000..d094fdd9d9e0 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/xlnx,dp-snd-codec.txt @@ -0,0 +1,18 @@ +Device-Tree bindings for Xilinx ZynqMP DisplayPort Codec + +The codec driver handles the audio clock and format management. + +Required properties: + - compatible: Should be "xlnx,dp-snd-codec". + - clocks: The phandle for the audio clock. The audio clock should be + configured to the correct audio clock rate, which should be one of + (44100 * 512) or (48000 * 512). + - clock-names: The identification string should be "aud_clk". + +Example: + + xlnx_dp_snd_codec0: dp_snd_codec0 { + compatible = "xlnx,dp-snd-codec"; + clocks = <&dp_aud_clk>; + clock-names = "aud_clk"; + }; diff --git a/Documentation/devicetree/bindings/sound/xlnx,dp-snd-pcm.txt b/Documentation/devicetree/bindings/sound/xlnx,dp-snd-pcm.txt new file mode 100644 index 000000000000..303232a2a375 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/xlnx,dp-snd-pcm.txt @@ -0,0 +1,18 @@ +Device-Tree bindings for Xilinx ZynqMP DisplayPort PCM + +The DPDMA driver of ZynqMP DisplayPort subsystem is based on DMA engine, +and the DP PCM driver is based on snd dmaengine helpers. + +Required properties: + - compatible: Should be "xlnx,dp-snd-pcm". + - dmas: the phandle list of DMA specifiers. The dma channel ID should be one + of 4 for audio0 channel or 5 for audio1 channel. + - dma-names: the indentifier strings for DMAs. The value should be "tx". + +Example: + + xlnx_dp_snd_pcm0: dp_snd_pcm0 { + compatible = "xlnx,dp-snd-pcm"; + dmas = <&xlnx_dpdma 4>; + dma-names = "tx"; + }; diff --git a/Documentation/devicetree/bindings/sound/xlnx,i2s.txt b/Documentation/devicetree/bindings/sound/xlnx,i2s.txt index 5e7c7d5bb60a..86b727c88bf9 100644 --- a/Documentation/devicetree/bindings/sound/xlnx,i2s.txt +++ b/Documentation/devicetree/bindings/sound/xlnx,i2s.txt @@ -11,18 +11,32 @@ Required property common to both I2S playback and capture: - xlnx,dwidth: sample data width. Can be any of 16, 24. - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4. supported channels = 2 * xlnx,num-channels + - xlnx,snd-pcm: reference to audio formatter block + - clock-names: List of input clocks. + Required elements for I2S Tx: "s_axi_ctrl_aclk", "aud_mclk", "s_axis_aud_aclk". + Required elements for I2S Rx: "s_axi_ctrl_aclk", "aud_mclk", "m_axis_aud_aclk". + - clocks: Input clock specifier. Refer to common clock bindings. Example: i2s_receiver@a0080000 { compatible = "xlnx,i2s-receiver-1.0"; + clock-names = "s_axi_ctrl_aclk", "aud_mclk", "m_axis_aud_aclk"; + clocks = <&clk 71>, <&audio_ss_0_clk_wiz_0 0>, <&clk 71>; reg = <0x0 0xa0080000 0x0 0x10000>; xlnx,dwidth = <0x18>; xlnx,num-channels = <1>; + xlnx,snd-pcm = <&audio_ss_0_audio_formatter_0>; }; i2s_transmitter@a0090000 { compatible = "xlnx,i2s-transmitter-1.0"; + clock-names = "s_axi_ctrl_aclk", "aud_mclk", "s_axis_aud_aclk"; + clocks = <&clk 71>, <&audio_ss_0_clk_wiz_0 0>, <&audio_ss_0_clk_wiz_0 0>; reg = <0x0 0xa0090000 0x0 0x10000>; xlnx,dwidth = <0x18>; xlnx,num-channels = <1>; + xlnx,snd-pcm = <&audio_ss_0_audio_formatter_0>; }; + Documentation of "audio_ss_0_audio_formatter_0" node is located + at Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt + diff --git a/Documentation/devicetree/bindings/sound/xlnx,spdif.txt b/Documentation/devicetree/bindings/sound/xlnx,spdif.txt index 15c2d64d247c..59bfa6bcb566 100644 --- a/Documentation/devicetree/bindings/sound/xlnx,spdif.txt +++ b/Documentation/devicetree/bindings/sound/xlnx,spdif.txt @@ -5,7 +5,8 @@ The IP supports playback and capture of SPDIF audio Required properties: - compatible: "xlnx,spdif-2.0" - clock-names: List of input clocks. - Required elements: "s_axi_aclk", "aud_clk_i" + Required elements for SPDIF Tx: "aud_clk_i", "s_axi_aclk", "s_axis_aclk". + Required elements for SPDIF Rx: "aud_clk_i", "s_axi_aclk", "m_axis_aclk". - clocks: Input clock specifier. Refer to common clock bindings. - reg: Base address and address length of the IP core instance. - interrupts-parent: Phandle for interrupt controller. @@ -14,10 +15,10 @@ Required properties: 1 :- transmitter mode - xlnx,aud_clk_i: input audio clock value. -Example: +Example - SPDIF Rx: spdif_0: spdif@80010000 { - clock-names = "aud_clk_i", "s_axi_aclk"; - clocks = <&misc_clk_0>, <&clk 71>; + clock-names = "aud_clk_i", "s_axi_aclk", "m_axis_aclk"; + clocks = <&si570_1>, <&clk 71>, <&clk 71>; compatible = "xlnx,spdif-2.0"; interrupt-names = "spdif_interrupt"; interrupt-parent = <&gic>; diff --git a/Documentation/devicetree/bindings/sound/xlnx,v-uhdsdi-audio.txt b/Documentation/devicetree/bindings/sound/xlnx,v-uhdsdi-audio.txt new file mode 100644 index 000000000000..69134458b9d5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/xlnx,v-uhdsdi-audio.txt @@ -0,0 +1,60 @@ +Device-Tree bindings for Xilinx SDI audio + +The IP core supports embed/extract of audio in SDI Tx and Rx +protocol respectively. Reference to PG: +https://www.xilinx.com/support/documentation/ip_documentation/v_uhdsdi_audio/v1_0/pg309-v-uhdsdi-audio.pdf + +Required properties: + - compatible: Should be one of: + "xlnx,v-uhdsdi-audio-2.0" + "xlnx,v-uhdsdi-audio-1.0" + Note: v1.0 (xlnx,v-uhdsdi-audio-1.0) is deprecated + and driver no longer supports it. Mandatory to upgrade to v2.0 + - interrupts: Interrupt number. + - interrupts-parent: phandle for interrupt controller. + - reg: Base address and size of the IP core instance. + - xlnx,snd-pcm: reference to audio formatter block + - clock-names: List of input clocks. + Required elements for SDI Embed: "s_axi_aclk", "s_axis_clk", "sdi_embed_clk". + Required elements for SDI Extract: "s_axi_aclk", "sdi_extract_clk", "m_axis_clk". + - clocks: Input clock specifier. Refer to common clock bindings. + +SDI embed contains a output port to remote endpoint of SDI video Tx node. +This pipeline should be described using the DT bindings defined in +Documentation/devicetree/bindings/graph.txt + +Example: + + audio_ss_0_v_uhdsdi_audio_extract_0: v_uhdsdi_audio@80080000 { + compatible = "xlnx,v-uhdsdi-audio-2.0"; + clock-names = "s_axi_aclk", "sdi_extract_clk", "m_axis_clk"; + clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_0>; + interrupt-names = "interrupt"; + interrupt-parent = <&gic>; + interrupts = <0 106 4>; + reg = <0x0 0x80080000 0x0 0x10000>; + xlnx,snd-pcm = <&audio_ss_0_audio_formatter_0>; + }; + + audio_ss_0_v_uhdsdi_audio_embed_0: v_uhdsdi_audio@80090000 { + compatible = "xlnx,v-uhdsdi-audio-2.0"; + clock-names = "s_axi_aclk", "s_axis_clk", "sdi_embed_clk"; + clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_1>; + interrupt-names = "interrupt"; + interrupt-parent = <&gic>; + interrupts = <0 107 4>; + reg = <0x0 0x80090000 0x0 0x10000>; + xlnx,snd-pcm = <&audio_ss_0_audio_formatter_0>; + sdi_av_port: port@0 { + reg = <0>; + sditx_audio_embed_src: endpoint { + remote-endpoint = <&sdi_audio_sink_port>; + }; + }; + }; + + Node 'v_smpte_uhdsdi_tx_ss' is documented in SDI Tx video bindings, + located at Documentation/devicetree/bindings/display/xlnx/xlnx,sdi-tx.txt. + + Node 'audio_ss_0_audio_formatter_0' node is documented + at Documentation/devicetree/bindings/sound/xlnx,audio-formatter.txt diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.txt b/Documentation/devicetree/bindings/spi/spi-xilinx.txt index dc924a5f71db..9a9af55055f5 100644 --- a/Documentation/devicetree/bindings/spi/spi-xilinx.txt +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.txt @@ -6,16 +6,27 @@ Required properties: - reg : Physical base address and size of SPI registers map. - interrupts : Property with a value describing the interrupt number. +- fifo-size : Depth of TX/RX Fifos Optional properties: -- xlnx,num-ss-bits : Number of chip selects used. +- num-cs : Number of chip selects used. +- bits-per-word : Number of bits per word. +- clock-names : Can be one or more strings from "axi_clk", "axi4_clk" + and "spi_clk" depending on IP configurations. +- clocks : Input clock specifier. Refer to common clock bindings. +- xlnx,startup-block : Indicates whether startup block is enabled or disabled. Example: axi_quad_spi@41e00000 { compatible = "xlnx,xps-spi-2.00.a"; + clock-names = "axi_clk", "axi4_clk", "spi_clk"; + clocks = <&clkc 71>, <&clkc 72>, <&clkc 73>; interrupt-parent = <&intc>; interrupts = <0 31 1>; reg = <0x41e00000 0x10000>; - xlnx,num-ss-bits = <0x1>; + num-cs = <0x1>; + fifo-size = <256>; + bits-per-word = <8>; + xlnx,startup-block; }; diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt index 0f6d37ff541c..a40827f58164 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.txt @@ -2,7 +2,8 @@ Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings ------------------------------------------------------------------- Required properties: -- compatible : Should be "xlnx,zynqmp-qspi-1.0". +- compatible : Should be "xlnx,zynqmp-qspi-1.0" for zynqmp or + "xlnx,versal-qspi-1.0" for versal. - reg : Physical base address and size of GQSPI registers map. - interrupts : Property with a value describing the interrupt number. @@ -12,6 +13,14 @@ Required properties: Optional properties: - num-cs : Number of chip selects used. +- has-io-mode : boolean property describes the controller operating + mode. if exists controller will operate in IO mode + else dma mode. +- is-dual : zynqmp qspi support for dual-parallel mode configuration + value should be 1. +- is-stacked : zynqmp qspi support for stacked mode configuration. + to enable this mode, is-dual should be 0 and is-stacked + should be 1. Example: qspi: spi@ff0f0000 { diff --git a/Documentation/devicetree/bindings/staging/xroeframer/xroeframer.txt b/Documentation/devicetree/bindings/staging/xroeframer/xroeframer.txt new file mode 100644 index 000000000000..8dabef16d083 --- /dev/null +++ b/Documentation/devicetree/bindings/staging/xroeframer/xroeframer.txt @@ -0,0 +1,17 @@ +* Xilinx Radio over Ethernet Framer driver + +Required properties: +- compatible: must be "xlnx,roe-framer-1.0" +- reg: physical base address of the framer and length of memory mapped region +- clock-names: list of clock names +- clocks: list of clock sources corresponding to the clock names + +Example: + roe_framer@a0000000 { + compatible = "xlnx,roe-framer-1.0"; + reg = <0x0 0xa0000000 0x0 0x10000>; + clock-names = "s_axi_aclk", "m_axis_defm_aclk", + "s_axis_fram_aclk", "tx0_eth_port_clk", + "internal_bus_clk"; + clocks = <0x43 0x44 0x44 0x45 0x45>; + }; diff --git a/Documentation/devicetree/bindings/staging/xroetrafficgen/xroetrafficgen.txt b/Documentation/devicetree/bindings/staging/xroetrafficgen/xroetrafficgen.txt new file mode 100644 index 000000000000..3516d3ff8009 --- /dev/null +++ b/Documentation/devicetree/bindings/staging/xroetrafficgen/xroetrafficgen.txt @@ -0,0 +1,15 @@ +* Xilinx Radio over Ethernet Traffic Generator driver + +Required properties: +- compatible: must be "xlnx,roe-framer-1.0" +- reg: physical base address of the framer and length of memory mapped region +- clock-names: list of clock names +- clocks: list of clock sources corresponding to the clock names + +Example: + roe_radio_ctrl@a0060000 { + compatible = "xlnx,roe-traffic-gen-1.0"; + reg = <0x0 0xa0060000 0x0 0x10000>; + clock-names = "s_axis_fram_aclk", "s_axi_aclk"; + clocks = <0x44 0x43>; + }; diff --git a/Documentation/devicetree/bindings/uio/xilinx_apm.txt b/Documentation/devicetree/bindings/uio/xilinx_apm.txt new file mode 100644 index 000000000000..a11c82e84b6a --- /dev/null +++ b/Documentation/devicetree/bindings/uio/xilinx_apm.txt @@ -0,0 +1,44 @@ +* Xilinx AXI Performance monitor IP + +Required properties: +- compatible: "xlnx,axi-perf-monitor" +- interrupts: Should contain APM interrupts. +- interrupt-parent: Must be core interrupt controller. +- reg: Should contain APM registers location and length. +- xlnx,enable-profile: Enables the profile mode. +- xlnx,enable-trace: Enables trace mode. +- xlnx,num-monitor-slots: Maximum number of slots in APM. +- xlnx,enable-event-count: Enable event count. +- xlnx,enable-event-log: Enable event logging. +- xlnx,have-sampled-metric-cnt:Sampled metric counters enabled in APM. +- xlnx,num-of-counters: Number of counters in APM +- xlnx,metric-count-width: Metric Counter width (32/64) +- xlnx,metrics-sample-count-width: Sampled metric counter width +- xlnx,global-count-width: Global Clock counter width +- clocks: Input clock specifier. + +Optional properties: +- xlnx,id-filter-32bit: APM is in 32-bit mode + +Example: +++++++++ + +apm: apm@44a00000 { + compatible = "xlnx,axi-perf-monitor"; + interrupt-parent = <&axi_intc_1>; + interrupts = <1 2>; + reg = <0x44a00000 0x1000>; + clocks = <&clkc 15>; + xlnx,enable-profile = <0>; + xlnx,enable-trace = <0>; + xlnx,num-monitor-slots = <4>; + xlnx,enable-event-count = <1>; + xlnx,enable-event-log = <1>; + xlnx,have-sampled-metric-cnt = <1>; + xlnx,num-of-counters = <8>; + xlnx,metric-count-width = <32>; + xlnx,metrics-sample-count-width = <32>; + xlnx,global-count-width = <32>; + xlnx,metric-count-scale = <1>; + xlnx,id-filter-32bit; +}; diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt index 4aae5b2cef56..622e27fc0b71 100644 --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt @@ -1,7 +1,8 @@ Xilinx SuperSpeed DWC3 USB SoC controller Required properties: -- compatible: Should contain "xlnx,zynqmp-dwc3" +- compatible: May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3" +- reg: Base address and length of the register control block - clocks: A list of phandles for the clocks listed in clock-names - clock-names: Should contain the following: "bus_clk" Master/Core clock, have to be >= 125 MHz for SS @@ -13,20 +14,38 @@ Required child node: A child node must exist to represent the core DWC3 IP block. The name of the node is not important. The content of the node is defined in dwc3.txt. +Optional properties for xlnx,zynqmp-dwc3: +- nvmem-cells: list of phandle to the nvmem data cells. +- nvmem-cell-names: Names for the each nvmem-cells specified. + +Optional properties for snps,dwc3: +- dma-coherent: Enable this flag if CCI is enabled in design. Adding this + flag configures Global SoC bus Configuration Register and + Xilinx USB 3.0 IP - USB coherency register to enable CCI. +- snps,enable-hibernation: Add this flag to enable hibernation support for + peripheral mode +- interrupt-names: This property provides the names of the interrupt ids used + Example device node: usb@0 { #address-cells = <0x2>; #size-cells = <0x1>; compatible = "xlnx,zynqmp-dwc3"; + reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk" "ref_clk"; clocks = <&clk125>, <&clk125>; ranges; + nvmem-cells = <&soc_revision>; + nvmem-cell-names = "soc_revision"; dwc3@fe200000 { compatible = "snps,dwc3"; reg = <0x0 0xfe200000 0x40000>; + interrupt-name = "dwc_usb3"; interrupts = <0x0 0x41 0x4>; dr_mode = "host"; + dma-coherent; + snps,enable-hibernation }; }; diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 14d97c40b75c..81df8753ff15 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -85,6 +85,19 @@ Optional properties: - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame length adjustment when the fladj_30mhz_sdbnd signal is invalid or incorrect. + - snps,refclk_fladj: Enable frame length adjustment for SOF/ITP counter. + - snps,enable_guctl1_resume_quirk: Adding this flag sets bit 10 of GUCTL1 + thus enabling the workaround in HW to fix the issue where the controller + was not able to generate correct CRC checksum on the very first transfer + packet after sending resume signal. + - snps,enable_guctl1_ipd_quirk: Adding this flag sets bit 9 of GUCTL1 + enabling the workaround in HW to reduce the Inter Packet Delay (IPD) + and making controller enumerate FS/LS devices connected behind VIA-LAB. + - snps,xhci-stream-quirk: Dwc3 host controller has a bug where it sometimes + fails to process the traansfer descriptors present in the BULK IN + stream ring. Since the controller is not processing any TD, no transfer + events will be triggered, resulting in a hang condition. Enabling this + flag in dts fixes the above said issue. - snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode only. Set this and rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31 programming guide diff --git a/Documentation/devicetree/bindings/usb/ehci-xilinx.txt b/Documentation/devicetree/bindings/usb/ehci-xilinx.txt new file mode 100644 index 000000000000..4df7ad6e3541 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ehci-xilinx.txt @@ -0,0 +1,21 @@ +Xilinx USB EHCI controller + +Required properties: +- compatible: must be "xlnx,xps-usb-host-1.00.a" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: The EHCI interrupt + +Optional properties: +- xlnx,ext-vbus-valid: Use external VBUS +- xlnx,support-usb-fs: Support for Full Speed USB +- xlnx,use-phy-bus-pwr: Use phy bus power in USB + +Example: + + xps_usb_host_0: usb@82400000 { + compatible = "xlnx,xps-usb-host-1.00.a"; + interrupt-parent = <&xps_intc_0>; + interrupts = < 0 2 >; + reg = < 0x82400000 0x200 >; + } ; diff --git a/Documentation/devicetree/bindings/usb/udc-xilinx.txt b/Documentation/devicetree/bindings/usb/udc-xilinx.txt index 47b4e397a08d..86f705384132 100644 --- a/Documentation/devicetree/bindings/usb/udc-xilinx.txt +++ b/Documentation/devicetree/bindings/usb/udc-xilinx.txt @@ -6,13 +6,16 @@ Required properties: device registers map. - interrupts : Should contain single irq line of USB2 device controller -- xlnx,has-builtin-dma : if DMA is included +- xlnx,has-builtin-dma : If DMA is included -Example: - axi-usb2-device@42e00000 { - compatible = "xlnx,usb2-device-4.00.a"; - interrupts = <0x0 0x39 0x1>; - reg = <0x42e00000 0x10000>; - xlnx,has-builtin-dma; - }; +Optional properties: +- clock-names : Should be "s_axi_aclk" +- clocks : Input clock specifier. Refer to common clock bindings. +Example: + axi-usb2-device@42e00000 { + compatible = "xlnx,usb2-device-4.00.a"; + interrupts = <0x0 0x39 0x1>; + reg = <0x42e00000 0x10000>; + xlnx,has-builtin-dma; + }; diff --git a/Documentation/devicetree/bindings/video/xilinx-fb.txt b/Documentation/devicetree/bindings/video/xilinx-fb.txt new file mode 100644 index 000000000000..11a6ba01a032 --- /dev/null +++ b/Documentation/devicetree/bindings/video/xilinx-fb.txt @@ -0,0 +1,35 @@ +Xilinx Axi TFT controller Device Tree Bindings +--------------------------------------------------------- + +Required properties: +- compatible : Can be any of the following + "xlnx,xps-tft-1.00.a","xlnx,xps-tft-2.00.a", + "xlnx,xps-tft-2.01.a","xlnx,plb-tft-cntlr-ref-1.00.a", + "xlnx,plb-dvi-cntlr-ref-1.00.c" +- reg : Physical base address and size of the Axi Tft + registers map +- interrupts : Property with a value describing the interrupt + number +- interrupt-parent : Must be core interrupt controller +- xlnx,dcr-splb-slave-if : Accessing TFT Controller through Bus or DCR interface. + for BUS its value is 1 and for DCR it is 0. + default is BUS i.e. 1 +- resolution : <xres yres> pixel resolution of framebuffer.Some + implementations use a different resolution +- virtual-resolution : <xvirt yvirt> Size of framebuffer in memory. +- rotate-display : (empty) rotate display 180 degrees +- phys-size : <screen_width_mm screen_height_mm> width and heigth of + screen + +Example: +axi_tft_0: axi_tft@44a00000 { + compatible = "xlnx,xps-tft-1.00.a"; + interrupt-parent = <&axi_intc>; + interrupts = <1 0>; + reg = <0x44a00000 0x10000>; + xlnx,dcr-splb-slave-if = <0x1>; + resolution = <640 480>; + virtual-resolution = <1024 480>; + phys-size = <1024 512>; + rotate-display; +}; diff --git a/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt b/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt index c6ae9c9d5e3e..10d68003158d 100644 --- a/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt @@ -1,21 +1,28 @@ -Xilinx AXI/PLB soft-core watchdog Device Tree Bindings ---------------------------------------------------------- +Xilinx AXI/PLB soft-core watchdog and window watchdog Device Tree Bindings +-------------------------------------------------------------------------- Required properties: - compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or - "xlnx,xps-timebase-wdt-1.01.a". + "xlnx,xps-timebase-wdt-1.01.a" or + "xlnx,versal-wwdt-1.0". - reg : Physical base address and size Optional properties: - clocks : Input clock specifier. Refer to common clock bindings. - clock-frequency : Frequency of clock in Hz + +Optional properties for AXI/PLB soft-core watchdog: - xlnx,wdt-enable-once : 0 - Watchdog can be restarted 1 - Watchdog can be enabled just once - xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles, <val> is integer from 8 to 31. +Optional properties for window watchdog: +- timeout-sec : Watchdog timeout value (in seconds). + Example: +Xilinx AXI/PLB soft-core watchdog: axi-timebase-wdt@40100000 { clock-frequency = <50000000>; compatible = "xlnx,xps-timebase-wdt-1.00.a"; @@ -24,3 +31,11 @@ axi-timebase-wdt@40100000 { xlnx,wdt-enable-once = <0x0>; xlnx,wdt-interval = <0x1b>; } ; + +Xilinx Versal window watchdog: +watchdog@fd4d0000 { + compatible = "xlnx,versal-wwdt-1.0"; + reg = <0x0 0xfd4d0000 0x0 0x10000>; + clocks = <&clk25>; + timeout-sec = <10>; +} ; diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt index d058ace29345..0c75bb153ca6 100644 --- a/Documentation/devicetree/bindings/xilinx.txt +++ b/Documentation/devicetree/bindings/xilinx.txt @@ -253,6 +253,7 @@ Optional properties: - 8-bit (empty) : Set this property for SystemACE in 8 bit mode + - port-number = <port_number> : Set port number for particular device iii) Xilinx EMAC and Xilinx TEMAC diff --git a/Documentation/devicetree/bindings/xlnx,ctrl-fb.txt b/Documentation/devicetree/bindings/xlnx,ctrl-fb.txt new file mode 100644 index 000000000000..8abc053dfa30 --- /dev/null +++ b/Documentation/devicetree/bindings/xlnx,ctrl-fb.txt @@ -0,0 +1,22 @@ +The Xilinx framebuffer DMA engine supports two soft IP blocks: one IP +block is used for reading video frame data from memory (FB Read) to the device +and the other IP block is used for writing video frame data from the device +to memory (FB Write). Both the FB Read/Write IP blocks are aware of the +format of the data being written to or read from memory including RGB and +YUV in packed, planar, and semi-planar formats. Because the FB Read/Write +is format aware, only one buffer pointer is needed by the IP blocks even +when planar or semi-planar format are used. + +Required properties: + - compatible: Should be "xlnx,ctrl-fbwr-1.0" for framebuffer Write OR + "xlnx,ctrl-fbrd-1.0" for framebuffer Read. + - reg: Base address and size of the IP core. + - reset-gpios: gpio to reset the framebuffer IP + +Example: + + fbwr@0xa0000000 { + compatible = "xlnx,ctrl-fbwr-1.0"; + reg = <0x0 0xa0000000 0x0 0x10000>; + reset-gpios = <&gpio 82 1>; + }; diff --git a/Documentation/devicetree/bindings/xlnx,ctrl-vpss.txt b/Documentation/devicetree/bindings/xlnx,ctrl-vpss.txt new file mode 100644 index 000000000000..04e6426f4e9b --- /dev/null +++ b/Documentation/devicetree/bindings/xlnx,ctrl-vpss.txt @@ -0,0 +1,21 @@ +The Xilinx VPSS Scaler is a Video IP that supports up scaling, down scaling and +no scaling functionailty along with color space conversion. This supports custom +resolution values between 0 to 4096. + +Required properties: + +- compatible: Must be "xlnx,ctrl-xvpss-1.0". +- reg: Base address and size of the IP core. +- reset-gpios: gpio to reset the framebuffer IP +- xlnx,vpss-taps: number of taps +- xlnx,vpss-ppc: pixels per clock + +Example: + + ctrlvpss: vpss@0xa0200000 { + compatible = "xlnx,ctrl-xvpss-1.0"; + reg = <0x0 0xa0200000 0x0 0x30000>; + reset-gpios = <&gpio 80 1>; + xlnx,vpss-taps = <6>; + xlnx,vpss-ppc = <2>; + }; diff --git a/Documentation/devicetree/configfs-overlays.txt b/Documentation/devicetree/configfs-overlays.txt new file mode 100644 index 000000000000..5fa43e064307 --- /dev/null +++ b/Documentation/devicetree/configfs-overlays.txt @@ -0,0 +1,31 @@ +Howto use the configfs overlay interface. + +A device-tree configfs entry is created in /config/device-tree/overlays +and and it is manipulated using standard file system I/O. +Note that this is a debug level interface, for use by developers and +not necessarily something accessed by normal users due to the +security implications of having direct access to the kernel's device tree. + +* To create an overlay you mkdir the directory: + + # mkdir /config/device-tree/overlays/foo + +* Either you echo the overlay firmware file to the path property file. + + # echo foo.dtbo >/config/device-tree/overlays/foo/path + +* Or you cat the contents of the overlay to the dtbo file + + # cat foo.dtbo >/config/device-tree/overlays/foo/dtbo + +The overlay file will be applied, and devices will be created/destroyed +as required. + +To remove it simply rmdir the directory. + + # rmdir /config/device-tree/overlays/foo + +The rationalle of the dual interface (firmware & direct copy) is that each is +better suited to different use patterns. The firmware interface is what's +intended to be used by hardware managers in the kernel, while the copy interface +make sense for developers (since it avoids problems with namespaces). |