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Diffstat (limited to 'Documentation/devicetree/bindings/media/xilinx')
18 files changed, 1347 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt new file mode 100644 index 000000000000..0993ad622008 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt @@ -0,0 +1,128 @@ + +Xilinx MIPI CSI2 Receiver Subsystem (CSI2RxSS) +---------------------------------------------- + +The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 traffic +from compliant camera sensors and send the output as AXI4 Stream video data +for image processing. The subsystem consists of a MIPI DPHY in slave mode +which captures the data packets. This is passed along the MIPI CSI2 IP which +extracts the packet data. This data is taken in by the Video Format Bridge +(VFB) if selected and converted into AXI4 Stream video data at selected +pixels per clock as per AXI4-Stream Video IP and System Design UG934. + +For more details, please refer to PG232 MIPI CSI-2 Receiver Subsystem v4.1 + +Required properties: + +- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-5.0" or + "xlnx,mipi-csi2-rx-subsystem-4.1" or "xlnx,mipi-csi2-rx-subsystem-4.0". + The older strings "xlnx,mipi-csi2-rx-subsystem-2.0" and + "xlnx,mipi-csi2-rx-subsystem-3.0" are deprecated. + +- reg: Physical base address and length of the registers set for the device. + +- xlnx,max-lanes: Maximum active lanes in the design. + +- xlnx,en-active-lanes: Enable Active lanes configuration in Protocol + Configuration Register. + +- xlnx,vc: Virtual Channel, specifies virtual channel number to be filtered. + If this is 4 then all virtual channels are allowed. + +- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw design. + Packets other than this data type (except for RAW8 and User defined data + types) will be filtered out. Possible values are RAW6, RAW7, RAW8, RAW10, + RAW12, RAW14, RAW16, RAW20, RGB444, RGB555, RGB565, RGB666, RGB888 and YUV4228bit. + +- xlnx,vfb: Video Format Bridge, Denotes if Video Format Bridge is selected + so that output is as per AXI stream documented in UG934. + +- xlnx,ppc: Pixels per clock, Number of pixels to be transferred per pixel + clock. This is valid only if xlnx,vfb property is set to 1. + +- xlnx,axis-tdata-width: AXI Stream width, This denotes the AXI Stream width. + It depends on Data type chosen, Video Format Bridge enabled/disabled and + pixels per clock. If VFB is disabled then its value is either 0x20 (32 bit) + or 0x40(64 bit) width. + +- xlnx,video-format, xlnx,video-width: Video format and width, as defined in + video.txt. + +- port: Video port, using the DT bindings defined in ../video-interfaces.txt. + The CSI 2 Rx Subsystem has a two ports, one input port for connecting to + camera sensor and other is output port. + +- data-lanes: The number of data lanes through which CSI2 Rx Subsystem is + connected to the camera sensor as per video-interfaces.txt + +- clocks: List of phandles to AXI Lite, Video and 200 MHz DPHY clocks. + +- clock-names: Must contain "lite_aclk", "video_aclk" and "dphy_clk_200M" in + the same order as clocks listed in clocks property. + +Optional Properties + +- xlnx,en-vcx: When present, the max number of virtual channels can be 16 else 4. + +- reset-gpios: Optional specifier for a GPIO that asserts video_aresetn. + +- xlnx,dphy-present: Boolean to indicate whether DPHY register interface is + enabled or not. When this is present and compatible string is + xlnx,mipi-csi2-rx-subsystem-5.0 then DPHY offset is 0x1000 (4K) else + it is 0x1_0000 (64K). + +- xlnx,iic-present: Boolean to show whether subsystem's IIC is present or not. + This affects the base address of the DPHY. This can't be present when the + compatible string is "xlnx,mipi-csi2-rx-subsystem-4.1" or later. + +Example: + + csiss_1: csiss@a0020000 { + compatible = "xlnx,mipi-csi2-rx-subsystem-5.0"; + reg = <0x0 0xa0020000 0x0 0x20000>; + interrupt-parent = <&gic>; + interrupts = <0 95 4>; + + reset-gpios = <&gpio 81 1>; + xlnx,max-lanes = <0x4>; + xlnx,en-active-lanes; + xlnx,dphy-present; + xlnx,iic-present; + xlnx,vc = <0x4>; + xlnx,csi-pxl-format = "RAW8"; + xlnx,vfb; + xlnx,ppc = <0x4>; + xlnx,axis-tdata-width = <0x20>; + + clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk"; + clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + csiss_out: endpoint { + remote-endpoint = <&vcap_csiss_in>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + csiss_in: endpoint { + data-lanes = <1 2 3 4>; + /* MIPI CSI2 Camera handle */ + remote-endpoint = <&vs2016_out>; + }; + + }; + + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,mem2mem.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,mem2mem.txt new file mode 100644 index 000000000000..73af77faeb20 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,mem2mem.txt @@ -0,0 +1,25 @@ +Xilinx Video IP MEM2MEM Pipeline (XVIM2M) +---------------------------------------- + +Xilinx video IP mem2mem pipeline processes DMA transfers to achieve memory +copy from one physical memory to other. The data is copied by employing two +DMA transfers memory to device and device to memory transactions one after +the other. The DT node of the XVIM2M represents as a top level node of the +pipeline and defines mappings between DMAs. + +Required properties: + +- compatible: Must be "xlnx,mem2mem". + +- dmas, dma-names: List of two DMA specifier and identifier strings (as + defined in Documentation/devicetree/bindings/dma/dma.txt) per port. + Identifier string of one DMA channel should be "tx" and other should be + "rx". + +Example: + + video_m2m { + compatible = "xlnx,mem2mem"; + dmas = <&dma_1 0>, <&dma_2 0>; + dma-names = "tx", "rx"; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt new file mode 100644 index 000000000000..169338ed086d --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt @@ -0,0 +1,74 @@ + +Xilinx SDI Receiver Subsystem +------------------------------ + +The Xilinx SDI Rx Subsystem is used to capture SDI Video in upto 12G mode. +It outputs the video as an AXI4 Stream video data in YUV 422 10bpc mode. +The subsystem consists of the SDI Rx IP whose SDI native output is connected +to a SDI to Native conversion Bridge. The output of the Native bridge is +connected to a Native to AXI4S Bridge which generates the AXI4 Stream of +YUV422 or YUV420 10 bpc in dual pixel per clock. + +Required properties: + +- compatible: Must contain "xlnx,v-smpte-uhdsdi-rx-ss" + +- reg: Physical base address and length of the registers set for the device. + +- interrupts: Contains the interrupt line number. + +- interrupt-parent: phandle to interrupt controller. + +- xlnx,include-edh: Whether the EDH processor is enabled in design or not. + +- xlnx,line-rate: The maximum mode supported by the design. + +- clocks: Input clock specifier. Refer to common clock bindings. + +- clock-names: List of input clocks. + Required elements: "s_axi_aclk", "sdi_rx_clk", "video_out_clk" + +- port: Video port, using the DT bindings defined in ../video-interfaces.txt. + The SDI Rx subsystem has one port configured as output port. + +- xlnx,video-format, xlnx,video-width: Video format and width, as defined in + video.txt. Please note that the video format is fixed to either YUV422 or YUV420 + and the video-width is 10. + +Optional properties: + +- reset_gt-gpios: contains GPIO reset phandle for FMC init done pin in GT. + This pin is active low. +- xlnx,bpp: This denotes the bit depth as 10 or 12 based on IP configuration. + The default value is 10 for backward compatibility. + +Example: + v_smpte_uhdsdi_rx_ss: v_smpte_uhdsdi_rx_ss@80000000 { + compatible = "xlnx,v-smpte-uhdsdi-rx-ss"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + reg = <0x0 0x80000000 0x0 0x10000>; + xlnx,include-axilite = "true"; + xlnx,include-edh = "true"; + xlnx,include-vid-over-axi = "true"; + xlnx,line-rate = "12G_SDI_8DS"; + clocks = <&clk_1>, <&si570_1>, <&clk_2>; + clock-names = "s_axi_aclk", "sdi_rx_clk", "video_out_clk"; + reset_gt-gpios = <&axi_gpio_0 0 0 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <10>; + + sdirx_out: endpoint { + remote-endpoint = <&vcap_sdirx_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-axi4s-switch.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-axi4s-switch.txt new file mode 100644 index 000000000000..fb5ed47d959a --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-axi4s-switch.txt @@ -0,0 +1,141 @@ +Xilinx AXI4-Stream Switch +------------------------------- + +The AXI4-Stream Switch provides configurable routing between masters and slaves. +It supports up to 16 masters/sources and 16 slaves/sinks and two routing options. +There is atleast one slave/sink port and two master/source ports. + +The two routing options available are TDEST routing and control register routing. +The TDEST based routing uses design parameters and hence there no software control. +Each port is mapped as a pad and has its own format specified. + +Control register routing introduces an AXI4-Lite interface to configure the +routing table. There is one register for each of the master interfaces to +control each of the selectors. This routing mode requires that there is +precisely only one path between master and slave. When attempting to map the +same slave interface to multiple master interfaces, only the lowest master +interface is able to access the slave interface. +Here only the slave/sink ports have formats as master/source ports will inherit +the corresponding slave ports formats. A routing table is maintained in this case. + +Please refer to PG085 AXI4-Stream Infrastructure IP Suite v2.2 for more details. + +Required properties: + + - compatible: Must be "xlnx,axis-switch-1.1". + - xlnx,routing-mode: Can be 0 (TDEST routing) or 1 (Control reg routing) + - xlnx,num-si-slots: Number of slave / input ports. Min 1 Max 16 . + - xlnx,num-mi-slots: Number of master / output ports. Min 1 Max 16. + - ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + - clocks: Reference to the AXI Streaming clock feeding the ACLK and + AXI4 Lite control interface clock when control routing is enabled. + - clock-names: Must have "aclk". + +Optional properties: + - reg: Physical base address and length of the registers set for the device. + This is required only if xlnx,routing-mode is 1. + - clocks: Reference to AXI4 Lite control interface clock when routing-mode is 1. + - clock-names: "s_axi_ctl_clk" clock for AXI4 Lite interface when routing-mode is 1. + +Example: + +For TDEST routing, from 1 slave port to 4 master ports + + axis_switch_0: axis_switch@0 { + compatible = "xlnx,axis-switch-1.1"; + xlnx,routing-mode = <0x0>; + xlnx,num-si-slots = <0x1>; + xlnx,num-mi-slots = <0x4>; + clocks = <&vid_stream_clk>; + clock-names = "aclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + switch_in0: endpoint { + remote-endpoint = <&csirxss_out>; + }; + }; + port@1 { + reg = <1>; + switch_out0: endpoint { + remote-endpoint = <&vcap_csirxss0_in>; + }; + }; + port@2 { + reg = <2>; + switch_out1: endpoint { + remote-endpoint = <&vcap_csirxss1_in>; + }; + }; + port@3 { + reg = <3>; + switch_out2: endpoint { + remote-endpoint = <&vcap_csirxss2_in>; + }; + }; + port@4 { + reg = <4>; + switch_out3: endpoint { + remote-endpoint = <&vcap_csirxss3_in>; + }; + }; + }; + + }; + +For Control reg based routing, from 2 slave ports to 4 master ports + + axis_switch_0: axis_switch@a0050000 { + compatible = "xlnx,axis-switch-1.1"; + reg = <0x0 0xa0050000 0x0 0x1000>; + xlnx,routing-mode = <0x1>; + xlnx,num-si-slots = <0x2>; + xlnx,num-mi-slots = <0x4>; + clocks = <&vid_stream_clk>, <&misc_clk_0>; + clock-names = "aclk", "s_axi_ctl_clk; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + switch_in0: endpoint { + remote-endpoint = <&csirxss_out>; + }; + }; + port@1 { + reg = <1>; + switch_in1: endpoint { + remote-endpoint = <&tpg_out>; + }; + }; + port@2 { + reg = <2>; + switch_out0: endpoint { + remote-endpoint = <&vcap_csirxss0_in>; + }; + }; + port@3 { + reg = <3>; + switch_out1: endpoint { + remote-endpoint = <&vcap_csirxss1_in>; + }; + }; + port@4 { + reg = <4>; + switch_out2: endpoint { + remote-endpoint = <&vcap_csirxss2_in>; + }; + }; + port@5 { + reg = <5>; + switch_out3: endpoint { + remote-endpoint = <&vcap_csirxss3_in>; + }; + }; + }; + + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cfa.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cfa.txt new file mode 100644 index 000000000000..cdb0886cf975 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cfa.txt @@ -0,0 +1,58 @@ +Xilinx Color Filter Array (CFA) +------------------------------- + +Required properties: + +- compatible: Must be "xlnx,v-cfa-7.0". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the video core clock. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The cfa has an input port (0) and an output port (1). + +Required port properties: + +- xlnx,video-format: Must be SENSOR_MONO for the input port (0), and RBG for + the output port (1). + +- xlnx,video-width: Video width as defined in video.txt + +- xlnx, cfa-pattern: Must be one of "rggb", "grbg", "gbrg", and "bggr" for the + input port (0). Must not be specified for the output port (1). + +Example: + + cfa_0: cfa@400b0000 { + compatible = "xlnx,v-cfa-7.0"; + reg = <0x400b0000 0x10000>; + clocks = <&clkc 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_SENSOR_MONO>; + xlnx,video-width = <8>; + xlnx,cfa-pattern = "rggb"; + + cfa0_in: endpoint { + remote-endpoint = <&spc0_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_RBG>; + xlnx,video-width = <8>; + + cfa0_out: endpoint { + remote-endpoint = <&ccm0_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cresample.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cresample.txt new file mode 100644 index 000000000000..f404ee301272 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-cresample.txt @@ -0,0 +1,54 @@ +Xilinx Chroma Resampler (CRESAMPLE) +----------------------------------- + +Required properties: + +- compatible: Must be "xlnx,v-cresample-4.0". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the video core clock. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The cresample as han input port (0) and an output port (1). + +Required port properties: + +- xlnx,video-format: Must be one of YUV_444, YUV_422 or YUV_420 for the input + port (0), and one of YUV_422 or YUV_420 for the output port (1). + +- xlnx,video-width: Video width as defined in video.txt + +Example: + + cresample_0: cresample@40120000 { + compatible = "xlnx,v-cresample-4.0"; + reg = <0x40120000 0x10000>; + clocks = <&clkc 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_YUV_444>; + xlnx,video-width = <8>; + + cresample0_in: endpoint { + remote-endpoint = <&rgb2yuv0_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + cresample0_out: endpoint { + remote-endpoint = <&scaler0_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-demosaic.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-demosaic.txt new file mode 100644 index 000000000000..9b3aff413e0e --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-demosaic.txt @@ -0,0 +1,62 @@ +Xilinx Video Demosaic IP +----------------------------- +The Xilinx Video Demosaic IP is used to interface to a Bayer video source. + +The driver set default Sink Pad media bus format to RGGB. +The IP and driver only support RGB as its Source Pad media format. + +Required properties: + +- compatible: Must be "xlnx,v-demosaic". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the AXI Streaming clock feeding the Demosaic ap_clk. + +- xlnx,max-height: Maximum number of lines. Valid range is 64 to 4320. + +- xlnx,max-width: Maximum number of pixels in a line. Valid range is 64 to 8192. + +- reset-gpios: Specifier for GPIO that asserts Demosaic IP (AP_RST_N) reset. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + +Required port properties: + +- reg: This value represents the media pad of the V4L2 sub-device. + A Sink Pad is represented by reg = <0> + A Source Pad is represented by reg = <1> + +- xlnx,video-width: Video width as defined in video.txt + +Example: + demosaic_1: demosaic@a00b0000 { + compatible = "xlnx,v-demosaic"; + reg = <0x0 0xa00b0000 0x0 0x10000>; + clocks = <&vid_stream_clk>; + reset-gpios = <&gpio 87 1>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + xlnx,video-width = <8>; + + demosaic_in: endpoint { + remote-endpoint = <&tpg_out>; + }; + }; + + port@1 { + reg = <1>; + xlnx,video-width = <8>; + + demosaic_out: endpoint { + remote-endpoint = <&gamma_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-gamma-lut.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-gamma-lut.txt new file mode 100644 index 000000000000..7bd750f009b4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-gamma-lut.txt @@ -0,0 +1,63 @@ +Xilinx Video Gamma Correction IP +----------------------------------- +The Xilinx Video Gamma Correction IP is used to provide RGB gamma correction. +The IP provides a look up table for each R,G and B components. + +Required properties: + +- compatible: Must be "xlnx,v-gamma-lut". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the clock that drives the ap_clk + signal of Video Gamma Lookup. + +- xlnx,max-height: Maximum number of lines. Valid range is 64 to 4320. + +- xlnx,max-width: Maximum number of pixels in a line. Valid range is 64 to 8192. + +- reset-gpios: Specifier for a GPIO that asserts Gamma IP (AP_RST_N) reset + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The Gamma LUT IP has an input port (0) and an output port (1). + + +Required port properties: +- reg: This value represents the media pad of the V4L2 sub-device. + A Sink Pad is represented by reg = <0> + A Source Pad is represented by reg = <1> + +- xlnx,video-width: Video width as defined in video.txt. Can be either 8 or 10. + +Example: + + gamma_lut_1: gamma_lut_1@0xa0080000 { + compatible = "xlnx,v-gamma-lut"; + reg = <0x0 0xa0080000 0x0 0x10000>; + clocks = <&vid_stream_clk>; + reset-gpios = <&gpio 83 1>; + xlnx,max-height = <2160>; + xlnx,max-width = <3840>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + xlnx,video-width = <8>; + + gamma_in: endpoint { + remote-endpoint = <&demosaic_out>; + }; + }; + + port@1 { + reg = <1>; + xlnx,video-width = <8>; + + gamma_out: endpoint { + remote-endpoint = <&csc_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-hls.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-hls.txt new file mode 100644 index 000000000000..a6db3040565a --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-hls.txt @@ -0,0 +1,64 @@ +Xilinx High-Level Synthesis Core (HLS) +-------------------------------------- + +High-Level Synthesis cores are synthesized from a high-level function +description developed by the user. As such their functions vary widely, but +they all share a set of common characteristics that allow them to be described +by common bindings. + + +Required properties: + +- compatible: This property must contain "xlnx,v-hls" to indicate that the + core is compatible with the generic Xilinx HLS DT bindings. It can also + contain a more specific string to identify the HLS core implementation. The + value of those implementation-specific strings is out of scope for these DT + bindings. + +- reg: Physical base address and length of the registers sets for the device. + The HLS core has two registers sets, the first one contains the core + standard registers and the second one contains the custom user registers. + +- clocks: Reference to the video core clock. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The HLS core has one input port (0) and one output port (1). + +Required port properties: + +- xlnx,video-format: Video format as defined in video.txt. +- xlnx,video-width: Video width as defined in video.txt. + +Example: + + hls_0: hls@43c00000 { + compatible = "xlnx,v-hls-sobel", "xlnx,v-hls"; + reg = <0x43c00000 0x24>, <0x43c00024 0xa0>; + clocks = <&clkc 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + hls0_in: endpoint { + remote-endpoint = <&vdma_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + hls0_out: endpoint { + remote-endpoint = <&vdma_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-multi-scaler.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-multi-scaler.txt new file mode 100644 index 000000000000..3aea1f36a6ce --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-multi-scaler.txt @@ -0,0 +1,95 @@ +Xilinx mem2mem Multi Video Scaler (XM2MSC) +----------------------------------------- + +Required propertie(s): +- compatible : Should be "xlnx,v-multi-scaler-v1.0" +- clocks : Input clock specifier. Refer to common clk bindings. +- interrupt-parent : Interrupt controller the interrupt is routed through +- interrupts : Should contain MultiScaler interrupt +- reset-gpios : Should contain GPIO reset phandle +- reg : Physical base address and + length of the registers set for the device. +- xlnx,max-chan : Maximum number of supported scaling channels (1 - 8) +- xlnx,max-width : Maximum number of supported column/width (64 - 3840) +- xlnx,max-height : Maximum number of supported row/height (64 - 2160) +- xlnx,dma-addr-width : dma address width (either 32 or 64) +- xlnx,pixels-per-clock : pixels per clock set in IP (1, 2 or 4) +- xlnx,vid-formats : A list of strings indicating what video memory + formats the IP has been configured to support. + See VIDEO FORMATS table below and examples. +- xlnx,num-taps : The number of filter taps for scaling (6, 8, 10, 12) + +VIDEO FORMATS +The following table describes the legal string values to be used for +the xlnx,vid-formats property. To the left is the string value and the +column to the right describes the format. + +IP FORMAT DTS String Description +-------------|----------------|--------------------- +RGB8 bgr888 Packed RGB, 8 bits per component. + Every RGB pixel in memory is represented with + 24 bits. +RGBX8 xbgr8888 Packed RGB, 8 bits per component. Every RGB + pixel in memory is represented with 32 bits. + Bits[31:24] do not contain pixel information. +BGRX8 xrgb8888 Packed BGR, 8 bits per component. Every BGR + pixel in memory is represented with 32 bits. + Bits[31:24] do not contain pixel information. +RGBX10 xbgr2101010 Packed RGB, 10 bits per component. Every RGB + pixel is represented with 32 bits. Bits[31:30] + do not contain any pixel information. +YUV8 vuy888 Packed YUV 4:4:4, 8 bits per component. Every + YUV 4:4:4 pixel in memory is represented with + 24 bits. +YUVX8 xvuy8888 Packed YUV 4:4:4, 8 bits per component. + Every YUV 4:4:4 pixel in memory is represented + with 32 bits. Bits[31:24] do not contain pixel + information. +YUYV8 yuyv Packed YUV 4:2:2, 8 bits per component. Every + two YUV 4:2:2 pixels in memory are represented + with 32 bits. +UYVY8 uyvy Packed YUV 4:2:2, 8 bits per component. + Every two YUV 4:2:2 pixels in memory are + represented with 32 bits. +YUVX10 yuvx2101010 Packed YUV 4:4:4, 10 bits per component. + Every YUV 4:4:4 pixel is represented with 32 bits. + Bits[31:30] do not contain any pixel information. +Y8 y8 Packed Luma-Only, 8 bits per component. Every + luma-only pixel in memory is represented with + 8 bits. Y8 is presented as YUV 4:4:4 on the + AXI4-Stream interface. +Y10 y10 Packed Luma-Only, 10 bits per component. Every + three luma-only pixels in memory is represented + with 32 bits. Y10 is presented as YUV 4:4:4 on + the AXI4-Stream interface. +Y_UV8 nv16 Semi-planar YUV 4:2:2 with 8 bits per component. + Y and UV stored in separate planes. +Y_UV8_420 nv12 Semi-planar YUV 4:2:0 with 8 bits per component. + Y and UV stored in separate planes. +Y_UV10 xv20 Semi-planar YUV 4:2:2 with 10 bits per component. + Every 3 pixels is represented with 32 bits. + Bits[31:30] do not contain any pixel information. + Y and UV stored in separate planes. +Y_UV10_420 xv15 Semi-planar YUV 4:2:0 with 10 bits per component. + Every 3 pixels is represented with 32 bits. + Bits[31:30] do not contain any pixel information. + Y and UV stored in separate planes. + +Example + +v_multi_scaler_0: v_multi_scaler@a0000000 {\ + clocks = <&clk 71>; + compatible = "xlnx,v-multi-scaler-v1.0"; + interrupt-names = "interrupt"; + interrupt-parent = <&gic>; + interrupts = <0 89 4>; + reg = <0x0 0xa0000000 0x0 0x10000>; + xlnx,vid-formats = "bgr888","vuy888"; + reset-gpios = <&gpio 78 1>; + xlnx,max-chan = <0x01>; + xlnx,dma-addr-width = <0x20>; + xlnx,pixels-per-clock = /bits/ 8 <2>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + xlnx,num-taps = <6>; +}; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-remapper.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-remapper.txt new file mode 100644 index 000000000000..cda02cb97a21 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-remapper.txt @@ -0,0 +1,61 @@ +Xilinx Video Remapper +--------------------- + +The IP core remaps input pixel components to produce an output pixel with +less, more or the same number of components as the input pixel. + +Required properties: + +- compatible: Must be "xlnx,v-remapper". + +- clocks: Reference to the video core clock. + +- xlnx,video-width: Video pixel component width, as defined in video.txt. + +- #xlnx,s-components: Number of components per pixel at the input port + (between 1 and 4 inclusive). + +- #xlnx,m-components: Number of components per pixel at the output port + (between 1 and 4 inclusive). + +- xlnx,component-maps: Remapping configuration represented as an array of + integers. The array contains one entry per output component, in the low to + high order. Each entry corresponds to the zero-based position of the + corresponding input component, or the value 4 to drive a constant value on + the output component. For example, to remap RGB to BGR use <2 1 0>, and to + remap RBG to xRGB use <1 0 2 4>. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The remapper as an input port (0) and and output port (1). + +Example: RBG to xRGB remapper + + remapper_0: remapper { + compatible = "xlnx,v-remapper"; + + clocks = <&clkc 15>; + + xlnx,video-width = <8>; + + #xlnx,s-components = <3>; + #xlnx,m-components = <4>; + xlnx,component-maps = <1 0 2 4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + remap0_in: endpoint { + remote-endpoint = <&tpg0_out>; + }; + }; + port@1 { + reg = <1>; + remap0_out: endpoint { + remote-endpoint = <&sobel0_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-rgb2yuv.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-rgb2yuv.txt new file mode 100644 index 000000000000..ecd10fb31ac1 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-rgb2yuv.txt @@ -0,0 +1,54 @@ +Xilinx RGB to YUV (RGB2YUV) +--------------------------- + +Required properties: + +- compatible: Must be "xlnx,v-rgb2yuv-7.1". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the video core clock. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The rgb2yuv has an input port (0) and an output port (1). + +Required port properties: + +- xlnx,video-format: Must be RBG for the input port (0) and YUV_444 for the + output port (1). + +- xlnx,video-width: Video width as defined in video.txt + +Example: + + rgb2yuv_0: rgb2yuv@40100000 { + compatible = "xlnx,v-rgb2yuv-7.1"; + reg = <0x40100000 0x10000>; + clocks = <&clkc 15>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_RBG>; + xlnx,video-width = <8>; + + rgb2yuv0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_444>; + xlnx,video-width = <8>; + + rgb2yuv0_out: endpoint { + remote-endpoint = <&cresample0_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scaler.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scaler.txt new file mode 100644 index 000000000000..0bb9c405f5ae --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scaler.txt @@ -0,0 +1,75 @@ +Xilinx Scaler (SCALER) +------------------------------------ + +Required properties: + +- compatible: Must be "xlnx,v-scaler-8.1". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the video core clock. + +- xlnx,num-hori-taps, xlnx,num-vert-taps: The number of horizontal and vertical + taps for scaling filter(range: 2 - 12). + +- xlnx,max-num-phases: The maximum number of phases for scaling filter + (range: 2 - 64). + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The scaler has an input port (0) and an output port (1). + +Optional properties: + +- xlnx,separate-yc-coef: When set, this boolean property specifies that + the hardware uses separate coefficients for the luma and chroma filters. + Otherwise a single set of coefficients is shared for both. + +- xlnx,separate-hv-coef: When set, this boolean property specifies that + the hardware uses separate coefficients for the horizontal and vertical + filters. Otherwise a single set of coefficients is shared for both. + +Required port properties: + +- xlnx,video-format: Must be one of RBG, YUV_422, YUV_422 or YUV_420 for + both input port (0) and output port (1). The two formats must be identical. + +- xlnx,video-width: Video width as defined in video.txt + +Example: + + scaler_0: scaler@43c30000 { + compatible = "xlnx,v-scaler-8.1"; + reg = <0x43c30000 0x10000>; + clocks = <&clkc 15>; + + xlnx,num-hori-taps = <12>; + xlnx,num-vert-taps = <12>; + xlnx,max-num-phases = <4>; + xlnx,separate-hv-coef; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + scaler0_in: endpoint { + remote-endpoint = <&cresample0_out>; + }; + }; + port@1 { + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + scaler0_out: endpoint { + remote-endpoint = <&vcap0_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scd.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scd.txt new file mode 100644 index 000000000000..a05e9712c833 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-scd.txt @@ -0,0 +1,164 @@ +Xilinx Scene Change Detection IP (SCD) +-------------------------------------- + +The Xilinx Scene Change Detection IP contains two blocks: one IP block is used +for reading video frame data from memory to the device and the other IP block +is used for determining whether there is a scene change between current and the +previous frame. The IP supports YUV planar and semi-planar formats. IP only +needs luma frame to determine the scene change event. The IP supports memory +based model, which means that it will accept a dma buffer address and perform +MEM2DEV transfer followed by statistical based image processing and give the +data back to application if scene change detection is present or not. + +Another version of scene change detection IP which supports streaming model, +which means that IP can be inserted in a capture pipeline. For example, +"hdmirx -> streaming-scd -> fb_wr" is a typical capture pipeline where +streaming SCD can be embedded. The IP accespts the AXI video data and perform +histogram based statistical analysis to detect scene change. The IP supports +single channel. + +Required properties: + +- compatible: Should be "xlnx,v-scd" + +- reg: Physical base address and length of the registers set for the device + +- clocks: Reference to the video core clock. + +- reset-gpios: Specifier for a GPIO that assert SCD (AP_RST_N) reset. + +- xlnx,memory-based: This is to differentiate between memory based and + streaming based IP. The value is 1 for memory based and 0 for streaming + based IPs. + +- xlnx,numstreams: Maximum active streams IP can support is 8 and this is based + on the design. + +- xlnx,addrwidth: Size of dma address pointer in IP (either 32 or 64) + +- subdev: Each channel will have its own subdev node. Each subdev will have its + sink port. + +- port: Video port, using the DT bindings defined in ../video-interfaces.txt. + +Example: + +1. Memory based device tree + +The following example shows how the device tree would look like for a memory +based design where 8 streams are enabled. + + scd: scenechange@a0100000 { + compatible = "xlnx,v-scd"; + reg = <0x0 0xa0100000 0x0 0x1fff>; + clocks = <&misc_clk_0>; + interrupt-parent = <&gic>; + interrupts = <0 90 4>; + reset-gpios = <&gpio 94 1>; + + xlnx,memory-based; + xlnx,numstreams = <8>; + xlnx,addrwidth = <0x20>; + + #address-cells = <1>; + #size-cells = <0>; + #dma-cells = <1>; + + subdev@0 { + port@0 { + reg = <0>; + scd_in0: endpoint { + remote-endpoint = <&vcap0_out0>; + }; + }; + }; + subdev@1 { + port@0 { + reg = <0>; + scd_in1: endpoint { + remote-endpoint = <&vcap0_out1>; + }; + }; + }; + subdev@2 { + port@0 { + reg = <0>; + scd_in2: endpoint { + remote-endpoint = <&vcap0_out2>; + }; + }; + }; + subdev@3 { + port@0 { + reg = <0>; + scd_in3: endpoint { + remote-endpoint = <&vcap0_out3>; + }; + }; + }; + subdev@4 { + port@0 { + reg = <0>; + scd_in4: endpoint { + remote-endpoint = <&vcap0_out4>; + }; + }; + }; + subdev@5 { + port@0 { + reg = <0>; + scd_in5: endpoint { + remote-endpoint = <&vcap0_out5>; + }; + }; + }; + subdev@6 { + port@0 { + reg = <0>; + scd_in6: endpoint { + remote-endpoint = <&vcap0_out6>; + }; + }; + }; + subdev@7 { + port@0 { + reg = <0>; + scd_in7: endpoint { + remote-endpoint = <&vcap0_out7>; + }; + }; + }; + }; + +2. Streaming based device tree + +The following example shows how the device tree would look like for a streaming +based design. + + scd: scenechange@a0280000 { + compatible = "xlnx,v-scd"; + reg = <0x0 0xa0280000 0x0 0x1fff>; + clocks = <&clk 72>; + interrupt-parent = <&gic>; + interrupts = <0 111 4>; + reset-gpios = <&gpio 100 1>; + #address-cells = <1>; + #size-cells = <0>; + xlnx,numstreams = <1>; + + scd { + port@0 { + reg = <0x0>; + scd_in0: endpoint { + remote-endpoint = <&vpss_scaler_out>; + }; + }; + + port@1 { + reg = <0x1>; + scd_out0: endpoint { + remote-endpoint = <&vcap_hdmi_in_1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-switch.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-switch.txt new file mode 100644 index 000000000000..91dc3af4a2b6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-switch.txt @@ -0,0 +1,55 @@ +Xilinx Video Switch +------------------- + +Required properties: + + - compatible: Must be "xlnx,v-switch-1.0". + + - reg: Physical base address and length of the registers set for the device. + + - clocks: Reference to the video core clock. + + - #xlnx,inputs: Number of input ports + - #xlnx,outputs: Number of outputs ports + + - ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + +Example: + + switch: switch@43c10000 { + compatible = "xlnx,v-switch-1.0"; + reg = <0x43c10000 0x10000>; + clocks = <&clkc 15>; + + #xlnx,inputs = <2>; + #xlnx,outputs = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + switch_in0: endpoint { + remote-endpoint = <&tpg_out>; + }; + }; + port@1 { + reg = <1>; + switch_in1: endpoint { + remote-endpoint = <&cresample0_out>; + }; + }; + port@2 { + reg = <2>; + switch_out0: endpoint { + remote-endpoint = <&scaler0_in>; + }; + }; + port@3 { + reg = <3>; + switch_out1: endpoint { + remote-endpoint = <&vcap0_in1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt index 439351ab2a79..4b2126a78a3f 100644 --- a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-tpg.txt @@ -6,7 +6,8 @@ Required properties: - compatible: Must contain at least one of "xlnx,v-tpg-5.0" (TPG version 5.0) - "xlnx,v-tpg-6.0" (TPG version 6.0) + "xlnx,v-tpg-7.0" (TPG version 7.0) + "xlnx,v-tpg-8.0" (TPG version 8.0) TPG versions backward-compatible with previous versions should list all compatible versions in the newer to older order. @@ -23,6 +24,8 @@ Required properties: Optional properties: +- xlnx,ppc: Pixels per clock. Valid values are 1, 2, 4 or 8. + - xlnx,vtc: A phandle referencing the Video Timing Controller that generates video timings for the TPG test patterns. @@ -30,16 +33,26 @@ Optional properties: input. The GPIO active level corresponds to the selection of VTC-generated video timings. +- reset-gpios: Specifier for a GPIO that assert TPG (AP_RST_N) reset. + This property is mandatory for TPG v7.0 and above. + +- xlnx,max-height: Maximum number of lines. + This property is mandatory for TPG v8.0. Value ranges from 64 to 7760. + +- xlnx,max-width: Maximum number of pixels in a line. + This property is mandatory for TPG v8.0. Value ranges from 64 to 10328. + The xlnx,vtc and timing-gpios properties are mandatory when the TPG is synthesized with two ports and forbidden when synthesized with one port. Example: tpg_0: tpg@40050000 { - compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0"; + compatible = "xlnx,v-tpg-5.0"; reg = <0x40050000 0x10000>; clocks = <&clkc 15>; + xlnx,ppc = <2>; xlnx,vtc = <&vtc_3>; timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-csc.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-csc.txt new file mode 100644 index 000000000000..b3627af85e6e --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-csc.txt @@ -0,0 +1,66 @@ +Xilinx VPSS Color Space Converter (CSC) +----------------------------------------- +The Xilinx VPSS Color Space Converter (CSC) is a Video IP that supports +color space conversion from RGB input to YUV output. + +Required properties: + +- compatible: Must be "xlnx,v-vpss-csc". + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the clock that drives the ap_clk signal. + +- xlnx,max-height: Maximum number of lines. + Valid range from 64 to 4320. + +- xlnx,max-width: Maximum number of pixels in a line. + Valid range from 64 to 8192. + +- reset-gpios: Specifier for a GPIO that assert VPSS CSC (AP_RST_N) reset. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The scaler has an input port (0) and an output port (1). + +Required port properties: + +- xlnx,video-format: Must be XVIP_VF_RBG, XVIP_VF_YUV_444 or XVIP_VF_YUV_422 + for input port (0) and XVIP_VF_RBG, XVIP_VF_YUV_444 or XVIP_VF_YUV_422 + for output port (1). See <dt-bindings/media/xilinx-vip.h> for more details. + +- xlnx,video-width: Video width as defined in video.txt. Must be either 8 or 10. + +Example: + csc_1:csc@a0040000 { + compatible = "xlnx,v-vpss-csc"; + reg = <0x0 0xa0040000 0x0 0x10000>; + clocks = <&vid_stream_clk>; + reset-gpios = <&gpio 84 1>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + /* Sink Pad */ + port@0 { + reg = <0>; + xlnx,video-format = <XVIP_VF_RBG>; + xlnx,video-width = <8>; + + csc_in: endpoint { + remote-endpoint = <&gamma_out>; + }; + }; + /* Source Pad */ + port@1 { + reg = <1>; + xlnx,video-format = <XVIP_VF_RBG>; + xlnx,video-width = <8>; + + csc_out: endpoint { + remote-endpoint = <&scalar_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-scaler.txt b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-scaler.txt new file mode 100644 index 000000000000..05ca0cb33cad --- /dev/null +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,v-vpss-scaler.txt @@ -0,0 +1,93 @@ + Xilinx VPSS Scaler +------------------------ + +Required properties: + +- compatible: Must be "xlnx,v-vpss-scaler-2.2" or "xlnx,v-vpss-scaler-1.0". + The older string "xlnx,v-vpss-scaler" will be deprecated. + +- reg: Physical base address and length of the registers set for the device. + +- clocks: Reference to the AXI Streaming clock feeding the VPSS Scaler AP_CLK + and AXI4 Lite control interface clock. + +- clock-names: Must contain "aclk_axis" and "aclk_ctrl" in the same order as + clocks listed in clocks property. + +- xlnx,num-hori-taps, xlnx,num-vert-taps: The number of horizontal and vertical + taps for scaling filter(range: 2,4,6,8,10,12). + + A value of 2 represents bilinear filters. A value of 4 represents bicubic. + Values 6,8,10,12 represent polyphase filters. + +- xlnx,pix-per-clk : The pixels per clock property of the IP + +- reset-gpios: Specifier for a GPIO that assert for VPSS Scaler reset. + This property is mandatory for the Scaler + +- xlnx,max-height: Maximum number of lines. + Valid range from 64 to 4320. + +- xlnx,max-width: Maximum number of pixels in a line. + Valid range from 64 to 8192. + +- ports: Video ports, using the DT bindings defined in ../video-interfaces.txt. + The scaler has an input port (0) and an output port (1). + +Required port properties: + +- xlnx,video-format: Must be one of XVIP_VF_RBG or XVIP_VF_YUV_422 for + input port (0) and must be XVIP_VF_RBG or XVIP_VF_YUV_422 or for + the output port (1). + See <dt-bindings/media/xilinx-vip.h> for more details. + +- reg: This value represents the media pad of the V4L2 sub-device. + A Sink Pad is represented by reg = <0> + A Source Pad is represented by reg = <1> + +- xlnx,video-width: Video width as defined in video.txt + +Example: + + scaler_1:scaler@a0000000 { + compatible = "xlnx,v-vpss-scaler-1.0"; + reg = <0x0 0xa0000000 0x0 0x40000>; + clocks = <&vid_stream_clk>, <&misc_clk_2>; + clock-names = "aclk_axis", "aclk_ctrl"; + xlnx,num-hori-taps = <8>; + xlnx,num-vert-taps = <8>; + xlnx,pix-per-clk = <2>; + reset-gpios = <&gpio 87 1>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + /* Sink Pad */ + reg = <0>; + + xlnx,video-format = <XVIP_VF_RBG>; + xlnx,video-width = <8>; + + scaler_in: endpoint { + remote-endpoint = <&csc_out>; + }; + }; + + port@1 { + /* Source Pad */ + reg = <1>; + + xlnx,video-format = <XVIP_VF_YUV_422>; + xlnx,video-width = <8>; + + scaler_out: endpoint { + remote-endpoint = <&vcap_tpg_in>; + }; + }; + }; + + }; |