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Diffstat (limited to 'Documentation/devicetree/bindings/display')
9 files changed, 560 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/xlnx/bridge.txt b/Documentation/devicetree/bindings/display/xlnx/bridge.txt new file mode 100644 index 000000000000..c5f7c0a1dea0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/bridge.txt @@ -0,0 +1,29 @@ +Xilinx DRM bridge +----------------- + +The Xilinx DRM provides the interface layer called Xilinx bridge to bridge +multiple components with a series of functions. It models a simple +unidirectional communication, single client -> single bridge. The client +is not limited to DRM compatible drivers, but can be any subsystem driver, +but the client driver should call the bridge functions explicitly. + +Provider +-------- + +The bridge provider should assign a corresponding of_node to struct xlnx_bridge. +For example, if its own node is used, + + provider_node: provider_node { + }; + + bridge.of_node = provider_device->of_node; + +Client +------ + +The bridge client should have a phandle to the bridge device node. The bridge +device node should be passed to get a bridge instance, + + client_node { + xlnx,bridge = <&provider_node>; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt new file mode 100644 index 000000000000..55508167e606 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi.txt @@ -0,0 +1,73 @@ +Device-Tree bindings for Xilinx MIPI DSI Tx IP core + +The IP core supports transmission of video data in MIPI DSI protocol. + +Required properties: + - compatible: Should be "xlnx,dsi". + + - reg: Base address and size of the IP core. + + - xlnx,dsi-datatype: Color format. The value should be one of "MIPI_DSI_FMT_RGB888", + "MIPI_DSI_FMT_RGB666", "MIPI_DSI_FMT_RGB666_PACKED" or "MIPI_DSI_FMT_RGB565". + + - simple_panel: The subnode for connected panel. This represents the + DSI peripheral connected to the DSI host node. Please refer to + Documentation/devicetree/bindings/display/mipi-dsi-bus.txt. The + simple-panel driver has auo,b101uan01 panel timing parameters added along + with other existing panels. DSI driver derive the required Tx IP controller + timing values from the panel timing parameters. + + - port: Logical block can be used / connected independently with + external device. In the display controller port nodes, topology + for entire pipeline should be described using the DT bindings defined in + Documentation/devicetree/bindings/graph.txt. + + - xlnx,dsi-num-lanes: Possible number of DSI lanes for the Tx controller. + The values should be 1, 2, 3 or 4. Based on xlnx,dsi-num-lanes and + line rate for the MIPI D-PHY core in Mbps, the AXI4-stream received by + Xilinx MIPI DSI Tx IP core adds markers as per DSI protocol and the packet + thus framed is convered to serial data by MIPI D-PHY core. Please refer + Xilinx pg238 for more details. This value should be equal to the number + of lanes supported by the connected DSI panel. Panel has to support this + value or has to be programmed to the same value that DSI Tx controller is + configured to. + + - clocks: List of phandles to Video and 200Mhz DPHY clocks. + + - clock-names: Must contain "s_axis_aclk" and "dphy_clk_200M" in same order as + clocks listed in clocks property. + +Required simple_panel properties: + - compatible: Value should be one of the panel names in + Documentation/devicetree/bindings/display/panel/. e.g. "auo,b101uan01". + For available panel compatible strings, please refer to bindings in + Documentation/devicetree/bindings/display/panel/ + +Optional properties: + - xlnx,vpss: vpss phandle + This handle is required only when VPSS is connected to DSI as bridge. + +Example: + +#include <dt-bindings/drm/mipi-dsi.h> + mipi_dsi_tx_subsystem@80000000 { + compatible = "xlnx,dsi"; + reg = <0x0 0x80000000 0x0 0x10000>; + xlnx,dsi-num-lanes = <4>; + xlnx,dsi-data-type = <MIPI_DSI_FMT_RGB888>; + #address-cells = <1>; + #size-cells = <0>; + xlnx,vpss = <&v_proc_ss_0>; + clock-names = "dphy_clk_200M", "s_axis_aclk"; + clocks = <&misc_clk_0>, <&misc_clk_1>; + encoder_dsi_port: port@0 { + reg = <0>; + dsi_encoder: endpoint { + remote-endpoint = <&xyz_port>; + }; + }; + simple_panel: simple-panel@0 { + compatible = "auo,b101uan01"; + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,mixer.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,mixer.txt new file mode 100644 index 000000000000..20f4cec27175 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,mixer.txt @@ -0,0 +1,163 @@ +Device-Tree bindings for Xilinx Video Mixer IP core + +The IP core provides a flexible video processing block for alpha blending +and compositing multiple video and/or graphics layers. +Support for up to sixteen layers based on IP version, with an optional logo +layer, using a combination of video inputs from either frame buffer or +streaming video cores (through AXI4-Stream interfaces) is provided. +The Video Mixer always has one streaming input layer, known as master layer. + +Required properties: + - compatible: Must contain atleast one of + "xlnx,mixer-4.0" (MIXER 4.0 version) + "xlnx,mixer-3.0" (MIXER 3.0 version) + - reg: Base address and size of the IP core. + - interrupts: Interrupt number. + - interrupts-parent: phandle for interrupt controller. + - reset-gpio: gpio to reset the mixer IP + - xlnx,dma-addr-width: dma address width, valid values are 32 and 64 + - xlnx,bpc: bits per component for mixer + - xlnx,ppc: pixel per clock for mixer + - xlnx,num-layers: Total number of layers (excluding logo) + Value ranges from 1-9 for compatible string xlnx,mixer-3.0 and + Value ranges from 1-17 for comptaible string xlnx,mixer-4.0 + - layer_[x]: node for [x] layer + - xlnx,layer-id: layer identifier number + - xlnx,vformat: video format for layer. See list of supported formats below. + - xlnx,layer-max-width: max layer width, mandatory for master layer + for overlay layers if scaling is alowed then this is mandatory otherwise + not required for overlay layers + - xlnx,layer-max-height: max layer height, mandatory for master layer + Not required for overlay layers + - xlnx,layer-primary: denotes the primary layer, should be mentioned in node + of layer which is expected to be constructing the primary plane + +Optional properties: + - dmas: dma attach to layer, mandatory for master layer + for rest other layers its optional + - dma-names: Should be "dma0", for more details on DMA identifier string + refer Documentation/devicetree/bindings/dma/dma.txt + - xlnx,layer-streaming: denotes layer can be streaming, + mandatory for master layer. Streaming layers need external dma, where + as non streaming layers read directly from memory. + - xlnx,layer-alpha: denotes layer can do alpha compositing + - xlnx,layer-scale: denotes layer can be scale to 2x and 4x + - xlnx,logo-layer: denotes logo layer is enable + - logo: logo layer + - xlnx,bridge: phandle to bridge node. + This handle is required only when VTC is connected as bridge. + +Supported Formats: + Mixer IP Format Driver supported Format String + BGR888 "RG24" + RGB888 "BG24" + XBGR2101010 "XB30" + XRGB8888 "XR24" + RGBA8888 "RA24" + ABGR8888 "AB24" + ARGB8888 "AR24" + XBGR8888 "XB24" + YUYV "YUYV" + UYVY "UYVY" + AYUV "AYUV" + NV12 "NV12" + NV16 "NV16" + Y8 "GREY" + Y10 "Y10 " (Note: Space included) + XVUY2101010 "XV30" + VUY888 "VU24" + XVUY8888 "XV24" + XV15 "XV15" + XV20 "XV20" +Note : Format strings are case sensitive. + +Example: + v_mix_0: v_mix@80100000 { + compatible = "xlnx,mixer-3.0"; + interrupt-parent = <&gic>; + interrupts = <0 93 4>; + reg = <0x0 0x80100000 0x0 0x80000>; + + xlnx,dma-addr-width=<32>; + reset-gpios = <&gpio 1 1>; + + xlnx,bpc = <8>; + xlnx,ppc = <2>; + xlnx,num-layers = <8>; + xlnx,logo-layer; + xlnx,bridge = <&v_tc_0>; + + mixer_port: mixer_port@0 { + reg = <0>; + mixer_crtc: endpoint { + remote-endpoint = <&sdi_encoder>; + }; + }; + xv_mix_master: layer_0 { + xlnx,layer-id = <0>; + xlnx,vformat = "YUYV"; + xlnx,layer-max-width = <4096>; + xlnx,layer-height = <2160>; + dmas = <&axi_vdma_0 0>; + dma-names = "dma0"; + xlnx,layer-streaming; + xlnx,layer-primary; + }; + xv_mix_overlay_1: layer_1 { + xlnx,layer-id = <1>; + xlnx,vformat = "NV16"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_2: layer_2 { + xlnx,layer-id = <2>; + xlnx,vformat = "YUYV"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_3: layer_3 { + xlnx,layer-id = <3>; + xlnx,vformat = "AYUV"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_4: layer_4 { + xlnx,layer-id = <4>; + xlnx,vformat = "GREY"; + dmas = <&scaler_v_frmbuf_rd_0 0>; + dma-names = "dma0"; + xlnx,layer-streaming; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_5: layer_5 { + xlnx,layer-id = <5>; + xlnx,vformat = "AB24"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_6: layer_6 { + xlnx,layer-id = <6>; + xlnx,vformat = "XB24"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_overlay_7: layer_7 { + xlnx,layer-id = <7>; + xlnx,vformat = "BG24"; + xlnx,layer-alpha; + xlnx,layer-scale; + xlnx,layer-max-width=<1920>; + }; + xv_mix_logo: logo { + xlnx,layer-id = <8>; + xlnx,logo-height = <64>; + xlnx,logo-width = <64>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,pl-disp.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,pl-disp.txt new file mode 100644 index 000000000000..c6034bffc64a --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,pl-disp.txt @@ -0,0 +1,41 @@ +Xilinx PL Display driver +------------------------ + +Pl_Display is a logical device to provide completeness to xilinx display +pipeline. This is a software driver for providing drm components crtc +and plane for various IPs using xilinx display pipelines. + +A linear pipeline with multiple blocks: +DMA --> PL_Display --> SDI + +Required properties: + +- compatible: Must be "xlnx,pl-disp" +- dmas: dma attach to pipeline +- dma-names: names for dma +- xlnx,vformat: video format for layer +- port: Logical block can be used / connected independently with + external device. In the display controller port nodes, topology + for entire pipeline should be described using the DT bindings defined in + Documentation/devicetree/bindings/graph.txt. +- reg: Base address and size of device + +Optional properties: + - xlnx,bridge: bridge phandle + This handle is required only when VTC is connected as bridge. + +Example: + + drm-pl-disp-drv { + compatible = "xlnx,pl-disp"; + dmas = <&axi_vdma_0 0>; + dma-names = "dma0"; + xlnx,vformat = "YUYV"; + xlnx,bridge = <&v_tc_0>; + pl_disp_port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&sdi_port>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,sdi-tx.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,sdi-tx.txt new file mode 100644 index 000000000000..971ac5304761 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,sdi-tx.txt @@ -0,0 +1,54 @@ +Device-Tree bindings for Xilinx SDI Tx subsystem + +The IP core supports transmission of video data in SDI Tx protocol + +Required properties: + - compatible: Should be "xlnx,sdi-tx". + - interrupts: Interrupt number. + - interrupts-parent: phandle for interrupt controller. + - reg: Base address and size of the IP core. + - port: Logical block can be used / connected independently with + external device. In the display controller port nodes, topology + for entire pipeline should be described using the DT bindings defined in + Documentation/devicetree/bindings/graph.txt. + Minimum one port is required. At max, 2 ports are present. + The reg index for AXI4 stream port is 0 and for ancillary data is 1. + - clocks: List of phandles to AXI Lite, Video and SDI Tx Clock + - clock-names: Must contain "s_axi_aclk", "video_in_clk" and "sdi_tx_clk" + in same order as clocks listed in clocks property. + +Optional properties: + - xlnx,vpss: vpss phandle + This handle is required only when VPSS is connected to SDI as bridge. + - xlnx,tx-insert-c-str-st352: Insert ST352 payload in Chroma stream. + +Example: + + sdi_tx_subsystem@80000000 { + compatible = "xlnx,sdi-tx"; + reg = <0x0 0x80000000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 90 4>; + #address-cells = <1>; + #size-cells = <0>; + xlnx,vpss = <&v_proc_ss_0>; + clock-names = "s_axi_aclk", "video_in_clk", "sdi_tx_clk"; + clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>; + ports { + #address-cells = <1>; + #size-cells = <0>; + encoder_sdi_port: port@0 { + reg = <0>; + sdi_encoder: endpoint { + remote-endpoint = <&pl_disp_crtc>; + }; + }; + + sdi_audio_port: port@1 { + reg = <1>; + sdi_audio_sink_port: endpoint { + remote-endpoint = <&sditx_audio_embed_src_port>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-csc.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-csc.txt new file mode 100644 index 000000000000..cf80d185d429 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-csc.txt @@ -0,0 +1,35 @@ +Xllinx VPSS Color Space Converter +----------------------------------------- +The Xilinx VPSS Color Space Converter is a Video IP that supports +color space conversion from RGB to YUV 444/422/420 and vice versa. + +Required properties: + +- compatible: Must be "xlnx,vpss-csc". + +- reg: Physical base address and length of registers set for the device. + +- xlnx,video-width: This property qualifies the video format with sample + width expressed as a number of bits per pixel component. Supported video + width values are 8/10/12/16. + +-reset-gpios: GPIO specifier to assert/de-assert the reset line. + +- clocks: phandle to IP clock. + +- xlnx,max-width: Maximum number of pixels in a line. + Valid range from 64 to 8192. + +- xlnx,max-height: Maximum number of lines in a frame. + Valid range from 64 to 4320. + +Example: + csc@a0040000 { + compatible = "xlnx,vpss-csc"; + reg = <0x0 0xa0040000 0x0 0x10000>; + reset-gpios = <&gpio 0x0 GPIO_ACTIVE_LOW>; + xlnx,video-width = <8>; + clocks = <&misc_clk_0>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + } diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-scaler.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-scaler.txt new file mode 100644 index 000000000000..8920b81e2779 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,vpss-scaler.txt @@ -0,0 +1,51 @@ +Xilinx VPSS Scaler +------------------ +The Xilinx VPSS Scaler is a Video IP that supports up scaling, +down scaling and no scaling functionailty. This supports custom +resolution values between 0 to 4096. + +Required properties: + +- compatible: Must be "xlnx,vpss-scaler". + +- reg: Physical base address and length of registers set for the device. + +- xlnx,num-hori-taps: The number of horizontal taps for scaling filter + supported tap values are 2/4/6/8/10/12. + +- xlnx,num-vert-taps: The number of vertical taps for scaling filter + supported tap values are 2/4/6/8/10/12. + + A value of 2 represents bilinear filters. A value of 4 represents bicubic. + Values 6, 8, 10, 12 represent polyphase filters. + +- xlnx,pix-per-clk : The pixels per clock property of the IP. + supported values are 1 and 2. + +- reset-gpios: GPIO specifier to assert/de-assert the reset line. + +- clocks: List of phandles to AXI Lite and Video clock + +- clock-names: Must contain "aclk_ctrl" and "aclk_axis" in same order as clocks + listed in clocks property. + +- xlnx,max-width: Maximum number of pixels in a line. + Valid range from 64 to 8192. + +- xlnx,max-height: Maximum number of lines in a frame. + Valid range from 64 to 4320. + +Example: + scaler@a0040000 { + compatible = "xlnx,vpss-scaler"; + reg = <0x0 0xa0000000 0x0 0x40000>; + reset-gpios = <&gpio 0x0 GPIO_ACTIVE_LOW>; + xlnx,num-hori-taps = <8>; + xlnx,num-vert-taps = <8>; + xlnx,pix-per-clk = <2>; + clock-names = "aclk_ctrl", "aclk_axis"; + clocks = <&misc_clk_0>, <&misc_clk_1>; + xlnx,max-width = <3840>; + xlnx,max-height = <2160>; + } + diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.txt new file mode 100644 index 000000000000..6a4d5bcc5e59 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.txt @@ -0,0 +1,32 @@ +Device-Tree bindings for Xilinx Video Timing Controller(VTC) + +Xilinx VTC is a general purpose video timing generator and detector. +The input side of this core automatically detects horizontal and +vertical synchronization, pulses, polarity, blanking timing and active pixels. +While on the output, it generates the horizontal and vertical blanking and +synchronization pulses used with a standard video system including support +for programmable pulse polarity. + +The core is commonly used with Video in to AXI4-Stream core to detect the +format and timing of incoming video data or with AXI4-Stream to Video out core +to generate outgoing video timing for downstream sinks like a video monitor. + +For details please refer to +https://www.xilinx.com/support/documentation/ip_documentation/v_tc/v6_1/pg016_v_tc.pdf + +Required properties: + - compatible: value should be "xlnx,bridge-v-tc-6.1" + - reg: base address and size of the VTC IP + - xlnx,pixels-per-clock: Pixels per clock of the stream. Can be 1, 2 or 4. + - clocks: List of phandles for AXI Lite and Video Clock + - clock-names: Must contain "s_axi_aclk" and "clk" in same order as clocks listed + in clocks property. + +Example: + v_tc_0: v_tc@80030000 { + compatible = "xlnx,bridge-v-tc-6.1"; + reg = <0x0 0x80030000 0x0 0x10000>; + xlnx,pixels-per-clock = <2>; + clock-names = "s_axi_aclk", "clk"; + clocks = <&misc_clk_0>, <&misc_clk_1>; + }; diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt new file mode 100644 index 000000000000..46d0c7671ee5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.txt @@ -0,0 +1,82 @@ +Xilinx ZynqMP DisplayPort subsystem +----------------------------------- + +Required properties: + +- compatible: Must be "xlnx,zynqmp-dpsub-1.7". + +- reg: Physical base address and length of the registers set for the device. +- reg-names: Must be "dp", "blend", "av_buf", and "aud" to map logical register + partitions. + +- interrupts: Interrupt number. +- interrupts-parent: phandle for interrupt controller. + +- clocks: phandles for axi, audio, non-live video, and live video clocks. + axi clock is required. Audio clock is optional. If not present, audio will + be disabled. One of non-live or live video clock should be present. +- clock-names: The identification strings are required. "aclk" for axi clock. + "dp_aud_clk" for audio clock. "dp_vtc_pixel_clk_in" for non-live video clock. + "dp_live_video_in_clk" for live video clock (clock from programmable logic). + +- phys: phandles for phy specifier. The number of lanes is configurable + between 1 and 2. The number of phandles should be 1 or 2. +- phy-names: The identifier strings. "dp-phy" followed by index, 0 or 1. + For single lane, only "dp-phy0" is required. For dual lane, both "dp-phy0" + and "dp-phy1" are required where "dp-phy0" is the primary lane. + +- power-domains: phandle for the corresponding power domain + +- vid-layer, gfx-layer: Required to represent available layers + +Required layer properties + +- dmas: phandles for DMA channels as defined in + Documentation/devicetree/bindings/dma/dma.txt. +- dma-names: The identifier strings are required. "gfx0" for graphics layer + dma channel. "vid" followed by index (0 - 2) for video layer dma channels. + +Optional child node + +- The driver populates any child device node in this node. This can be used, + for example, to populate the sound device from the DisplayPort subsystem + driver. + +Example: + zynqmp-display-subsystem@fd4a0000 { + compatible = "xlnx,zynqmp-dpsub-1.7"; + reg = <0x0 0xfd4a0000 0x0 0x1000>, + <0x0 0xfd4aa000 0x0 0x1000>, + <0x0 0xfd4ab000 0x0 0x1000>, + <0x0 0xfd4ac000 0x0 0x1000>; + reg-names = "dp", "blend", "av_buf", "aud"; + interrupts = <0 119 4>; + interrupt-parent = <&gic>; + + clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk"; + clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>; + + phys = <&lane1>, <&lane0>; + phy-names = "dp-phy0", "dp-phy1"; + + power-domains = <&pd_dp>; + + vid-layer { + dma-names = "vid0", "vid1", "vid2"; + dmas = <&xlnx_dpdma 0>, + <&xlnx_dpdma 1>, + <&xlnx_dpdma 2>; + }; + + gfx-layer { + dma-names = "gfx0"; + dmas = <&xlnx_dpdma 3>; + }; + + dma-names = "vid0", "vid1", "vid2", "gfx0"; + dmas = <&xlnx_dpdma 0>, + <&xlnx_dpdma 1>, + <&xlnx_dpdma 2>, + <&xlnx_dpdma 3>; + }; +}; |