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path: root/drivers/net/hamradio/baycom_ser_fdx.c
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/*****************************************************************************/

/*
 *	baycom_ser_fdx.c  -- baycom ser12 fullduplex radio modem driver.
 *
 *	Copyright (C) 1996-2000  Thomas Sailer (sailer@ife.ee.ethz.ch)
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	This program is distributed in the hope that it will be useful,
 *	but WITHOUT ANY WARRANTY; without even the implied warranty of
 *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *	GNU General Public License for more details.
 *
 *	You should have received a copy of the GNU General Public License
 *	along with this program; if not, write to the Free Software
 *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *  Please note that the GPL allows you to use the driver, NOT the radio.
 *  In order to use the radio, you need a license from the communications
 *  authority of your country.
 *
 *
 *  Supported modems
 *
 *  ser12:  This is a very simple 1200 baud AFSK modem. The modem consists only
 *          of a modulator/demodulator chip, usually a TI TCM3105. The computer
 *          is responsible for regenerating the receiver bit clock, as well as
 *          for handling the HDLC protocol. The modem connects to a serial port,
 *          hence the name. Since the serial port is not used as an async serial
 *          port, the kernel driver for serial ports cannot be used, and this
 *          driver only supports standard serial hardware (8250, 16450, 16550A)
 *
 *          This modem usually draws its supply current out of the otherwise unused
 *          TXD pin of the serial port. Thus a contignuous stream of 0x00-bytes
 *          is transmitted to achieve a positive supply voltage.
 *
 *  hsk:    This is a 4800 baud FSK modem, designed for TNC use. It works fine
 *          in 'baycom-mode' :-)  In contrast to the TCM3105 modem, power is
 *          externally supplied. So there's no need to provide the 0x00-byte-stream
 *          when receiving or idle, which drastically reduces interrupt load.
 *
 *  Command line options (insmod command line)
 *
 *  mode     ser#    hardware DCD
 *           ser#*   software DCD
 *           ser#+   hardware DCD, inverted signal at DCD pin
 *           '#' denotes the baud rate / 100, eg. ser12* is '1200 baud, soft DCD'
 *  iobase   base address of the port; common values are 0x3f8, 0x2f8, 0x3e8, 0x2e8
 *  baud     baud rate (between 300 and 4800)
 *  irq      interrupt line of the port; common values are 4,3
 *
 *
 *  History:
 *   0.1  26.06.1996  Adapted from baycom.c and made network driver interface
 *        18.10.1996  Changed to new user space access routines (copy_{to,from}_user)
 *   0.3  26.04.1997  init code/data tagged
 *   0.4  08.07.1997  alternative ser12 decoding algorithm (uses delta CTS ints)
 *   0.5  11.11.1997  ser12/par96 split into separate files
 *   0.6  24.01.1998  Thorsten Kranzkowski, dl8bcu and Thomas Sailer:
 *                    reduced interrupt load in transmit case
 *                    reworked receiver
 *   0.7  03.08.1999  adapt to Linus' new __setup/__initcall
 *   0.8  10.08.1999  use module_init/module_exit
 *   0.9  12.02.2000  adapted to softnet driver interface
 *   0.10 03.07.2000  fix interface name handling
 */

/*****************************************************************************/

#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/hdlcdrv.h>
#include <linux/baycom.h>
#include <linux/jiffies.h>

#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/irq.h>

/* --------------------------------------------------------------------- */

#define BAYCOM_DEBUG

/* --------------------------------------------------------------------- */

static const char bc_drvname[] = "baycom_ser_fdx";
static const char bc_drvinfo[] = KERN_INFO "baycom_ser_fdx: (C) 1996-2000 Thomas Sailer, HB9JNX/AE4WA\n"
KERN_INFO "baycom_ser_fdx: version 0.10 compiled " __TIME__ " " __DATE__ "\n";

/* --------------------------------------------------------------------- */

#define NR_PORTS 4

static struct net_device *baycom_device[NR_PORTS];

/* --------------------------------------------------------------------- */

#define RBR(iobase) (iobase+0)
#define THR(iobase) (iobase+0)
#define IER(iobase) (iobase+1)
#define IIR(iobase) (iobase+2)
#define FCR(iobase) (iobase+2)
#define LCR(iobase) (iobase+3)
#define MCR(iobase) (iobase+4)
#define LSR(iobase) (iobase+5)
#define MSR(iobase) (iobase+6)
#define SCR(iobase) (iobase+7)
#define DLL(iobase) (iobase+0)
#define DLM(iobase) (iobase+1)

#define SER12_EXTENT 8

/* ---------------------------------------------------------------------- */
/*
 * Information that need to be kept for each board.
 */

struct baycom_state {
	struct hdlcdrv_state hdrv;

	unsigned int baud, baud_us, baud_arbdiv, baud_uartdiv, baud_dcdtimeout;
	int opt_dcd;

	struct modem_state {
		unsigned char flags;
		unsigned char ptt;
		unsigned int shreg;
		struct modem_state_ser12 {
			unsigned char tx_bit;
			unsigned char last_rxbit;
			int dcd_sum0, dcd_sum1, dcd_sum2;
			int dcd_time;
			unsigned int pll_time;
			unsigned int txshreg;
		} ser12;
	} modem;

#ifdef BAYCOM_DEBUG
	struct debug_vals {
		unsigned long last_jiffies;
		unsigned cur_intcnt;
		unsigned last_intcnt;
		int cur_pllcorr;
		int last_pllcorr;
	} debug_vals;
#endif /* BAYCOM_DEBUG */
};

/* --------------------------------------------------------------------- */

static inline void baycom_int_freq(struct baycom_state *bc)
{
#ifdef BAYCOM_DEBUG
	unsigned long cur_jiffies = jiffies;
	/*
	 * measure the interrupt frequency
	 */
	bc->debug_vals.cur_intcnt++;
	if (time_after_eq(cur_jiffies, bc->debug_vals.last_jiffies + HZ)) {
		bc->debug_vals.last_jiffies = cur_jiffies;
		bc->debug_vals.last_intcnt = bc->debug_vals.cur_intcnt;
		bc->debug_vals.cur_intcnt = 0;
		bc->debug_vals.last_pllcorr = bc->debug_vals.cur_pllcorr;
		bc->debug_vals.cur_pllcorr = 0;
	}
#endif /* BAYCOM_DEBUG */
}

/* --------------------------------------------------------------------- */
/*
 * ===================== SER12 specific routines =========================
 */

/* --------------------------------------------------------------------- */

static inline void ser12_set_divisor(struct net_device *dev,
                                     unsigned int divisor)
{
        outb(0x81, LCR(dev->base_addr));        /* DLAB = 1 */
        outb(divisor, DLL(dev->base_addr));
        outb(divisor >> 8, DLM(dev->base_addr));
        outb(0x01, LCR(dev->base_addr));        /* word length = 6 */
        /*
         * make sure the next interrupt is generated;
         * 0 must be used to power the modem; the modem draws its
         * power from the TxD line
         */
        outb(0x00, THR(dev->base_addr));
        /*
         * it is important not to set the divider while transmitting;
         * this reportedly makes some UARTs generating interrupts
         * in the hundredthousands per second region
         * Reported by: Ignacio.Arenaza@studi.epfl.ch (Ignacio Arenaza Nuno)
         */
}

/* --------------------------------------------------------------------- */

#if 0
static inline unsigned int hweight16(unsigned int w)
        __attribute__ ((unused));
static inline unsigned int hweight8(unsigned int w)
        __attribute__ ((unused));

static inline unsigned int hweight16(unsigned int w)
{
        unsigned short res = (w & 0x5555) + ((w >> 1) & 0x5555);
        res = (res & 0x3333) + ((res >> 2) & 0x3333);
        res = (res & 0x0F0F) + ((res >> 4) & 0x0F0F);
        return (res & 0x00FF) + ((res >> 8) & 0x00FF);
}

static inline unsigned int hweight8(unsigned int w)
{
        unsigned short res = (w & 0x55) + ((w >> 1) & 0x55);
        res = (res & 0x33) + ((res >> 2) & 0x33);
        return (res & 0x0F) + ((res >> 4) & 0x0F);
}
#endif

/* --------------------------------------------------------------------- */

static __inline__ void ser12_rx(struct net_device *dev, struct baycom_state *bc, struct timeval *tv, unsigned char curs)
{
	int timediff;
	int bdus8 = bc->baud_us >> 3;
	int bdus4 = bc->baud_us >> 2;
	int bdus2 = bc->baud_us >> 1;

	timediff = 1000000 + tv->tv_usec - bc->modem.ser12.pll_time;
	while (timediff >= 500000)
		timediff -= 1000000;
	while (timediff >= bdus2) {
		timediff -= bc->baud_us;
		bc->modem.ser12.pll_time += bc->baud_us;
		bc->modem.ser12.dcd_time--;
		/* first check if there is room to add a bit */
		if (bc->modem.shreg & 1) {
			hdlcdrv_putbits(&bc->hdrv, (bc->modem.shreg >> 1) ^ 0xffff);
			bc->modem.shreg = 0x10000;
		}
		/* add a one bit */
		bc->modem.shreg >>= 1;
	}
	if (bc->modem.ser12.dcd_time <= 0) {
		if (!bc->opt_dcd)
			hdlcdrv_setdcd(&bc->hdrv, (bc->modem.ser12.dcd_sum0 + 
						   bc->modem.ser12.dcd_sum1 + 
						   bc->modem.ser12.dcd_sum2) < 0);
		bc->modem.ser12.dcd_sum2 = bc->modem.ser12.dcd_sum1;
		bc->modem.ser12.dcd_sum1 = bc->modem.ser12.dcd_sum0;
		bc->modem.ser12.dcd_sum0 = 2; /* slight bias */
		bc->modem.ser12.dcd_time += 120;
	}
	if (bc->modem.ser12.last_rxbit != curs) {
		bc->modem.ser12.last_rxbit = curs;
		bc->modem.shreg |= 0x10000;
		/* adjust the PLL */
		if (timediff > 0)
			bc->modem.ser12.pll_time += bdus8;
		else
			bc->modem.ser12.pll_time += 1000000 - bdus8;
		/* update DCD */
		if (abs(timediff) > bdus4)
			bc->modem.ser12.dcd_sum0 += 4;
		else
			bc->modem.ser12.dcd_sum0--;
#ifdef BAYCOM_DEBUG
		bc->debug_vals.cur_pllcorr = timediff;
#endif /* BAYCOM_DEBUG */
	}
	while (bc->modem.ser12.pll_time >= 1000000)
		bc->modem.ser12.pll_time -= 1000000;
}

/* --------------------------------------------------------------------- */

static irqreturn_t ser12_interrupt(int irq, void *dev_id)
{
	struct net_device *dev = (struct net_device *)dev_id;
	struct baycom_state *bc = netdev_priv(dev);
	struct timeval tv;
	unsigned char iir, msr;
	unsigned int txcount = 0;

	if (!bc || bc->hdrv.magic != HDLCDRV_MAGIC)
		return IRQ_NONE;
	/* fast way out for shared irq */
	if ((iir = inb(IIR(dev->base_addr))) & 1) 	
		return IRQ_NONE;
	/* get current time */
	do_gettimeofday(&tv);
	msr = inb(MSR(dev->base_addr));
	/* delta DCD */
	if ((msr & 8) && bc->opt_dcd)
		hdlcdrv_setdcd(&bc->hdrv, !((msr ^ bc->opt_dcd) & 0x80));
	do {
		switch (iir & 6) {
		case 6:
			inb(LSR(dev->base_addr));
			break;
			
		case 4:
			inb(RBR(dev->base_addr));
			break;
			
		case 2:
			/*
			 * make sure the next interrupt is generated;
			 * 0 must be used to power the modem; the modem draws its
			 * power from the TxD line
			 */
			outb(0x00, THR(dev->base_addr));
			baycom_int_freq(bc);
			txcount++;
			/*
			 * first output the last bit (!) then call HDLC transmitter,
			 * since this may take quite long
			 */
			if (bc->modem.ptt)
				outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr));
			else
				outb(0x0d, MCR(dev->base_addr));       /* transmitter off */
			break;
			
		default:
			msr = inb(MSR(dev->base_addr));
			/* delta DCD */
			if ((msr & 8) && bc->opt_dcd) 
				hdlcdrv_setdcd(&bc->hdrv, !((msr ^ bc->opt_dcd) & 0x80));
			break;
		}
		iir = inb(IIR(dev->base_addr));
	} while (!(iir & 1));
	ser12_rx(dev, bc, &tv, msr & 0x10); /* CTS */
	if (bc->modem.ptt && txcount) {
		if (bc->modem.ser12.txshreg <= 1) {
			bc->modem.ser12.txshreg = 0x10000 | hdlcdrv_getbits(&bc->hdrv);
			if (!hdlcdrv_ptt(&bc->hdrv)) {
				ser12_set_divisor(dev, 115200/100/8);
				bc->modem.ptt = 0;
				goto end_transmit;
			}
		}
		bc->modem.ser12.tx_bit = !(bc->modem.ser12.tx_bit ^ (bc->modem.ser12.txshreg & 1));
		bc->modem.ser12.txshreg >>= 1;
	}
 end_transmit:
	local_irq_enable();
	if (!bc->modem.ptt && txcount) {
		hdlcdrv_arbitrate(dev, &bc->hdrv);
		if (hdlcdrv_ptt(&bc->hdrv)) {
			ser12_set_divisor(dev, bc->baud_uartdiv);
			bc->modem.ser12.txshreg = 1;
			bc->modem.ptt = 1;
		}
	}
	hdlcdrv_transmitter(dev, &bc->hdrv);
	hdlcdrv_receiver(dev, &bc->hdrv);
	local_irq_disable();
	return IRQ_HANDLED;
}

/* --------------------------------------------------------------------- */

enum uart { c_uart_unknown, c_uart_8250,
	    c_uart_16450, c_uart_16550, c_uart_16550A};
static const char *uart_str[] = { 
	"unknown", "8250", "16450", "16550", "16550A" 
};

static enum uart ser12_check_uart(unsigned int iobase)
{
	unsigned char b1,b2,b3;
	enum uart u;
	enum uart uart_tab[] =
		{ c_uart_16450, c_uart_unknown, c_uart_16550, c_uart_16550A };

	b1 = inb(MCR(iobase));
	outb(b1 | 0x10, MCR(iobase));	/* loopback mode */
	b2 = inb(MSR(iobase));
	outb(0x1a, MCR(iobase));
	b3 = inb(MSR(iobase)) & 0xf0;
	outb(b1, MCR(iobase));			/* restore old values */
	outb(b2, MSR(iobase));
	if (b3 != 0x90)
		return c_uart_unknown;
	inb(RBR(iobase));
	inb(RBR(iobase));
	outb(0x01, FCR(iobase));		/* enable FIFOs */
	u = uart_tab[(inb(IIR(iobase)) >> 6) & 3];
	if (u == c_uart_16450) {
		outb(0x5a, SCR(iobase));
		b1 = inb(SCR(iobase));
		outb(0xa5, SCR(iobase));
		b2 = inb(SCR(iobase));
		if ((b1 != 0x5a) || (b2 != 0xa5))
			u = c_uart_8250;
	}
	return u;
}

/* --------------------------------------------------------------------- */

static int ser12_open(struct net_device *dev)
{
	struct baycom_state *bc = netdev_priv(dev);
	enum uart u;

	if (!dev || !bc)
		return -ENXIO;
	if (!dev->base_addr || dev->base_addr > 0xffff-SER12_EXTENT ||
	    dev->irq < 2 || dev->irq > nr_irqs) {
		printk(KERN_INFO "baycom_ser_fdx: invalid portnumber (max %u) "
				"or irq (2 <= irq <= %d)\n",
				0xffff-SER12_EXTENT, nr_irqs);
		return -ENXIO;
	}
	if (bc->baud < 300 || bc->baud > 4800) {
		printk(KERN_INFO "baycom_ser_fdx: invalid baudrate "
				"(300...4800)\n");
		return -EINVAL;
	}
	if (!request_region(dev->base_addr, SER12_EXTENT, "baycom_ser_fdx")) {
		printk(KERN_WARNING "BAYCOM_SER_FSX: I/O port 0x%04lx busy \n", 
		       dev->base_addr);
		return -EACCES;
	}
	memset(&bc->modem, 0, sizeof(bc->modem));
	bc->hdrv.par.bitrate = bc->baud;
	bc->baud_us = 1000000/bc->baud;
	bc->baud_uartdiv = (115200/8)/bc->baud;
	if ((u = ser12_check_uart(dev->base_addr)) == c_uart_unknown){
		release_region(dev->base_addr, SER12_EXTENT);
		return -EIO;
	}
	outb(0, FCR(dev->base_addr));  /* disable FIFOs */
	outb(0x0d, MCR(dev->base_addr));
	outb(0, IER(dev->base_addr));
	if (request_irq(dev->irq, ser12_interrupt, IRQF_DISABLED | IRQF_SHARED,
			"baycom_ser_fdx", dev)) {
		release_region(dev->base_addr, SER12_EXTENT);
		return -EBUSY;
	}
	/*
	 * set the SIO to 6 Bits/character; during receive,
	 * the baud rate is set to produce 100 ints/sec
	 * to feed the channel arbitration process,
	 * during transmit to baud ints/sec to run
	 * the transmitter
	 */
	ser12_set_divisor(dev, 115200/100/8);
	/*
	 * enable transmitter empty interrupt and modem status interrupt
	 */
	outb(0x0a, IER(dev->base_addr));
	/*
	 * make sure the next interrupt is generated;
	 * 0 must be used to power the modem; the modem draws its
	 * power from the TxD line
	 */
	outb(0x00, THR(dev->base_addr));
	hdlcdrv_setdcd(&bc->hdrv, 0);
	printk(KERN_INFO "%s: ser_fdx at iobase 0x%lx irq %u baud %u uart %s\n",
	       bc_drvname, dev->base_addr, dev->irq, bc->baud, uart_str[u]);
	return 0;
}

/* --------------------------------------------------------------------- */

static int ser12_close(struct net_device *dev)
{
	struct baycom_state *bc = netdev_priv(dev);

	if (!dev || !bc)
		return -EINVAL;
	/*
	 * disable interrupts
	 */
	outb(0, IER(dev->base_addr));
	outb(1, MCR(dev->base_addr));
	free_irq(dev->irq, dev);
	release_region(dev->base_addr, SER12_EXTENT);
	printk(KERN_INFO "%s: close ser_fdx at iobase 0x%lx irq %u\n",
	       bc_drvname, dev->base_addr, dev->irq);
	return 0;
}

/* --------------------------------------------------------------------- */
/*
 * ===================== hdlcdrv driver interface =========================
 */

/* --------------------------------------------------------------------- */

static int baycom_ioctl(struct net_device *dev, struct ifreq *ifr,
			struct hdlcdrv_ioctl *hi, int cmd);

/* --------------------------------------------------------------------- */

static struct hdlcdrv_ops ser12_ops = {
	.drvname = bc_drvname,
	.drvinfo = bc_drvinfo,
	.open    = ser12_open,
	.close   = ser12_close,
	.ioctl   = baycom_ioctl,
};

/* --------------------------------------------------------------------- */

static int baycom_setmode(struct baycom_state *bc, const char *modestr)
{
	unsigned int baud;

	if (!strncmp(modestr, "ser", 3)) {
		baud = simple_strtoul(modestr+3, NULL, 10);
		if (baud >= 3 && baud <= 48)
			bc->baud = baud*100;
	}
	if (strchr(modestr, '*'))
		bc->opt_dcd = 0;
	else if (strchr(modestr, '+'))
		bc->opt_dcd = -1;
	else
		bc->opt_dcd = 1;
	return 0;
}

/* --------------------------------------------------------------------- */

static int baycom_ioctl(struct net_device *dev, struct ifreq *ifr,
			struct hdlcdrv_ioctl *hi, int cmd)
{
	struct baycom_state *bc;
	struct baycom_ioctl bi;

	if (!dev)
		return -EINVAL;

	bc = netdev_priv(dev);
	BUG_ON(bc->hdrv.magic != HDLCDRV_MAGIC);

	if (cmd != SIOCDEVPRIVATE)
		return -ENOIOCTLCMD;
	switch (hi->cmd) {
	default:
		break;

	case HDLCDRVCTL_GETMODE:
		sprintf(hi->data.modename, "ser%u", bc->baud / 100);
		if (bc->opt_dcd <= 0)
			strcat(hi->data.modename, (!bc->opt_dcd) ? "*" : "+");
		if (copy_to_user(ifr->ifr_data, hi, sizeof(struct hdlcdrv_ioctl)))
			return -EFAULT;
		return 0;

	case HDLCDRVCTL_SETMODE:
		if (netif_running(dev) || !capable(CAP_NET_ADMIN))
			return -EACCES;
		hi->data.modename[sizeof(hi->data.modename)-1] = '\0';
		return baycom_setmode(bc, hi->data.modename);

	case HDLCDRVCTL_MODELIST:
		strcpy(hi->data.modename, "ser12,ser3,ser24");
		if (copy_to_user(ifr->ifr_data, hi, sizeof(struct hdlcdrv_ioctl)))
			return -EFAULT;
		return 0;

	case HDLCDRVCTL_MODEMPARMASK:
		return HDLCDRV_PARMASK_IOBASE | HDLCDRV_PARMASK_IRQ;

	}

	if (copy_from_user(&bi, ifr->ifr_data, sizeof(bi)))
		return -EFAULT;
	switch (bi.cmd) {
	default:
		return -ENOIOCTLCMD;

#ifdef BAYCOM_DEBUG
	case BAYCOMCTL_GETDEBUG:
		bi.data.dbg.debug1 = bc->hdrv.ptt_keyed;
		bi.data.dbg.debug2 = bc->debug_vals.last_intcnt;
		bi.data.dbg.debug3 = bc->debug_vals.last_pllcorr;
		break;
#endif /* BAYCOM_DEBUG */

	}
	if (copy_to_user(ifr->ifr_data, &bi, sizeof(bi)))
		return -EFAULT;
	return 0;

}

/* --------------------------------------------------------------------- */

/*
 * command line settable parameters
 */
static char *mode[NR_PORTS] = { "ser12*", };
static int iobase[NR_PORTS] = { 0x3f8, };
static int irq[NR_PORTS] = { 4, };
static int baud[NR_PORTS] = { [0 ... NR_PORTS-1] = 1200 };

module_param_array(mode, charp, NULL, 0);
MODULE_PARM_DESC(mode, "baycom operating mode; * for software DCD");
module_param_array(iobase, int, NULL, 0);
MODULE_PARM_DESC(iobase, "baycom io base address");
module_param_array(irq, int, NULL, 0);
MODULE_PARM_DESC(irq, "baycom irq number");
module_param_array(baud, int, NULL, 0);
MODULE_PARM_DESC(baud, "baycom baud rate (300 to 4800)");

MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
MODULE_DESCRIPTION("Baycom ser12 full duplex amateur radio modem driver");
MODULE_LICENSE("GPL");

/* --------------------------------------------------------------------- */

static int __init init_baycomserfdx(void)
{
	int i, found = 0;
	char set_hw = 1;

	printk(bc_drvinfo);
	/*
	 * register net devices
	 */
	for (i = 0; i < NR_PORTS; i++) {
		struct net_device *dev;
		struct baycom_state *bc;
		char ifname[IFNAMSIZ];

		sprintf(ifname, "bcsf%d", i);

		if (!mode[i])
			set_hw = 0;
		if (!set_hw)
			iobase[i] = irq[i] = 0;

		dev = hdlcdrv_register(&ser12_ops, 
				       sizeof(struct baycom_state),
				       ifname, iobase[i], irq[i], 0);
		if (IS_ERR(dev)) 
			break;

		bc = netdev_priv(dev);
		if (set_hw && baycom_setmode(bc, mode[i]))
			set_hw = 0;
		bc->baud = baud[i];
		found++;
		baycom_device[i] = dev;
	}

	if (!found)
		return -ENXIO;
	return 0;
}

static void __exit cleanup_baycomserfdx(void)
{
	int i;

	for(i = 0; i < NR_PORTS; i++) {
		struct net_device *dev = baycom_device[i];
		if (dev) 
			hdlcdrv_unregister(dev);
	}
}

module_init(init_baycomserfdx);
module_exit(cleanup_baycomserfdx);

/* --------------------------------------------------------------------- */

#ifndef MODULE

/*
 * format: baycom_ser_fdx=io,irq,mode
 * mode: ser#    hardware DCD
 *       ser#*   software DCD
 *       ser#+   hardware DCD, inverted signal at DCD pin
 * '#' denotes the baud rate / 100, eg. ser12* is '1200 baud, soft DCD'
 */

static int __init baycom_ser_fdx_setup(char *str)
{
        static unsigned nr_dev;
        int ints[4];

        if (nr_dev >= NR_PORTS)
                return 0;
        str = get_options(str, 4, ints);
        if (ints[0] < 2)
                return 0;
        mode[nr_dev] = str;
        iobase[nr_dev] = ints[1];
        irq[nr_dev] = ints[2];
	if (ints[0] >= 3)
		baud[nr_dev] = ints[3];
	nr_dev++;
	return 1;
}

__setup("baycom_ser_fdx=", baycom_ser_fdx_setup);

#endif /* MODULE */
/* --------------------------------------------------------------------- */
>int on) { unsigned char tmp; if (on) { /* * Turn off screen and disable sequencer. */ tmp = NVReadSeq(par, 0x01); NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */ NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */ } else { /* * Reenable sequencer, then turn on screen. */ tmp = NVReadSeq(par, 0x01); NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */ NVWriteSeq(par, 0x00, 0x03); /* End Reset */ } } static void nvidia_save_vga(struct nvidia_par *par, struct _riva_hw_state *state) { int i; NVTRACE_ENTER(); NVLockUnlock(par, 0); NVUnloadStateExt(par, state); state->misc_output = NVReadMiscOut(par); for (i = 0; i < NUM_CRT_REGS; i++) state->crtc[i] = NVReadCrtc(par, i); for (i = 0; i < NUM_ATC_REGS; i++) state->attr[i] = NVReadAttr(par, i); for (i = 0; i < NUM_GRC_REGS; i++) state->gra[i] = NVReadGr(par, i); for (i = 0; i < NUM_SEQ_REGS; i++) state->seq[i] = NVReadSeq(par, i); NVTRACE_LEAVE(); } #undef DUMP_REG static void nvidia_write_regs(struct nvidia_par *par, struct _riva_hw_state *state) { int i; NVTRACE_ENTER(); NVLoadStateExt(par, state); NVWriteMiscOut(par, state->misc_output); for (i = 1; i < NUM_SEQ_REGS; i++) { #ifdef DUMP_REG printk(" SEQ[%02x] = %08x\n", i, state->seq[i]); #endif NVWriteSeq(par, i, state->seq[i]); } /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */ NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80); for (i = 0; i < NUM_CRT_REGS; i++) { switch (i) { case 0x19: case 0x20 ... 0x40: break; default: #ifdef DUMP_REG printk("CRTC[%02x] = %08x\n", i, state->crtc[i]); #endif NVWriteCrtc(par, i, state->crtc[i]); } } for (i = 0; i < NUM_GRC_REGS; i++) { #ifdef DUMP_REG printk(" GRA[%02x] = %08x\n", i, state->gra[i]); #endif NVWriteGr(par, i, state->gra[i]); } for (i = 0; i < NUM_ATC_REGS; i++) { #ifdef DUMP_REG printk("ATTR[%02x] = %08x\n", i, state->attr[i]); #endif NVWriteAttr(par, i, state->attr[i]); } NVTRACE_LEAVE(); } static int nvidia_calc_regs(struct fb_info *info) { struct nvidia_par *par = info->par; struct _riva_hw_state *state = &par->ModeReg; int i, depth = fb_get_color_depth(&info->var, &info->fix); int h_display = info->var.xres / 8 - 1; int h_start = (info->var.xres + info->var.right_margin) / 8 - 1; int h_end = (info->var.xres + info->var.right_margin + info->var.hsync_len) / 8 - 1; int h_total = (info->var.xres + info->var.right_margin + info->var.hsync_len + info->var.left_margin) / 8 - 5; int h_blank_s = h_display; int h_blank_e = h_total + 4; int v_display = info->var.yres - 1; int v_start = info->var.yres + info->var.lower_margin - 1; int v_end = (info->var.yres + info->var.lower_margin + info->var.vsync_len) - 1; int v_total = (info->var.yres + info->var.lower_margin + info->var.vsync_len + info->var.upper_margin) - 2; int v_blank_s = v_display; int v_blank_e = v_total + 1; /* * Set all CRTC values. */ if (info->var.vmode & FB_VMODE_INTERLACED) v_total |= 1; if (par->FlatPanel == 1) { v_start = v_total - 3; v_end = v_total - 2; v_blank_s = v_start; h_start = h_total - 5; h_end = h_total - 2; h_blank_e = h_total + 4; } state->crtc[0x0] = Set8Bits(h_total); state->crtc[0x1] = Set8Bits(h_display); state->crtc[0x2] = Set8Bits(h_blank_s); state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0) | SetBit(7); state->crtc[0x4] = Set8Bits(h_start); state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7) | SetBitField(h_end, 4: 0, 4:0); state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0); state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0) | SetBitField(v_display, 8: 8, 1:1) | SetBitField(v_start, 8: 8, 2:2) | SetBitField(v_blank_s, 8: 8, 3:3) | SetBit(4) | SetBitField(v_total, 9: 9, 5:5) | SetBitField(v_display, 9: 9, 6:6) | SetBitField(v_start, 9: 9, 7:7); state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5) | SetBit(6) | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00); state->crtc[0x10] = Set8Bits(v_start); state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5); state->crtc[0x12] = Set8Bits(v_display); state->crtc[0x13] = ((info->var.xres_virtual / 8) * (info->var.bits_per_pixel / 8)); state->crtc[0x15] = Set8Bits(v_blank_s); state->crtc[0x16] = Set8Bits(v_blank_e); state->attr[0x10] = 0x01; if (par->Television) state->attr[0x11] = 0x00; state->screen = SetBitField(h_blank_e, 6: 6, 4:4) | SetBitField(v_blank_s, 10: 10, 3:3) | SetBitField(v_start, 10: 10, 2:2) | SetBitField(v_display, 10: 10, 1:1) | SetBitField(v_total, 10: 10, 0:0); state->horiz = SetBitField(h_total, 8: 8, 0:0) | SetBitField(h_display, 8: 8, 1:1) | SetBitField(h_blank_s, 8: 8, 2:2) | SetBitField(h_start, 8: 8, 3:3); state->extra = SetBitField(v_total, 11: 11, 0:0) | SetBitField(v_display, 11: 11, 2:2) | SetBitField(v_start, 11: 11, 4:4) | SetBitField(v_blank_s, 11: 11, 6:6); if (info->var.vmode & FB_VMODE_INTERLACED) { h_total = (h_total >> 1) & ~1; state->interlace = Set8Bits(h_total); state->horiz |= SetBitField(h_total, 8: 8, 4:4); } else { state->interlace = 0xff; /* interlace off */ } /* * Calculate the extended registers. */ if (depth < 24) i = depth; else i = 32; if (par->Architecture >= NV_ARCH_10) par->CURSOR = (volatile u32 __iomem *)(info->screen_base + par->CursorStart); if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) state->misc_output &= ~0x40; else state->misc_output |= 0x40; if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) state->misc_output &= ~0x80; else state->misc_output |= 0x80; NVCalcStateExt(par, state, i, info->var.xres_virtual, info->var.xres, info->var.yres_virtual, 1000000000 / info->var.pixclock, info->var.vmode); state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff; if (par->FlatPanel == 1) { state->pixel |= (1 << 7); if (!par->fpScaler || (par->fpWidth <= info->var.xres) || (par->fpHeight <= info->var.yres)) { state->scale |= (1 << 8); } if (!par->crtcSync_read) { state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828); par->crtcSync_read = 1; } par->PanelTweak = nvidia_panel_tweak(par, state); } state->vpll = state->pll; state->vpll2 = state->pll; state->vpllB = state->pllB; state->vpll2B = state->pllB; VGA_WR08(par->PCIO, 0x03D4, 0x1C); state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); if (par->CRTCnumber) { state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000; state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000; state->crtcOwner = 3; state->pllsel |= 0x20000800; state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); if (par->twoStagePLL) state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578); } else if (par->twoHeads) { state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000; state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000; state->crtcOwner = 0; state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); if (par->twoStagePLL) state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); } state->cursorConfig = 0x00000100; if (info->var.vmode & FB_VMODE_DOUBLE) state->cursorConfig |= (1 << 4); if (par->alphaCursor) { if ((par->Chipset & 0x0ff0) != 0x0110) state->cursorConfig |= 0x04011000; else state->cursorConfig |= 0x14011000; state->general |= (1 << 29); } else state->cursorConfig |= 0x02000000; if (par->twoHeads) { if ((par->Chipset & 0x0ff0) == 0x0110) { state->dither = NV_RD32(par->PRAMDAC, 0x0528) & ~0x00010000; if (par->FPDither) state->dither |= 0x00010000; } else { state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1; if (par->FPDither) state->dither |= 1; } } state->timingH = 0; state->timingV = 0; state->displayV = info->var.xres; return 0; } static void nvidia_init_vga(struct fb_info *info) { struct nvidia_par *par = info->par; struct _riva_hw_state *state = &par->ModeReg; int i; for (i = 0; i < 0x10; i++) state->attr[i] = i; state->attr[0x10] = 0x41; state->attr[0x11] = 0xff; state->attr[0x12] = 0x0f; state->attr[0x13] = 0x00; state->attr[0x14] = 0x00; memset(state->crtc, 0x00, NUM_CRT_REGS); state->crtc[0x0a] = 0x20; state->crtc[0x17] = 0xe3; state->crtc[0x18] = 0xff; state->crtc[0x28] = 0x40; memset(state->gra, 0x00, NUM_GRC_REGS); state->gra[0x05] = 0x40; state->gra[0x06] = 0x05; state->gra[0x07] = 0x0f; state->gra[0x08] = 0xff; state->seq[0x00] = 0x03; state->seq[0x01] = 0x01; state->seq[0x02] = 0x0f; state->seq[0x03] = 0x00; state->seq[0x04] = 0x0e; state->misc_output = 0xeb; } static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor) { struct nvidia_par *par = info->par; u8 data[MAX_CURS * MAX_CURS / 8]; int i, set = cursor->set; u16 fg, bg; if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) return -ENXIO; NVShowHideCursor(par, 0); if (par->cursor_reset) { set = FB_CUR_SETALL; par->cursor_reset = 0; } if (set & FB_CUR_SETSIZE) memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2); if (set & FB_CUR_SETPOS) { u32 xx, yy, temp; yy = cursor->image.dy - info->var.yoffset; xx = cursor->image.dx - info->var.xoffset; temp = xx & 0xFFFF; temp |= yy << 16; NV_WR32(par->PRAMDAC, 0x0000300, temp); } if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { u32 bg_idx = cursor->image.bg_color; u32 fg_idx = cursor->image.fg_color; u32 s_pitch = (cursor->image.width + 7) >> 3; u32 d_pitch = MAX_CURS / 8; u8 *dat = (u8 *) cursor->image.data; u8 *msk = (u8 *) cursor->mask; u8 *src; src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC); if (src) { switch (cursor->rop) { case ROP_XOR: for (i = 0; i < s_pitch * cursor->image.height; i++) src[i] = dat[i] ^ msk[i]; break; case ROP_COPY: default: for (i = 0; i < s_pitch * cursor->image.height; i++) src[i] = dat[i] & msk[i]; break; } fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, cursor->image.height); bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | ((info->cmap.green[bg_idx] & 0xf8) << 2) | ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15; fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | ((info->cmap.green[fg_idx] & 0xf8) << 2) | ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15; NVLockUnlock(par, 0); nvidiafb_load_cursor_image(par, data, bg, fg, cursor->image.width, cursor->image.height); kfree(src); } } if (cursor->enable) NVShowHideCursor(par, 1); return 0; } static int nvidiafb_set_par(struct fb_info *info) { struct nvidia_par *par = info->par; NVTRACE_ENTER(); NVLockUnlock(par, 1); if (!par->FlatPanel || !par->twoHeads) par->FPDither = 0; if (par->FPDither < 0) { if ((par->Chipset & 0x0ff0) == 0x0110) par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528) & 0x00010000); else par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1); printk(KERN_INFO PFX "Flat panel dithering %s\n", par->FPDither ? "enabled" : "disabled"); } info->fix.visual = (info->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; nvidia_init_vga(info); nvidia_calc_regs(info); NVLockUnlock(par, 0); if (par->twoHeads) { VGA_WR08(par->PCIO, 0x03D4, 0x44); VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); NVLockUnlock(par, 0); } nvidia_screen_off(par, 1); nvidia_write_regs(par, &par->ModeReg); NVSetStartAddress(par, 0); #if defined (__BIG_ENDIAN) /* turn on LFB swapping */ { unsigned char tmp; VGA_WR08(par->PCIO, 0x3d4, 0x46); tmp = VGA_RD08(par->PCIO, 0x3d5); tmp |= (1 << 7); VGA_WR08(par->PCIO, 0x3d5, tmp); } #endif info->fix.line_length = (info->var.xres_virtual * info->var.bits_per_pixel) >> 3; if (info->var.accel_flags) { info->fbops->fb_imageblit = nvidiafb_imageblit; info->fbops->fb_fillrect = nvidiafb_fillrect; info->fbops->fb_copyarea = nvidiafb_copyarea; info->fbops->fb_sync = nvidiafb_sync; info->pixmap.scan_align = 4; info->flags &= ~FBINFO_HWACCEL_DISABLED; info->flags |= FBINFO_READS_FAST; NVResetGraphics(info); } else { info->fbops->fb_imageblit = cfb_imageblit; info->fbops->fb_fillrect = cfb_fillrect; info->fbops->fb_copyarea = cfb_copyarea; info->fbops->fb_sync = NULL; info->pixmap.scan_align = 1; info->flags |= FBINFO_HWACCEL_DISABLED; info->flags &= ~FBINFO_READS_FAST; } par->cursor_reset = 1; nvidia_screen_off(par, 0); #ifdef CONFIG_BOOTX_TEXT /* Update debug text engine */ btext_update_display(info->fix.smem_start, info->var.xres, info->var.yres, info->var.bits_per_pixel, info->fix.line_length); #endif NVLockUnlock(par, 0); NVTRACE_LEAVE(); return 0; } static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info) { struct nvidia_par *par = info->par; int i; NVTRACE_ENTER(); if (regno >= (1 << info->var.green.length)) return -EINVAL; if (info->var.grayscale) { /* gray = 0.30*R + 0.59*G + 0.11*B */ red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; } if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { ((u32 *) info->pseudo_palette)[regno] = (regno << info->var.red.offset) | (regno << info->var.green.offset) | (regno << info->var.blue.offset); } switch (info->var.bits_per_pixel) { case 8: /* "transparent" stuff is completely ignored. */ nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); break; case 16: if (info->var.green.length == 5) { for (i = 0; i < 8; i++) { nvidia_write_clut(par, regno * 8 + i, red >> 8, green >> 8, blue >> 8); } } else { u8 r, g, b; if (regno < 32) { for (i = 0; i < 8; i++) { nvidia_write_clut(par, regno * 8 + i, red >> 8, green >> 8, blue >> 8); } } nvidia_read_clut(par, regno * 4, &r, &g, &b); for (i = 0; i < 4; i++) nvidia_write_clut(par, regno * 4 + i, r, green >> 8, b); } break; case 32: nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); break; default: /* do nothing */ break; } NVTRACE_LEAVE(); return 0; } static int nvidiafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { struct nvidia_par *par = info->par; int memlen, vramlen, mode_valid = 0; int pitch, err = 0; NVTRACE_ENTER(); var->transp.offset = 0; var->transp.length = 0; var->xres &= ~7; if (var->bits_per_pixel <= 8) var->bits_per_pixel = 8; else if (var->bits_per_pixel <= 16) var->bits_per_pixel = 16; else var->bits_per_pixel = 32; switch (var->bits_per_pixel) { case 8: var->red.offset = 0; var->red.length = 8; var->green.offset = 0; var->green.length = 8; var->blue.offset = 0; var->blue.length = 8; var->transp.offset = 0; var->transp.length = 0; break; case 16: var->green.length = (var->green.length < 6) ? 5 : 6; var->red.length = 5; var->blue.length = 5; var->transp.length = 6 - var->green.length; var->blue.offset = 0; var->green.offset = 5; var->red.offset = 5 + var->green.length; var->transp.offset = (5 + var->red.offset) & 15; break; case 32: /* RGBA 8888 */ var->red.offset = 16; var->red.length = 8; var->green.offset = 8; var->green.length = 8; var->blue.offset = 0; var->blue.length = 8; var->transp.length = 8; var->transp.offset = 24; break; } var->red.msb_right = 0; var->green.msb_right = 0; var->blue.msb_right = 0; var->transp.msb_right = 0; if (!info->monspecs.hfmax || !info->monspecs.vfmax || !info->monspecs.dclkmax || !fb_validate_mode(var, info)) mode_valid = 1; /* calculate modeline if supported by monitor */ if (!mode_valid && info->monspecs.gtf) { if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) mode_valid = 1; } if (!mode_valid) { const struct fb_videomode *mode; mode = fb_find_best_mode(var, &info->modelist); if (mode) { fb_videomode_to_var(var, mode); mode_valid = 1; } } if (!mode_valid && info->monspecs.modedb_len) return -EINVAL; /* * If we're on a flat panel, check if the mode is outside of the * panel dimensions. If so, cap it and try for the next best mode * before bailing out. */ if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres || par->fpHeight < var->yres)) { const struct fb_videomode *mode; var->xres = par->fpWidth; var->yres = par->fpHeight; mode = fb_find_best_mode(var, &info->modelist); if (!mode) { printk(KERN_ERR PFX "mode out of range of flat " "panel dimensions\n"); return -EINVAL; } fb_videomode_to_var(var, mode); } if (var->yres_virtual < var->yres) var->yres_virtual = var->yres; if (var->xres_virtual < var->xres) var->xres_virtual = var->xres; var->xres_virtual = (var->xres_virtual + 63) & ~63; vramlen = info->screen_size; pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8; memlen = pitch * var->yres_virtual; if (memlen > vramlen) { var->yres_virtual = vramlen / pitch; if (var->yres_virtual < var->yres) { var->yres_virtual = var->yres; var->xres_virtual = vramlen / var->yres_virtual; var->xres_virtual /= var->bits_per_pixel / 8; var->xres_virtual &= ~63; pitch = (var->xres_virtual * var->bits_per_pixel + 7) / 8; memlen = pitch * var->yres; if (var->xres_virtual < var->xres) { printk("nvidiafb: required video memory, " "%d bytes, for %dx%d-%d (virtual) " "is out of range\n", memlen, var->xres_virtual, var->yres_virtual, var->bits_per_pixel); err = -ENOMEM; } } } if (var->accel_flags) { if (var->yres_virtual > 0x7fff) var->yres_virtual = 0x7fff; if (var->xres_virtual > 0x7fff) var->xres_virtual = 0x7fff; } var->xres_virtual &= ~63; NVTRACE_LEAVE(); return err; } static int nvidiafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) { struct nvidia_par *par = info->par; u32 total; total = var->yoffset * info->fix.line_length + var->xoffset; NVSetStartAddress(par, total); return 0; } static int nvidiafb_blank(int blank, struct fb_info *info) { struct nvidia_par *par = info->par; unsigned char tmp, vesa; tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */ vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */ NVTRACE_ENTER(); if (blank) tmp |= 0x20; switch (blank) { case FB_BLANK_UNBLANK: case FB_BLANK_NORMAL: break; case FB_BLANK_VSYNC_SUSPEND: vesa |= 0x80; break; case FB_BLANK_HSYNC_SUSPEND: vesa |= 0x40; break; case FB_BLANK_POWERDOWN: vesa |= 0xc0; break; } NVWriteSeq(par, 0x01, tmp); NVWriteCrtc(par, 0x1a, vesa); NVTRACE_LEAVE(); return 0; } /* * Because the VGA registers are not mapped linearly in its MMIO space, * restrict VGA register saving and restore to x86 only, where legacy VGA IO * access is legal. Consequently, we must also check if the device is the * primary display. */ #ifdef CONFIG_X86 static void save_vga_x86(struct nvidia_par *par) { struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; if (res && res->flags & IORESOURCE_ROM_SHADOW) { memset(&par->vgastate, 0, sizeof(par->vgastate)); par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; save_vga(&par->vgastate); } } static void restore_vga_x86(struct nvidia_par *par) { struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; if (res && res->flags & IORESOURCE_ROM_SHADOW) restore_vga(&par->vgastate); } #else #define save_vga_x86(x) do {} while (0) #define restore_vga_x86(x) do {} while (0) #endif /* X86 */ static int nvidiafb_open(struct fb_info *info, int user) { struct nvidia_par *par = info->par; if (!par->open_count) { save_vga_x86(par); nvidia_save_vga(par, &par->initial_state); } par->open_count++; return 0; } static int nvidiafb_release(struct fb_info *info, int user) { struct nvidia_par *par = info->par; int err = 0; if (!par->open_count) { err = -EINVAL; goto done; } if (par->open_count == 1) { nvidia_write_regs(par, &par->initial_state); restore_vga_x86(par); } par->open_count--; done: return err; } static struct fb_ops nvidia_fb_ops = { .owner = THIS_MODULE, .fb_open = nvidiafb_open, .fb_release = nvidiafb_release, .fb_check_var = nvidiafb_check_var, .fb_set_par = nvidiafb_set_par, .fb_setcolreg = nvidiafb_setcolreg, .fb_pan_display = nvidiafb_pan_display, .fb_blank = nvidiafb_blank, .fb_fillrect = nvidiafb_fillrect, .fb_copyarea = nvidiafb_copyarea, .fb_imageblit = nvidiafb_imageblit, .fb_cursor = nvidiafb_cursor, .fb_sync = nvidiafb_sync, }; #ifdef CONFIG_PM static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t mesg) { struct fb_info *info = pci_get_drvdata(dev); struct nvidia_par *par = info->par; if (mesg.event == PM_EVENT_PRETHAW) mesg.event = PM_EVENT_FREEZE; console_lock(); par->pm_state = mesg.event; if (mesg.event & PM_EVENT_SLEEP) { fb_set_suspend(info, 1); nvidiafb_blank(FB_BLANK_POWERDOWN, info); nvidia_write_regs(par, &par->SavedReg); pci_save_state(dev); pci_disable_device(dev); pci_set_power_state(dev, pci_choose_state(dev, mesg)); } dev->dev.power.power_state = mesg; console_unlock(); return 0; } static int nvidiafb_resume(struct pci_dev *dev) { struct fb_info *info = pci_get_drvdata(dev); struct nvidia_par *par = info->par; console_lock(); pci_set_power_state(dev, PCI_D0); if (par->pm_state != PM_EVENT_FREEZE) { pci_restore_state(dev); if (pci_enable_device(dev)) goto fail; pci_set_master(dev); } par->pm_state = PM_EVENT_ON; nvidiafb_set_par(info); fb_set_suspend (info, 0); nvidiafb_blank(FB_BLANK_UNBLANK, info); fail: console_unlock(); return 0; } #else #define nvidiafb_suspend NULL #define nvidiafb_resume NULL #endif static int nvidia_set_fbinfo(struct fb_info *info) { struct fb_monspecs *specs = &info->monspecs; struct fb_videomode modedb; struct nvidia_par *par = info->par; int lpitch; NVTRACE_ENTER(); info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_YPAN; fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len, &info->modelist); fb_var_to_videomode(&modedb, &nvidiafb_default_var); switch (bpp) { case 0 ... 8: bpp = 8; break; case 9 ... 16: bpp = 16; break; default: bpp = 32; break; } if (specs->modedb != NULL) { const struct fb_videomode *mode; mode = fb_find_best_display(specs, &info->modelist); fb_videomode_to_var(&nvidiafb_default_var, mode); nvidiafb_default_var.bits_per_pixel = bpp; } else if (par->fpWidth && par->fpHeight) { char buf[16]; memset(buf, 0, 16); snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight); fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb, specs->modedb_len, &modedb, bpp); } if (mode_option) fb_find_mode(&nvidiafb_default_var, info, mode_option, specs->modedb, specs->modedb_len, &modedb, bpp); info->var = nvidiafb_default_var; info->fix.visual = (info->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; info->pseudo_palette = par->pseudo_palette; fb_alloc_cmap(&info->cmap, 256, 0); fb_destroy_modedb(info->monspecs.modedb); info->monspecs.modedb = NULL; /* maximize virtual vertical length */ lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3); info->var.yres_virtual = info->screen_size / lpitch; info->pixmap.scan_align = 4; info->pixmap.buf_align = 4; info->pixmap.access_align = 32; info->pixmap.size = 8 * 1024; info->pixmap.flags = FB_PIXMAP_SYSTEM; if (!hwcur) info->fbops->fb_cursor = NULL; info->var.accel_flags = (!noaccel); switch (par->Architecture) { case NV_ARCH_04: info->fix.accel = FB_ACCEL_NV4; break; case NV_ARCH_10: info->fix.accel = FB_ACCEL_NV_10; break; case NV_ARCH_20: info->fix.accel = FB_ACCEL_NV_20; break; case NV_ARCH_30: info->fix.accel = FB_ACCEL_NV_30; break; case NV_ARCH_40: info->fix.accel = FB_ACCEL_NV_40; break; } NVTRACE_LEAVE(); return nvidiafb_check_var(&info->var, info); } static u32 nvidia_get_chipset(struct fb_info *info) { struct nvidia_par *par = info->par; u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device; printk(KERN_INFO PFX "Device ID: %x \n", id); if ((id & 0xfff0) == 0x00f0 || (id & 0xfff0) == 0x02e0) { /* pci-e */ id = NV_RD32(par->REGS, 0x1800); if ((id & 0x0000ffff) == 0x000010DE) id = 0x10DE0000 | (id >> 16); else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */ id = 0x10DE0000 | ((id << 8) & 0x0000ff00) | ((id >> 8) & 0x000000ff); printk(KERN_INFO PFX "Subsystem ID: %x \n", id); } return id; } static u32 nvidia_get_arch(struct fb_info *info) { struct nvidia_par *par = info->par; u32 arch = 0; switch (par->Chipset & 0x0ff0) { case 0x0100: /* GeForce 256 */ case 0x0110: /* GeForce2 MX */ case 0x0150: /* GeForce2 */ case 0x0170: /* GeForce4 MX */ case 0x0180: /* GeForce4 MX (8x AGP) */ case 0x01A0: /* nForce */ case 0x01F0: /* nForce2 */ arch = NV_ARCH_10; break; case 0x0200: /* GeForce3 */ case 0x0250: /* GeForce4 Ti */ case 0x0280: /* GeForce4 Ti (8x AGP) */ arch = NV_ARCH_20; break; case 0x0300: /* GeForceFX 5800 */ case 0x0310: /* GeForceFX 5600 */ case 0x0320: /* GeForceFX 5200 */ case 0x0330: /* GeForceFX 5900 */ case 0x0340: /* GeForceFX 5700 */ arch = NV_ARCH_30; break; case 0x0040: /* GeForce 6800 */ case 0x00C0: /* GeForce 6800 */ case 0x0120: /* GeForce 6800 */ case 0x0140: /* GeForce 6600 */ case 0x0160: /* GeForce 6200 */ case 0x01D0: /* GeForce 7200, 7300, 7400 */ case 0x0090: /* GeForce 7800 */ case 0x0210: /* GeForce 6800 */ case 0x0220: /* GeForce 6200 */ case 0x0240: /* GeForce 6100 */ case 0x0290: /* GeForce 7900 */ case 0x0390: /* GeForce 7600 */ case 0x03D0: arch = NV_ARCH_40; break; case 0x0020: /* TNT, TNT2 */ arch = NV_ARCH_04; break; default: /* unknown architecture */ break; } return arch; } static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) { struct nvidia_par *par; struct fb_info *info; unsigned short cmd; NVTRACE_ENTER(); assert(pd != NULL); info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev); if (!info) goto err_out; par = info->par; par->pci_dev = pd; info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); if (info->pixmap.addr == NULL) goto err_out_kfree; if (pci_enable_device(pd)) { printk(KERN_ERR PFX "cannot enable PCI device\n"); goto err_out_enable; } if (pci_request_regions(pd, "nvidiafb")) { printk(KERN_ERR PFX "cannot request PCI regions\n"); goto err_out_enable; } par->FlatPanel = flatpanel; if (flatpanel == 1) printk(KERN_INFO PFX "flatpanel support enabled\n"); par->FPDither = fpdither; par->CRTCnumber = forceCRTC; par->FpScale = (!noscale); par->paneltweak = paneltweak; par->reverse_i2c = reverse_i2c; /* enable IO and mem if not already done */ pci_read_config_word(pd, PCI_COMMAND, &cmd); cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); pci_write_config_word(pd, PCI_COMMAND, cmd); nvidiafb_fix.mmio_start = pci_resource_start(pd, 0); nvidiafb_fix.smem_start = pci_resource_start(pd, 1); nvidiafb_fix.mmio_len = pci_resource_len(pd, 0); par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); if (!par->REGS) { printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); goto err_out_free_base0; } par->Chipset = nvidia_get_chipset(info); par->Architecture = nvidia_get_arch(info); if (par->Architecture == 0) { printk(KERN_ERR PFX "unknown NV_ARCH\n"); goto err_out_arch; } sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); if (NVCommonSetup(info)) goto err_out_arch; par->FbAddress = nvidiafb_fix.smem_start; par->FbMapSize = par->RamAmountKBytes * 1024; if (vram && vram * 1024 * 1024 < par->FbMapSize) par->FbMapSize = vram * 1024 * 1024; /* Limit amount of vram to 64 MB */ if (par->FbMapSize > 64 * 1024 * 1024) par->FbMapSize = 64 * 1024 * 1024; if(par->Architecture >= NV_ARCH_40) par->FbUsableSize = par->FbMapSize - (560 * 1024); else par->FbUsableSize = par->FbMapSize - (128 * 1024); par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 : 16 * 1024; par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize; par->CursorStart = par->FbUsableSize + (32 * 1024); info->screen_base = ioremap_wc(nvidiafb_fix.smem_start, par->FbMapSize); info->screen_size = par->FbUsableSize; nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024; if (!info->screen_base) { printk(KERN_ERR PFX "cannot ioremap FB base\n"); goto err_out_free_base1; } par->FbStart = info->screen_base; if (!nomtrr) par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start, par->RamAmountKBytes * 1024); info->fbops = &nvidia_fb_ops; info->fix = nvidiafb_fix; if (nvidia_set_fbinfo(info) < 0) { printk(KERN_ERR PFX "error setting initial video mode\n"); goto err_out_iounmap_fb; } nvidia_save_vga(par, &par->SavedReg); pci_set_drvdata(pd, info); if (backlight) nvidia_bl_init(par); if (register_framebuffer(info) < 0) { printk(KERN_ERR PFX "error registering nVidia framebuffer\n"); goto err_out_iounmap_fb; } printk(KERN_INFO PFX "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n", info->fix.id, par->FbMapSize / (1024 * 1024), info->fix.smem_start); NVTRACE_LEAVE(); return 0; err_out_iounmap_fb: iounmap(info->screen_base); err_out_free_base1: fb_destroy_modedb(info->monspecs.modedb); nvidia_delete_i2c_busses(par); err_out_arch: iounmap(par->REGS); err_out_free_base0: pci_release_regions(pd); err_out_enable: kfree(info->pixmap.addr); err_out_kfree: framebuffer_release(info); err_out: return -ENODEV; } static void nvidiafb_remove(struct pci_dev *pd) { struct fb_info *info = pci_get_drvdata(pd); struct nvidia_par *par = info->par; NVTRACE_ENTER(); unregister_framebuffer(info); nvidia_bl_exit(par); arch_phys_wc_del(par->wc_cookie); iounmap(info->screen_base); fb_destroy_modedb(info->monspecs.modedb); nvidia_delete_i2c_busses(par); iounmap(par->REGS); pci_release_regions(pd); kfree(info->pixmap.addr); framebuffer_release(info); NVTRACE_LEAVE(); } /* ------------------------------------------------------------------------- * * * initialization * * ------------------------------------------------------------------------- */ #ifndef MODULE static int nvidiafb_setup(char *options) { char *this_opt; NVTRACE_ENTER(); if (!options || !*options) return 0; while ((this_opt = strsep(&options, ",")) != NULL) { if (!strncmp(this_opt, "forceCRTC", 9)) { char *p; p = this_opt + 9; if (!*p || !*(++p)) continue; forceCRTC = *p - '0'; if (forceCRTC < 0 || forceCRTC > 1) forceCRTC = -1; } else if (!strncmp(this_opt, "flatpanel", 9)) { flatpanel = 1; } else if (!strncmp(this_opt, "hwcur", 5)) { hwcur = 1; } else if (!strncmp(this_opt, "noaccel", 6)) { noaccel = 1; } else if (!strncmp(this_opt, "noscale", 7)) { noscale = 1; } else if (!strncmp(this_opt, "reverse_i2c", 11)) { reverse_i2c = 1; } else if (!strncmp(this_opt, "paneltweak:", 11)) { paneltweak = simple_strtoul(this_opt+11, NULL, 0); } else if (!strncmp(this_opt, "vram:", 5)) { vram = simple_strtoul(this_opt+5, NULL, 0); } else if (!strncmp(this_opt, "backlight:", 10)) { backlight = simple_strtoul(this_opt+10, NULL, 0); } else if (!strncmp(this_opt, "nomtrr", 6)) { nomtrr = true; } else if (!strncmp(this_opt, "fpdither:", 9)) { fpdither = simple_strtol(this_opt+9, NULL, 0); } else if (!strncmp(this_opt, "bpp:", 4)) { bpp = simple_strtoul(this_opt+4, NULL, 0); } else mode_option = this_opt; } NVTRACE_LEAVE(); return 0; } #endif /* !MODULE */ static struct pci_driver nvidiafb_driver = { .name = "nvidiafb", .id_table = nvidiafb_pci_tbl, .probe = nvidiafb_probe, .suspend = nvidiafb_suspend, .resume = nvidiafb_resume, .remove = nvidiafb_remove, }; /* ------------------------------------------------------------------------- * * * modularization * * ------------------------------------------------------------------------- */ static int nvidiafb_init(void) { #ifndef MODULE char *option = NULL; if (fb_get_options("nvidiafb", &option)) return -ENODEV; nvidiafb_setup(option); #endif return pci_register_driver(&nvidiafb_driver); } module_init(nvidiafb_init); static void __exit nvidiafb_exit(void) { pci_unregister_driver(&nvidiafb_driver); } module_exit(nvidiafb_exit); module_param(flatpanel, int, 0); MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. " "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); module_param(fpdither, int, 0); MODULE_PARM_DESC(fpdither, "Enables dithering of flat panel for 6 bits panels. " "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); module_param(hwcur, int, 0); MODULE_PARM_DESC(hwcur, "Enables hardware cursor implementation. (0 or 1=enabled) " "(default=0)"); module_param(noaccel, int, 0); MODULE_PARM_DESC(noaccel, "Disables hardware acceleration. (0 or 1=disable) " "(default=0)"); module_param(noscale, int, 0); MODULE_PARM_DESC(noscale, "Disables screen scaling. (0 or 1=disable) " "(default=0, do scaling)"); module_param(paneltweak, int, 0); MODULE_PARM_DESC(paneltweak, "Tweak display settings for flatpanels. " "(default=0, no tweaks)"); module_param(forceCRTC, int, 0); MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection " "fails. (0 or 1) (default=autodetect)"); module_param(vram, int, 0); MODULE_PARM_DESC(vram, "amount of framebuffer memory to remap in MiB" "(default=0 - remap entire memory)"); module_param(mode_option, charp, 0); MODULE_PARM_DESC(mode_option, "Specify initial video mode"); module_param(bpp, int, 0); MODULE_PARM_DESC(bpp, "pixel width in bits" "(default=8)"); module_param(reverse_i2c, int, 0); MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus"); module_param(nomtrr, bool, false); MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) " "(default=0)"); MODULE_AUTHOR("Antonino Daplas"); MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset"); MODULE_LICENSE("GPL");