summaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
blob: b1288f56d5095b4ad782e81b0453c9094ec47ac1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
/*
 * DM81xx hwmod data.
 *
 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <plat/dmtimer.h>

#include "omap_hwmod_common_data.h"
#include "cm81xx.h"
#include "ti81xx.h"
#include "wd_timer.h"

/*
 * DM816X hardware modules integration data
 *
 * Note: This is incomplete and at present, not generated from h/w database.
 */

/*
 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400.
 */
#define DM81XX_CM_ALWON_MCASP0_CLKCTRL		0x140
#define DM81XX_CM_ALWON_MCASP1_CLKCTRL		0x144
#define DM81XX_CM_ALWON_MCASP2_CLKCTRL		0x148
#define DM81XX_CM_ALWON_MCBSP_CLKCTRL		0x14c
#define DM81XX_CM_ALWON_UART_0_CLKCTRL		0x150
#define DM81XX_CM_ALWON_UART_1_CLKCTRL		0x154
#define DM81XX_CM_ALWON_UART_2_CLKCTRL		0x158
#define DM81XX_CM_ALWON_GPIO_0_CLKCTRL		0x15c
#define DM81XX_CM_ALWON_GPIO_1_CLKCTRL		0x160
#define DM81XX_CM_ALWON_I2C_0_CLKCTRL		0x164
#define DM81XX_CM_ALWON_I2C_1_CLKCTRL		0x168
#define DM81XX_CM_ALWON_WDTIMER_CLKCTRL		0x18c
#define DM81XX_CM_ALWON_SPI_CLKCTRL		0x190
#define DM81XX_CM_ALWON_MAILBOX_CLKCTRL		0x194
#define DM81XX_CM_ALWON_SPINBOX_CLKCTRL		0x198
#define DM81XX_CM_ALWON_MMUDATA_CLKCTRL		0x19c
#define DM81XX_CM_ALWON_MMUCFG_CLKCTRL		0x1a8
#define DM81XX_CM_ALWON_CONTROL_CLKCTRL		0x1c4
#define DM81XX_CM_ALWON_GPMC_CLKCTRL		0x1d0
#define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL	0x1d4
#define DM81XX_CM_ALWON_L3_CLKCTRL		0x1e4
#define DM81XX_CM_ALWON_L4HS_CLKCTRL		0x1e8
#define DM81XX_CM_ALWON_L4LS_CLKCTRL		0x1ec
#define DM81XX_CM_ALWON_RTC_CLKCTRL		0x1f0
#define DM81XX_CM_ALWON_TPCC_CLKCTRL		0x1f4
#define DM81XX_CM_ALWON_TPTC0_CLKCTRL		0x1f8
#define DM81XX_CM_ALWON_TPTC1_CLKCTRL		0x1fc
#define DM81XX_CM_ALWON_TPTC2_CLKCTRL		0x200
#define DM81XX_CM_ALWON_TPTC3_CLKCTRL		0x204

/* Registers specific to dm814x */
#define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL	0x16c
#define DM814X_CM_ALWON_ATL_CLKCTRL		0x170
#define DM814X_CM_ALWON_MLB_CLKCTRL		0x174
#define DM814X_CM_ALWON_PATA_CLKCTRL		0x178
#define DM814X_CM_ALWON_UART_3_CLKCTRL		0x180
#define DM814X_CM_ALWON_UART_4_CLKCTRL		0x184
#define DM814X_CM_ALWON_UART_5_CLKCTRL		0x188
#define DM814X_CM_ALWON_OCM_0_CLKCTRL		0x1b4
#define DM814X_CM_ALWON_VCP_CLKCTRL		0x1b8
#define DM814X_CM_ALWON_MPU_CLKCTRL		0x1dc
#define DM814X_CM_ALWON_DEBUGSS_CLKCTRL		0x1e0
#define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL	0x218
#define DM814X_CM_ALWON_MMCHS_0_CLKCTRL		0x21c
#define DM814X_CM_ALWON_MMCHS_1_CLKCTRL		0x220
#define DM814X_CM_ALWON_MMCHS_2_CLKCTRL		0x224
#define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL	0x228

/* Registers specific to dm816x */
#define DM816X_DM_ALWON_BASE		0x1400
#define DM816X_CM_ALWON_TIMER_1_CLKCTRL	(0x1570 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_2_CLKCTRL	(0x1574 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_3_CLKCTRL	(0x1578 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_4_CLKCTRL	(0x157c - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_5_CLKCTRL	(0x1580 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_6_CLKCTRL	(0x1584 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_TIMER_7_CLKCTRL	(0x1588 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_SDIO_CLKCTRL	(0x15b0 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_OCMC_0_CLKCTRL	(0x15b4 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_OCMC_1_CLKCTRL	(0x15b8 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_MPU_CLKCTRL	(0x15dc - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_SR_0_CLKCTRL	(0x1608 - DM816X_DM_ALWON_BASE)
#define DM816X_CM_ALWON_SR_1_CLKCTRL	(0x160c - DM816X_DM_ALWON_BASE)

/*
 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500
 */
#define DM816X_CM_DEFAULT_OFFSET	0x500
#define DM816X_CM_DEFAULT_USB_CLKCTRL	(0x558 - DM816X_CM_DEFAULT_OFFSET)

/* L3 Interconnect entries clocked at 125, 250 and 500MHz */
static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = {
	.name		= "alwon_l3_slow",
	.clkdm_name	= "alwon_l3s_clkdm",
	.class		= &l3_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

static struct omap_hwmod dm81xx_default_l3_slow_hwmod = {
	.name		= "default_l3_slow",
	.clkdm_name	= "default_l3_slow_clkdm",
	.class		= &l3_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = {
	.name		= "l3_med",
	.clkdm_name	= "alwon_l3_med_clkdm",
	.class		= &l3_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = {
	.name		= "l3_fast",
	.clkdm_name	= "alwon_l3_fast_clkdm",
	.class		= &l3_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

/*
 * L4 standard peripherals, see TRM table 1-12 for devices using this.
 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock.
 */
static struct omap_hwmod dm81xx_l4_ls_hwmod = {
	.name		= "l4_ls",
	.clkdm_name	= "alwon_l3s_clkdm",
	.class		= &l4_hwmod_class,
};

/*
 * L4 high-speed peripherals. For devices using this, please see the TRM
 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM
 * table 1-73 for devices using 250MHz SYSCLK5 clock.
 */
static struct omap_hwmod dm81xx_l4_hs_hwmod = {
	.name		= "l4_hs",
	.clkdm_name	= "alwon_l3_med_clkdm",
	.class		= &l4_hwmod_class,
};

/* L3 slow -> L4 ls peripheral interface running at 125MHz */
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = {
	.master	= &dm81xx_alwon_l3_slow_hwmod,
	.slave	= &dm81xx_l4_ls_hwmod,
	.user	= OCP_USER_MPU,
};

/* L3 med -> L4 fast peripheral interface running at 250MHz */
static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = {
	.master	= &dm81xx_alwon_l3_med_hwmod,
	.slave	= &dm81xx_l4_hs_hwmod,
	.user	= OCP_USER_MPU,
};

/* MPU */
static struct omap_hwmod dm814x_mpu_hwmod = {
	.name		= "mpu",
	.clkdm_name	= "alwon_l3s_clkdm",
	.class		= &mpu_hwmod_class,
	.flags		= HWMOD_INIT_NO_IDLE,
	.main_clk	= "mpu_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = {
	.master		= &dm814x_mpu_hwmod,
	.slave		= &dm81xx_alwon_l3_slow_hwmod,
	.user		= OCP_USER_MPU,
};

/* L3 med peripheral interface running at 200MHz */
static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = {
	.master	= &dm814x_mpu_hwmod,
	.slave	= &dm81xx_alwon_l3_med_hwmod,
	.user	= OCP_USER_MPU,
};

static struct omap_hwmod dm816x_mpu_hwmod = {
	.name		= "mpu",
	.clkdm_name	= "alwon_mpu_clkdm",
	.class		= &mpu_hwmod_class,
	.flags		= HWMOD_INIT_NO_IDLE,
	.main_clk	= "mpu_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = {
	.master		= &dm816x_mpu_hwmod,
	.slave		= &dm81xx_alwon_l3_slow_hwmod,
	.user		= OCP_USER_MPU,
};

/* L3 med peripheral interface running at 250MHz */
static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = {
	.master	= &dm816x_mpu_hwmod,
	.slave	= &dm81xx_alwon_l3_med_hwmod,
	.user	= OCP_USER_MPU,
};

/* UART common */
static struct omap_hwmod_class_sysconfig uart_sysc = {
	.rev_offs	= 0x50,
	.sysc_offs	= 0x54,
	.syss_offs	= 0x58,
	.sysc_flags	= SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
				SYSS_HAS_RESET_STATUS,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
				MSTANDBY_SMART_WKUP,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class uart_class = {
	.name = "uart",
	.sysc = &uart_sysc,
};

static struct omap_hwmod dm81xx_uart1_hwmod = {
	.name		= "uart1",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk10_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.class		= &uart_class,
	.flags		= DEBUG_TI81XXUART1_FLAGS,
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_uart1_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm81xx_uart2_hwmod = {
	.name		= "uart2",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk10_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.class		= &uart_class,
	.flags		= DEBUG_TI81XXUART2_FLAGS,
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_uart2_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm81xx_uart3_hwmod = {
	.name		= "uart3",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk10_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.class		= &uart_class,
	.flags		= DEBUG_TI81XXUART3_FLAGS,
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_uart3_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_class_sysconfig wd_timer_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x10,
	.syss_offs	= 0x14,
	.sysc_flags	= SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
				SYSS_HAS_RESET_STATUS,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class wd_timer_class = {
	.name		= "wd_timer",
	.sysc		= &wd_timer_sysc,
	.pre_shutdown	= &omap2_wd_timer_disable,
	.reset		= &omap2_wd_timer_reset,
};

static struct omap_hwmod dm81xx_wd_timer_hwmod = {
	.name		= "wd_timer",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk18_ck",
	.flags		= HWMOD_NO_IDLEST,
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.class		= &wd_timer_class,
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_wd_timer_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

/* I2C common */
static struct omap_hwmod_class_sysconfig i2c_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x10,
	.syss_offs	= 0x90,
	.sysc_flags	= SYSC_HAS_SIDLEMODE |
				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
				SYSC_HAS_AUTOIDLE,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class i2c_class = {
	.name = "i2c",
	.sysc = &i2c_sysc,
};

static struct omap_hwmod dm81xx_i2c1_hwmod = {
	.name		= "i2c1",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk10_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.class		= &i2c_class,
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_i2c1_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm81xx_i2c2_hwmod = {
	.name		= "i2c2",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk10_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.class		= &i2c_class,
};

static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
				SYSC_HAS_SOFTRESET |
				SYSS_HAS_RESET_STATUS,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_i2c2_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_class dm81xx_elm_hwmod_class = {
	.name = "elm",
	.sysc = &dm81xx_elm_sysc,
};

static struct omap_hwmod dm81xx_elm_hwmod = {
	.name		= "elm",
	.clkdm_name	= "alwon_l3s_clkdm",
	.class		= &dm81xx_elm_hwmod_class,
	.main_clk	= "sysclk6_ck",
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_elm_hwmod,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0114,
	.sysc_flags	= SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
				SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
				SYSS_HAS_RESET_STATUS,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
				SIDLE_SMART_WKUP,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dm81xx_gpio_hwmod_class = {
	.name	= "gpio",
	.sysc	= &dm81xx_gpio_sysc,
	.rev	= 2,
};

static struct omap_gpio_dev_attr gpio_dev_attr = {
	.bank_width	= 32,
	.dbck_flag	= true,
};

static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
	{ .role = "dbclk", .clk = "sysclk18_ck" },
};

static struct omap_hwmod dm81xx_gpio1_hwmod = {
	.name		= "gpio1",
	.clkdm_name	= "alwon_l3s_clkdm",
	.class		= &dm81xx_gpio_hwmod_class,
	.main_clk	= "sysclk6_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= gpio1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_gpio1_hwmod,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
	{ .role = "dbclk", .clk = "sysclk18_ck" },
};

static struct omap_hwmod dm81xx_gpio2_hwmod = {
	.name		= "gpio2",
	.clkdm_name	= "alwon_l3s_clkdm",
	.class		= &dm81xx_gpio_hwmod_class,
	.main_clk	= "sysclk6_ck",
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.opt_clks	= gpio2_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
	.dev_attr	= &gpio_dev_attr,
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_gpio2_hwmod,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x10,
	.syss_offs	= 0x14,
	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = {
	.name	= "gpmc",
	.sysc	= &dm81xx_gpmc_sysc,
};

static struct omap_hwmod dm81xx_gpmc_hwmod = {
	.name		= "gpmc",
	.clkdm_name	= "alwon_l3s_clkdm",
	.class		= &dm81xx_gpmc_hwmod_class,
	.main_clk	= "sysclk6_ck",
	/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
	.flags		= DEBUG_OMAP_GPMC_HWMOD_FLAGS,
	.prcm = {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = {
	.master		= &dm81xx_alwon_l3_slow_hwmod,
	.slave		= &dm81xx_gpmc_hwmod,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x10,
	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
				SYSC_HAS_SOFTRESET,
	.idlemodes	= SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART,
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dm81xx_usbotg_class = {
	.name = "usbotg",
	.sysc = &dm81xx_usbhsotg_sysc,
};

static struct omap_hwmod dm81xx_usbss_hwmod = {
	.name		= "usb_otg_hs",
	.clkdm_name	= "default_l3_slow_clkdm",
	.main_clk	= "sysclk6_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.class		= &dm81xx_usbotg_class,
};

static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = {
	.master		= &dm81xx_default_l3_slow_hwmod,
	.slave		= &dm81xx_usbss_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = {
	.rev_offs	= 0x0000,
	.sysc_offs	= 0x0010,
	.syss_offs	= 0x0014,
	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
				SIDLE_SMART_WKUP,
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dm816x_timer_hwmod_class = {
	.name = "timer",
	.sysc = &dm816x_timer_sysc,
};

static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
	.timer_capability	= OMAP_TIMER_ALWON,
};

static struct omap_hwmod dm814x_timer1_hwmod = {
	.name		= "timer1",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "timer_sys_ck",
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &dm816x_timer_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm814x_timer1_hwmod,
	.clk		= "timer_sys_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm816x_timer1_hwmod = {
	.name		= "timer1",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "timer1_fck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &dm816x_timer_hwmod_class,
};

static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm816x_timer1_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm814x_timer2_hwmod = {
	.name		= "timer2",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "timer_sys_ck",
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &dm816x_timer_hwmod_class,
	.flags		= HWMOD_NO_IDLEST,
};

static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm814x_timer2_hwmod,
	.clk		= "timer_sys_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm816x_timer2_hwmod = {
	.name		= "timer2",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "timer2_fck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &dm816x_timer_hwmod_class,
};

static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm816x_timer2_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm816x_timer3_hwmod = {
	.name		= "timer3",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "timer3_fck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &dm816x_timer_hwmod_class,
};

static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm816x_timer3_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm816x_timer4_hwmod = {
	.name		= "timer4",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "timer4_fck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &dm816x_timer_hwmod_class,
};

static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm816x_timer4_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm816x_timer5_hwmod = {
	.name		= "timer5",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "timer5_fck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &dm816x_timer_hwmod_class,
};

static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm816x_timer5_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm816x_timer6_hwmod = {
	.name		= "timer6",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "timer6_fck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &dm816x_timer_hwmod_class,
};

static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm816x_timer6_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm816x_timer7_hwmod = {
	.name		= "timer7",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "timer7_fck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &capability_alwon_dev_attr,
	.class		= &dm816x_timer_hwmod_class,
};

static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm816x_timer7_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

/* CPSW on dm814x */
static struct omap_hwmod_class_sysconfig dm814x_cpgmac_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x8,
	.syss_offs	= 0x4,
	.sysc_flags	= SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
			  SYSS_HAS_RESET_STATUS,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
			  MSTANDBY_NO,
	.sysc_fields	= &omap_hwmod_sysc_type3,
};

static struct omap_hwmod_class dm814x_cpgmac0_hwmod_class = {
	.name		= "cpgmac0",
	.sysc		= &dm814x_cpgmac_sysc,
};

static struct omap_hwmod dm814x_cpgmac0_hwmod = {
	.name		= "cpgmac0",
	.class		= &dm814x_cpgmac0_hwmod_class,
	.clkdm_name	= "alwon_ethernet_clkdm",
	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
	.main_clk	= "cpsw_125mhz_gclk",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_class dm814x_mdio_hwmod_class = {
	.name		= "davinci_mdio",
};

static struct omap_hwmod dm814x_mdio_hwmod = {
	.name		= "davinci_mdio",
	.class		= &dm814x_mdio_hwmod_class,
	.clkdm_name	= "alwon_ethernet_clkdm",
	.main_clk	= "cpsw_125mhz_gclk",
};

static struct omap_hwmod_ocp_if dm814x_l4_hs__cpgmac0 = {
	.master		= &dm81xx_l4_hs_hwmod,
	.slave		= &dm814x_cpgmac0_hwmod,
	.clk		= "cpsw_125mhz_gclk",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if dm814x_cpgmac0__mdio = {
	.master		= &dm814x_cpgmac0_hwmod,
	.slave		= &dm814x_mdio_hwmod,
	.user		= OCP_USER_MPU,
	.flags		= HWMOD_NO_IDLEST,
};

/* EMAC Ethernet */
static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x4,
	.sysc_flags	= SYSC_HAS_SOFTRESET,
	.sysc_fields	= &omap_hwmod_sysc_type2,
};

static struct omap_hwmod_class dm816x_emac_hwmod_class = {
	.name		= "emac",
	.sysc		= &dm816x_emac_sysc,
};

/*
 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate
 * driver probed before EMAC0, we let MDIO do the clock idling.
 */
static struct omap_hwmod dm816x_emac0_hwmod = {
	.name		= "emac0",
	.clkdm_name	= "alwon_ethernet_clkdm",
	.class		= &dm816x_emac_hwmod_class,
};

static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = {
	.master		= &dm81xx_l4_hs_hwmod,
	.slave		= &dm816x_emac0_hwmod,
	.clk		= "sysclk5_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_class dm81xx_mdio_hwmod_class = {
	.name		= "davinci_mdio",
	.sysc		= &dm816x_emac_sysc,
};

static struct omap_hwmod dm81xx_emac0_mdio_hwmod = {
	.name		= "davinci_mdio",
	.class		= &dm81xx_mdio_hwmod_class,
	.clkdm_name	= "alwon_ethernet_clkdm",
	.main_clk	= "sysclk24_ck",
	.flags		= HWMOD_NO_IDLEST,
	/*
	 * REVISIT: This should be moved to the emac0_hwmod
	 * once we have a better way to handle device slaves.
	 */
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = {
	.master		= &dm81xx_l4_hs_hwmod,
	.slave		= &dm81xx_emac0_mdio_hwmod,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod dm816x_emac1_hwmod = {
	.name		= "emac1",
	.clkdm_name	= "alwon_ethernet_clkdm",
	.main_clk	= "sysclk24_ck",
	.flags		= HWMOD_NO_IDLEST,
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.class		= &dm816x_emac_hwmod_class,
};

static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = {
	.master		= &dm81xx_l4_hs_hwmod,
	.slave		= &dm816x_emac1_hwmod,
	.clk		= "sysclk5_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x110,
	.syss_offs	= 0x114,
	.sysc_flags	= SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dm816x_mmc_class = {
	.name = "mmc",
	.sysc = &dm816x_mmc_sysc,
};

static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = {
	{ .role = "dbck", .clk = "sysclk18_ck", },
};

static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
	.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
};

static struct omap_hwmod dm816x_mmc1_hwmod = {
	.name		= "mmc1",
	.clkdm_name	= "alwon_l3s_clkdm",
	.opt_clks	= dm816x_mmc1_opt_clks,
	.opt_clks_cnt	= ARRAY_SIZE(dm816x_mmc1_opt_clks),
	.main_clk	= "sysclk10_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.dev_attr	= &mmc1_dev_attr,
	.class		= &dm816x_mmc_class,
};

static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm816x_mmc1_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
	.flags		= OMAP_FIREWALL_L4
};

static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = {
	.rev_offs	= 0x0,
	.sysc_offs	= 0x110,
	.syss_offs	= 0x114,
	.sysc_flags	= SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
				SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dm816x_mcspi_class = {
	.name = "mcspi",
	.sysc = &dm816x_mcspi_sysc,
	.rev = OMAP3_MCSPI_REV,
};

static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = {
	.num_chipselect = 4,
};

static struct omap_hwmod dm81xx_mcspi1_hwmod = {
	.name		= "mcspi1",
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk10_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
	.class		= &dm816x_mcspi_class,
	.dev_attr	= &dm816x_mcspi1_dev_attr,
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_mcspi1_hwmod,
	.clk		= "sysclk6_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = {
	.rev_offs	= 0x000,
	.sysc_offs	= 0x010,
	.syss_offs	= 0x014,
	.sysc_flags	= SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
				SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE,
	.idlemodes	= SIDLE_FORCE | SIDLE_NO | SIDLE_SMART,
	.sysc_fields	= &omap_hwmod_sysc_type1,
};

static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = {
	.name = "mailbox",
	.sysc = &dm81xx_mailbox_sysc,
};

static struct omap_hwmod dm81xx_mailbox_hwmod = {
	.name		= "mailbox",
	.clkdm_name	= "alwon_l3s_clkdm",
	.class		= &dm81xx_mailbox_hwmod_class,
	.main_clk	= "sysclk6_ck",
	.prcm		= {
		.omap4 = {
			.clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL,
			.modulemode = MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = {
	.master		= &dm81xx_l4_ls_hwmod,
	.slave		= &dm81xx_mailbox_hwmod,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = {
	.name		= "tpcc",
};

static struct omap_hwmod dm81xx_tpcc_hwmod = {
	.name		= "tpcc",
	.class		= &dm81xx_tpcc_hwmod_class,
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk4_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= DM81XX_CM_ALWON_TPCC_CLKCTRL,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = {
	.master		= &dm81xx_alwon_l3_fast_hwmod,
	.slave		= &dm81xx_tpcc_hwmod,
	.clk		= "sysclk4_ck",
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = {
	{
		.pa_start	= 0x49800000,
		.pa_end		= 0x49800000 + SZ_8K - 1,
		.flags		= ADDR_TYPE_RT,
	},
	{ },
};

static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = {
	.name		= "tptc0",
};

static struct omap_hwmod dm81xx_tptc0_hwmod = {
	.name		= "tptc0",
	.class		= &dm81xx_tptc0_hwmod_class,
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk4_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC0_CLKCTRL,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = {
	.master		= &dm81xx_alwon_l3_fast_hwmod,
	.slave		= &dm81xx_tptc0_hwmod,
	.clk		= "sysclk4_ck",
	.addr		= dm81xx_tptc0_addr_space,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = {
	.master		= &dm81xx_tptc0_hwmod,
	.slave		= &dm81xx_alwon_l3_fast_hwmod,
	.clk		= "sysclk4_ck",
	.addr		= dm81xx_tptc0_addr_space,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = {
	{
		.pa_start	= 0x49900000,
		.pa_end		= 0x49900000 + SZ_8K - 1,
		.flags		= ADDR_TYPE_RT,
	},
	{ },
};

static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = {
	.name		= "tptc1",
};

static struct omap_hwmod dm81xx_tptc1_hwmod = {
	.name		= "tptc1",
	.class		= &dm81xx_tptc1_hwmod_class,
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk4_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC1_CLKCTRL,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = {
	.master		= &dm81xx_alwon_l3_fast_hwmod,
	.slave		= &dm81xx_tptc1_hwmod,
	.clk		= "sysclk4_ck",
	.addr		= dm81xx_tptc1_addr_space,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = {
	.master		= &dm81xx_tptc1_hwmod,
	.slave		= &dm81xx_alwon_l3_fast_hwmod,
	.clk		= "sysclk4_ck",
	.addr		= dm81xx_tptc1_addr_space,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = {
	{
		.pa_start	= 0x49a00000,
		.pa_end		= 0x49a00000 + SZ_8K - 1,
		.flags		= ADDR_TYPE_RT,
	},
	{ },
};

static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = {
	.name		= "tptc2",
};

static struct omap_hwmod dm81xx_tptc2_hwmod = {
	.name		= "tptc2",
	.class		= &dm81xx_tptc2_hwmod_class,
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk4_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC2_CLKCTRL,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = {
	.master		= &dm81xx_alwon_l3_fast_hwmod,
	.slave		= &dm81xx_tptc2_hwmod,
	.clk		= "sysclk4_ck",
	.addr		= dm81xx_tptc2_addr_space,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = {
	.master		= &dm81xx_tptc2_hwmod,
	.slave		= &dm81xx_alwon_l3_fast_hwmod,
	.clk		= "sysclk4_ck",
	.addr		= dm81xx_tptc2_addr_space,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = {
	{
		.pa_start	= 0x49b00000,
		.pa_end		= 0x49b00000 + SZ_8K - 1,
		.flags		= ADDR_TYPE_RT,
	},
	{ },
};

static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = {
	.name		= "tptc3",
};

static struct omap_hwmod dm81xx_tptc3_hwmod = {
	.name		= "tptc3",
	.class		= &dm81xx_tptc3_hwmod_class,
	.clkdm_name	= "alwon_l3s_clkdm",
	.main_clk	= "sysclk4_ck",
	.prcm		= {
		.omap4	= {
			.clkctrl_offs	= DM81XX_CM_ALWON_TPTC3_CLKCTRL,
			.modulemode	= MODULEMODE_SWCTRL,
		},
	},
};

static struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = {
	.master		= &dm81xx_alwon_l3_fast_hwmod,
	.slave		= &dm81xx_tptc3_hwmod,
	.clk		= "sysclk4_ck",
	.addr		= dm81xx_tptc3_addr_space,
	.user		= OCP_USER_MPU,
};

static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
	.master		= &dm81xx_tptc3_hwmod,
	.slave		= &dm81xx_alwon_l3_fast_hwmod,
	.clk		= "sysclk4_ck",
	.addr		= dm81xx_tptc3_addr_space,
	.user		= OCP_USER_MPU,
};

/*
 * REVISIT: Test and enable the following once clocks work:
 * dm81xx_l4_ls__gpio1
 * dm81xx_l4_ls__gpio2
 * dm81xx_l4_ls__mailbox
 * dm81xx_alwon_l3_slow__gpmc
 * dm81xx_default_l3_slow__usbss
 *
 * Also note that some devices share a single clkctrl_offs..
 * For example, i2c1 and 3 share one, and i2c2 and 4 share one.
 */
static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
	&dm814x_mpu__alwon_l3_slow,
	&dm814x_mpu__alwon_l3_med,
	&dm81xx_alwon_l3_slow__l4_ls,
	&dm81xx_alwon_l3_slow__l4_hs,
	&dm81xx_l4_ls__uart1,
	&dm81xx_l4_ls__uart2,
	&dm81xx_l4_ls__uart3,
	&dm81xx_l4_ls__wd_timer1,
	&dm81xx_l4_ls__i2c1,
	&dm81xx_l4_ls__i2c2,
	&dm81xx_l4_ls__elm,
	&dm81xx_l4_ls__mcspi1,
	&dm81xx_alwon_l3_fast__tpcc,
	&dm81xx_alwon_l3_fast__tptc0,
	&dm81xx_alwon_l3_fast__tptc1,
	&dm81xx_alwon_l3_fast__tptc2,
	&dm81xx_alwon_l3_fast__tptc3,
	&dm81xx_tptc0__alwon_l3_fast,
	&dm81xx_tptc1__alwon_l3_fast,
	&dm81xx_tptc2__alwon_l3_fast,
	&dm81xx_tptc3__alwon_l3_fast,
	&dm814x_l4_ls__timer1,
	&dm814x_l4_ls__timer2,
	&dm814x_l4_hs__cpgmac0,
	&dm814x_cpgmac0__mdio,
	NULL,
};

int __init dm814x_hwmod_init(void)
{
	omap_hwmod_init();
	return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs);
}

static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = {
	&dm816x_mpu__alwon_l3_slow,
	&dm816x_mpu__alwon_l3_med,
	&dm81xx_alwon_l3_slow__l4_ls,
	&dm81xx_alwon_l3_slow__l4_hs,
	&dm81xx_l4_ls__uart1,
	&dm81xx_l4_ls__uart2,
	&dm81xx_l4_ls__uart3,
	&dm81xx_l4_ls__wd_timer1,
	&dm81xx_l4_ls__i2c1,
	&dm81xx_l4_ls__i2c2,
	&dm81xx_l4_ls__gpio1,
	&dm81xx_l4_ls__gpio2,
	&dm81xx_l4_ls__elm,
	&dm816x_l4_ls__mmc1,
	&dm816x_l4_ls__timer1,
	&dm816x_l4_ls__timer2,
	&dm816x_l4_ls__timer3,
	&dm816x_l4_ls__timer4,
	&dm816x_l4_ls__timer5,
	&dm816x_l4_ls__timer6,
	&dm816x_l4_ls__timer7,
	&dm81xx_l4_ls__mcspi1,
	&dm81xx_l4_ls__mailbox,
	&dm81xx_l4_hs__emac0,
	&dm81xx_emac0__mdio,
	&dm816x_l4_hs__emac1,
	&dm81xx_alwon_l3_fast__tpcc,
	&dm81xx_alwon_l3_fast__tptc0,
	&dm81xx_alwon_l3_fast__tptc1,
	&dm81xx_alwon_l3_fast__tptc2,
	&dm81xx_alwon_l3_fast__tptc3,
	&dm81xx_tptc0__alwon_l3_fast,
	&dm81xx_tptc1__alwon_l3_fast,
	&dm81xx_tptc2__alwon_l3_fast,
	&dm81xx_tptc3__alwon_l3_fast,
	&dm81xx_alwon_l3_slow__gpmc,
	&dm81xx_default_l3_slow__usbss,
	NULL,
};

int __init dm816x_hwmod_init(void)
{
	omap_hwmod_init();
	return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs);
}