summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/exynos5250.dtsi
blob: 0a229fcd7acfdfff4e07b4359cf0c7776e510efc (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
/*
 * SAMSUNG EXYNOS5250 SoC device tree source
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
 * EXYNOS5250 based board files can include this file and provide
 * values for board specfic bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
 * additional nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <dt-bindings/clock/exynos5250.h>
#include "exynos5.dtsi"
#include "exynos5250-pinctrl.dtsi"

#include <dt-bindings/clock/exynos-audss-clk.h>

/ {
	compatible = "samsung,exynos5250", "samsung,exynos5";

	aliases {
		spi0 = &spi_0;
		spi1 = &spi_1;
		spi2 = &spi_2;
		gsc0 = &gsc_0;
		gsc1 = &gsc_1;
		gsc2 = &gsc_2;
		gsc3 = &gsc_3;
		mshc0 = &mmc_0;
		mshc1 = &mmc_1;
		mshc2 = &mmc_2;
		mshc3 = &mmc_3;
		i2c0 = &i2c_0;
		i2c1 = &i2c_1;
		i2c2 = &i2c_2;
		i2c3 = &i2c_3;
		i2c4 = &i2c_4;
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
		i2c7 = &i2c_7;
		i2c8 = &i2c_8;
		i2c9 = &i2c_9;
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		pinctrl3 = &pinctrl_3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1700000000>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			clock-frequency = <1700000000>;
		};
	};

	sysram@02020000 {
		compatible = "mmio-sram";
		reg = <0x02020000 0x30000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x02020000 0x30000>;

		smp-sysram@0 {
			compatible = "samsung,exynos4210-sysram";
			reg = <0x0 0x1000>;
		};

		smp-sysram@2f000 {
			compatible = "samsung,exynos4210-sysram-ns";
			reg = <0x2f000 0x1000>;
		};
	};

	pd_gsc: gsc-power-domain@10044000 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10044000 0x20>;
	};

	pd_mfc: mfc-power-domain@10044040 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10044040 0x20>;
	};

	clock: clock-controller@10010000 {
		compatible = "samsung,exynos5250-clock";
		reg = <0x10010000 0x30000>;
		#clock-cells = <1>;
	};

	clock_audss: audss-clock-controller@3810000 {
		compatible = "samsung,exynos5250-audss-clock";
		reg = <0x03810000 0x0C>;
		#clock-cells = <1>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
			 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
		clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
			     <1 14 0xf08>,
			     <1 11 0xf08>,
			     <1 10 0xf08>;
		/* Unfortunately we need this since some versions of U-Boot
		 * on Exynos don't set the CNTFRQ register, so we need the
		 * value from DT.
		 */
		clock-frequency = <24000000>;
	};

	mct@101C0000 {
		compatible = "samsung,exynos4210-mct";
		reg = <0x101C0000 0x800>;
		interrupt-controller;
		#interrups-cells = <2>;
		interrupt-parent = <&mct_map>;
		interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
			     <4 0>, <5 0>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
		clock-names = "fin_pll", "mct";

		mct_map: mct-map {
			#interrupt-cells = <2>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0x0 0 &combiner 23 3>,
					<0x1 0 &combiner 23 4>,
					<0x2 0 &combiner 25 2>,
					<0x3 0 &combiner 25 3>,
					<0x4 0 &gic 0 120 0>,
					<0x5 0 &gic 0 121 0>;
		};
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupt-parent = <&combiner>;
		interrupts = <1 2>, <22 4>;
	};

	pinctrl_0: pinctrl@11400000 {
		compatible = "samsung,exynos5250-pinctrl";
		reg = <0x11400000 0x1000>;
		interrupts = <0 46 0>;

		wakup_eint: wakeup-interrupt-controller {
			compatible = "samsung,exynos4210-wakeup-eint";
			interrupt-parent = <&gic>;
			interrupts = <0 32 0>;
		};
	};

	pinctrl_1: pinctrl@13400000 {
		compatible = "samsung,exynos5250-pinctrl";
		reg = <0x13400000 0x1000>;
		interrupts = <0 45 0>;
	};

	pinctrl_2: pinctrl@10d10000 {
		compatible = "samsung,exynos5250-pinctrl";
		reg = <0x10d10000 0x1000>;
		interrupts = <0 50 0>;
	};

	pinctrl_3: pinctrl@03860000 {
		compatible = "samsung,exynos5250-pinctrl";
		reg = <0x03860000 0x1000>;
		interrupts = <0 47 0>;
	};

	pmu_system_controller: system-controller@10040000 {
		compatible = "samsung,exynos5250-pmu", "syscon";
		reg = <0x10040000 0x5000>;
		clock-names = "clkout16";
		clocks = <&clock CLK_FIN_PLL>;
		#clock-cells = <1>;
	};

	sysreg_system_controller: syscon@10050000 {
		compatible = "samsung,exynos5-sysreg", "syscon";
		reg = <0x10050000 0x5000>;
	};

	watchdog@101D0000 {
		compatible = "samsung,exynos5250-wdt";
		reg = <0x101D0000 0x100>;
		interrupts = <0 42 0>;
		clocks = <&clock CLK_WDT>;
		clock-names = "watchdog";
		samsung,syscon-phandle = <&pmu_system_controller>;
	};

	g2d@10850000 {
		compatible = "samsung,exynos5250-g2d";
		reg = <0x10850000 0x1000>;
		interrupts = <0 91 0>;
		clocks = <&clock CLK_G2D>;
		clock-names = "fimg2d";
	};

	mfc: codec@11000000 {
		compatible = "samsung,mfc-v6";
		reg = <0x11000000 0x10000>;
		interrupts = <0 96 0>;
		samsung,power-domain = <&pd_mfc>;
		clocks = <&clock CLK_MFC>;
		clock-names = "mfc";
	};

	rtc: rtc@101E0000 {
		clocks = <&clock CLK_RTC>;
		clock-names = "rtc";
		status = "disabled";
	};

	tmu@10060000 {
		compatible = "samsung,exynos5250-tmu";
		reg = <0x10060000 0x100>;
		interrupts = <0 65 0>;
		clocks = <&clock CLK_TMU>;
		clock-names = "tmu_apbif";
	};

	serial@12C00000 {
		clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
		clock-names = "uart", "clk_uart_baud0";
	};

	serial@12C10000 {
		clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
		clock-names = "uart", "clk_uart_baud0";
	};

	serial@12C20000 {
		clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
		clock-names = "uart", "clk_uart_baud0";
	};

	serial@12C30000 {
		clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
		clock-names = "uart", "clk_uart_baud0";
	};

	sata: sata@122F0000 {
		compatible = "snps,dwc-ahci";
		samsung,sata-freq = <66>;
		reg = <0x122F0000 0x1ff>;
		interrupts = <0 115 0>;
		clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
		clock-names = "sata", "sclk_sata";
		phys = <&sata_phy>;
		phy-names = "sata-phy";
		status = "disabled";
	};

	sata_phy: sata-phy@12170000 {
		compatible = "samsung,exynos5250-sata-phy";
		reg = <0x12170000 0x1ff>;
		clocks = <&clock CLK_SATA_PHYCTRL>;
		clock-names = "sata_phyctrl";
		#phy-cells = <0>;
		samsung,syscon-phandle = <&pmu_system_controller>;
		status = "disabled";
	};

	i2c_0: i2c@12C60000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12C60000 0x100>;
		interrupts = <0 56 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C0>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_bus>;
		samsung,sysreg-phandle = <&sysreg_system_controller>;
		status = "disabled";
	};

	i2c_1: i2c@12C70000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12C70000 0x100>;
		interrupts = <0 57 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C1>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_bus>;
		samsung,sysreg-phandle = <&sysreg_system_controller>;
		status = "disabled";
	};

	i2c_2: i2c@12C80000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12C80000 0x100>;
		interrupts = <0 58 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C2>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2_bus>;
		samsung,sysreg-phandle = <&sysreg_system_controller>;
		status = "disabled";
	};

	i2c_3: i2c@12C90000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12C90000 0x100>;
		interrupts = <0 59 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C3>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3_bus>;
		samsung,sysreg-phandle = <&sysreg_system_controller>;
		status = "disabled";
	};

	i2c_4: i2c@12CA0000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12CA0000 0x100>;
		interrupts = <0 60 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C4>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c4_bus>;
		status = "disabled";
	};

	i2c_5: i2c@12CB0000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12CB0000 0x100>;
		interrupts = <0 61 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C5>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c5_bus>;
		status = "disabled";
	};

	i2c_6: i2c@12CC0000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12CC0000 0x100>;
		interrupts = <0 62 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C6>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c6_bus>;
		status = "disabled";
	};

	i2c_7: i2c@12CD0000 {
		compatible = "samsung,s3c2440-i2c";
		reg = <0x12CD0000 0x100>;
		interrupts = <0 63 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C7>;
		clock-names = "i2c";
		pinctrl-names = "default";
		pinctrl-0 = <&i2c7_bus>;
		status = "disabled";
	};

	i2c_8: i2c@12CE0000 {
		compatible = "samsung,s3c2440-hdmiphy-i2c";
		reg = <0x12CE0000 0x1000>;
		interrupts = <0 64 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_I2C_HDMI>;
		clock-names = "i2c";
		status = "disabled";
	};

	i2c_9: i2c@121D0000 {
                compatible = "samsung,exynos5-sata-phy-i2c";
                reg = <0x121D0000 0x100>;
                #address-cells = <1>;
                #size-cells = <0>;
		clocks = <&clock CLK_SATA_PHYI2C>;
		clock-names = "i2c";
		status = "disabled";
	};

	spi_0: spi@12d20000 {
		compatible = "samsung,exynos4210-spi";
		status = "disabled";
		reg = <0x12d20000 0x100>;
		interrupts = <0 66 0>;
		dmas = <&pdma0 5
			&pdma0 4>;
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
		clock-names = "spi", "spi_busclk0";
		pinctrl-names = "default";
		pinctrl-0 = <&spi0_bus>;
	};

	spi_1: spi@12d30000 {
		compatible = "samsung,exynos4210-spi";
		status = "disabled";
		reg = <0x12d30000 0x100>;
		interrupts = <0 67 0>;
		dmas = <&pdma1 5
			&pdma1 4>;
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
		clock-names = "spi", "spi_busclk0";
		pinctrl-names = "default";
		pinctrl-0 = <&spi1_bus>;
	};

	spi_2: spi@12d40000 {
		compatible = "samsung,exynos4210-spi";
		status = "disabled";
		reg = <0x12d40000 0x100>;
		interrupts = <0 68 0>;
		dmas = <&pdma0 7
			&pdma0 6>;
		dma-names = "tx", "rx";
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
		clock-names = "spi", "spi_busclk0";
		pinctrl-names = "default";
		pinctrl-0 = <&spi2_bus>;
	};

	mmc_0: mmc@12200000 {
		compatible = "samsung,exynos5250-dw-mshc";
		interrupts = <0 75 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x12200000 0x1000>;
		clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
		clock-names = "biu", "ciu";
		fifo-depth = <0x80>;
		status = "disabled";
	};

	mmc_1: mmc@12210000 {
		compatible = "samsung,exynos5250-dw-mshc";
		interrupts = <0 76 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x12210000 0x1000>;
		clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
		clock-names = "biu", "ciu";
		fifo-depth = <0x80>;
		status = "disabled";
	};

	mmc_2: mmc@12220000 {
		compatible = "samsung,exynos5250-dw-mshc";
		interrupts = <0 77 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x12220000 0x1000>;
		clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
		clock-names = "biu", "ciu";
		fifo-depth = <0x80>;
		status = "disabled";
	};

	mmc_3: mmc@12230000 {
		compatible = "samsung,exynos5250-dw-mshc";
		reg = <0x12230000 0x1000>;
		interrupts = <0 78 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
		clock-names = "biu", "ciu";
		fifo-depth = <0x80>;
		status = "disabled";
	};

	i2s0: i2s@03830000 {
		compatible = "samsung,s5pv210-i2s";
		status = "disabled";
		reg = <0x03830000 0x100>;
		dmas = <&pdma0 10
			&pdma0 9
			&pdma0 8>;
		dma-names = "tx", "rx", "tx-sec";
		clocks = <&clock_audss EXYNOS_I2S_BUS>,
			<&clock_audss EXYNOS_I2S_BUS>,
			<&clock_audss EXYNOS_SCLK_I2S>;
		clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
		samsung,idma-addr = <0x03000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_bus>;
	};

	i2s1: i2s@12D60000 {
		compatible = "samsung,s3c6410-i2s";
		status = "disabled";
		reg = <0x12D60000 0x100>;
		dmas = <&pdma1 12
			&pdma1 11>;
		dma-names = "tx", "rx";
		clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
		clock-names = "iis", "i2s_opclk0";
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1_bus>;
	};

	i2s2: i2s@12D70000 {
		compatible = "samsung,s3c6410-i2s";
		status = "disabled";
		reg = <0x12D70000 0x100>;
		dmas = <&pdma0 12
			&pdma0 11>;
		dma-names = "tx", "rx";
		clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
		clock-names = "iis", "i2s_opclk0";
		pinctrl-names = "default";
		pinctrl-0 = <&i2s2_bus>;
	};

	usb@12000000 {
		compatible = "samsung,exynos5250-dwusb3";
		clocks = <&clock CLK_USB3>;
		clock-names = "usbdrd30";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		usbdrd_dwc3: dwc3 {
			compatible = "synopsys,dwc3";
			reg = <0x12000000 0x10000>;
			interrupts = <0 72 0>;
			phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
			phy-names = "usb2-phy", "usb3-phy";
		};
	};

	usbdrd_phy: phy@12100000 {
		compatible = "samsung,exynos5250-usbdrd-phy";
		reg = <0x12100000 0x100>;
		clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
		clock-names = "phy", "ref";
		samsung,pmu-syscon = <&pmu_system_controller>;
		#phy-cells = <1>;
	};

	ehci: usb@12110000 {
		compatible = "samsung,exynos4210-ehci";
		reg = <0x12110000 0x100>;
		interrupts = <0 71 0>;

		clocks = <&clock CLK_USB2>;
		clock-names = "usbhost";
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			phys = <&usb2_phy_gen 1>;
		};
	};

	ohci: usb@12120000 {
		compatible = "samsung,exynos4210-ohci";
		reg = <0x12120000 0x100>;
		interrupts = <0 71 0>;

		clocks = <&clock CLK_USB2>;
		clock-names = "usbhost";
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
			reg = <0>;
			phys = <&usb2_phy_gen 1>;
		};
	};

	usb2_phy_gen: phy@12130000 {
		compatible = "samsung,exynos5250-usb2-phy";
		reg = <0x12130000 0x100>;
		clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
		clock-names = "phy", "ref";
		#phy-cells = <1>;
		samsung,sysreg-phandle = <&sysreg_system_controller>;
		samsung,pmureg-phandle = <&pmu_system_controller>;
	};

	pwm: pwm@12dd0000 {
		compatible = "samsung,exynos4210-pwm";
		reg = <0x12dd0000 0x100>;
		samsung,pwm-outputs = <0>, <1>, <2>, <3>;
		#pwm-cells = <3>;
		clocks = <&clock CLK_PWM>;
		clock-names = "timers";
	};

	amba {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "arm,amba-bus";
		interrupt-parent = <&gic>;
		ranges;

		pdma0: pdma@121A0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x121A0000 0x1000>;
			interrupts = <0 34 0>;
			clocks = <&clock CLK_PDMA0>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
		};

		pdma1: pdma@121B0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x121B0000 0x1000>;
			interrupts = <0 35 0>;
			clocks = <&clock CLK_PDMA1>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
		};

		mdma0: mdma@10800000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x10800000 0x1000>;
			interrupts = <0 33 0>;
			clocks = <&clock CLK_MDMA0>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <1>;
		};

		mdma1: mdma@11C10000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x11C10000 0x1000>;
			interrupts = <0 124 0>;
			clocks = <&clock CLK_MDMA1>;
			clock-names = "apb_pclk";
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <1>;
		};
	};

	gsc_0:  gsc@13e00000 {
		compatible = "samsung,exynos5-gsc";
		reg = <0x13e00000 0x1000>;
		interrupts = <0 85 0>;
		samsung,power-domain = <&pd_gsc>;
		clocks = <&clock CLK_GSCL0>;
		clock-names = "gscl";
	};

	gsc_1:  gsc@13e10000 {
		compatible = "samsung,exynos5-gsc";
		reg = <0x13e10000 0x1000>;
		interrupts = <0 86 0>;
		samsung,power-domain = <&pd_gsc>;
		clocks = <&clock CLK_GSCL1>;
		clock-names = "gscl";
	};

	gsc_2:  gsc@13e20000 {
		compatible = "samsung,exynos5-gsc";
		reg = <0x13e20000 0x1000>;
		interrupts = <0 87 0>;
		samsung,power-domain = <&pd_gsc>;
		clocks = <&clock CLK_GSCL2>;
		clock-names = "gscl";
	};

	gsc_3:  gsc@13e30000 {
		compatible = "samsung,exynos5-gsc";
		reg = <0x13e30000 0x1000>;
		interrupts = <0 88 0>;
		samsung,power-domain = <&pd_gsc>;
		clocks = <&clock CLK_GSCL3>;
		clock-names = "gscl";
	};

	hdmi: hdmi {
		compatible = "samsung,exynos4212-hdmi";
		reg = <0x14530000 0x70000>;
		interrupts = <0 95 0>;
		clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
			 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
			 <&clock CLK_MOUT_HDMI>;
		clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
				"sclk_hdmiphy", "mout_hdmi";
		samsung,syscon-phandle = <&pmu_system_controller>;
	};

	mixer {
		compatible = "samsung,exynos5250-mixer";
		reg = <0x14450000 0x10000>;
		interrupts = <0 94 0>;
		clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
		clock-names = "mixer", "sclk_hdmi";
	};

	dp_phy: video-phy@10040720 {
		compatible = "samsung,exynos5250-dp-video-phy";
		reg = <0x10040720 4>;
		#phy-cells = <0>;
	};

	dp: dp-controller@145B0000 {
		clocks = <&clock CLK_DP>;
		clock-names = "dp";
		phys = <&dp_phy>;
		phy-names = "dp";
	};

	fimd: fimd@14400000 {
		clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
		clock-names = "sclk_fimd", "fimd";
	};

	adc: adc@12D10000 {
		compatible = "samsung,exynos-adc-v1";
		reg = <0x12D10000 0x100>;
		interrupts = <0 106 0>;
		clocks = <&clock CLK_ADC>;
		clock-names = "adc";
		#io-channel-cells = <1>;
		io-channel-ranges;
		samsung,syscon-phandle = <&pmu_system_controller>;
		status = "disabled";
	};

	sss@10830000 {
		compatible = "samsung,exynos4210-secss";
		reg = <0x10830000 0x10000>;
		interrupts = <0 112 0>;
		clocks = <&clock CLK_SSS>;
		clock-names = "secss";
	};
};