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path: root/drivers/staging/comedi/drivers/mite.c
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Diffstat (limited to 'drivers/staging/comedi/drivers/mite.c')
-rw-r--r--drivers/staging/comedi/drivers/mite.c231
1 files changed, 121 insertions, 110 deletions
diff --git a/drivers/staging/comedi/drivers/mite.c b/drivers/staging/comedi/drivers/mite.c
index e652f3b270b1..188f58042746 100644
--- a/drivers/staging/comedi/drivers/mite.c
+++ b/drivers/staging/comedi/drivers/mite.c
@@ -64,6 +64,7 @@
MODULE_LICENSE("GPL");
struct mite_struct *mite_devices;
+EXPORT_SYMBOL(mite_devices);
#define TOP_OF_PAGE(x) ((x)|(~(PAGE_MASK)))
@@ -80,7 +81,7 @@ void mite_init(void)
mite = kzalloc(sizeof(*mite), GFP_KERNEL);
if (!mite) {
- printk("mite: allocation failed\n");
+ printk(KERN_ERR "mite: allocation failed\n");
pci_dev_put(pcidev);
return;
}
@@ -99,14 +100,14 @@ void mite_init(void)
static void dump_chip_signature(u32 csigr_bits)
{
- printk
- ("mite: version = %i, type = %i, mite mode = %i, interface mode = %i\n",
- mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
- mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
- printk
- ("mite: num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
- mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
- mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
+ printk(KERN_INFO "mite: version = %i, type = %i, mite mode = %i,"
+ "interface mode = %i\n",
+ mite_csigr_version(csigr_bits), mite_csigr_type(csigr_bits),
+ mite_csigr_mmode(csigr_bits), mite_csigr_imode(csigr_bits));
+ printk(KERN_INFO "mite: num channels = %i, write post fifo depth = %i,"
+ "wins = %i, iowins = %i\n",
+ mite_csigr_dmac(csigr_bits), mite_csigr_wpdep(csigr_bits),
+ mite_csigr_wins(csigr_bits), mite_csigr_iowins(csigr_bits));
}
unsigned mite_fifo_size(struct mite_struct *mite, unsigned channel)
@@ -126,7 +127,7 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
unsigned unknown_dma_burst_bits;
if (comedi_pci_enable(mite->pcidev, "mite")) {
- printk("error enabling mite and requesting io regions\n");
+ printk(KERN_ERR "error enabling mite and requesting io regions\n");
return -EIO;
}
pci_set_master(mite->pcidev);
@@ -135,27 +136,30 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
mite->mite_phys_addr = addr;
mite->mite_io_addr = ioremap(addr, PCI_MITE_SIZE);
if (!mite->mite_io_addr) {
- printk("failed to remap mite io memory address\n");
+ printk(KERN_ERR "Failed to remap mite io memory address\n");
return -ENOMEM;
}
- printk("MITE:0x%08llx mapped to %p ",
+ printk(KERN_INFO "MITE:0x%08llx mapped to %p ",
(unsigned long long)mite->mite_phys_addr, mite->mite_io_addr);
addr = pci_resource_start(mite->pcidev, 1);
mite->daq_phys_addr = addr;
length = pci_resource_len(mite->pcidev, 1);
- /* In case of a 660x board, DAQ size is 8k instead of 4k (see as shown by lspci output) */
+ /*
+ * In case of a 660x board, DAQ size is 8k instead of 4k
+ * (see as shown by lspci output)
+ */
mite->daq_io_addr = ioremap(mite->daq_phys_addr, length);
if (!mite->daq_io_addr) {
- printk("failed to remap daq io memory address\n");
+ printk(KERN_ERR "Failed to remap daq io memory address\n");
return -ENOMEM;
}
- printk("DAQ:0x%08llx mapped to %p\n",
+ printk(KERN_INFO "DAQ:0x%08llx mapped to %p\n",
(unsigned long long)mite->daq_phys_addr, mite->daq_io_addr);
if (use_iodwbsr_1) {
writel(0, mite->mite_io_addr + MITE_IODWBSR);
- printk("mite: using I/O Window Base Size register 1\n");
+ printk(KERN_INFO "mite: using I/O Window Base Size register 1\n");
writel(mite->daq_phys_addr | WENAB |
MITE_IODWBSR_1_WSIZE_bits(length),
mite->mite_io_addr + MITE_IODWBSR_1);
@@ -164,11 +168,12 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
writel(mite->daq_phys_addr | WENAB,
mite->mite_io_addr + MITE_IODWBSR);
}
- /* make sure dma bursts work. I got this from running a bus analyzer
- on a pxi-6281 and a pxi-6713. 6713 powered up with register value
- of 0x61f and bursts worked. 6281 powered up with register value of
- 0x1f and bursts didn't work. The NI windows driver reads the register,
- then does a bitwise-or of 0x600 with it and writes it back.
+ /*
+ * make sure dma bursts work. I got this from running a bus analyzer
+ * on a pxi-6281 and a pxi-6713. 6713 powered up with register value
+ * of 0x61f and bursts worked. 6281 powered up with register value of
+ * 0x1f and bursts didn't work. The NI windows driver reads the
+ * register, then does a bitwise-or of 0x600 with it and writes it back.
*/
unknown_dma_burst_bits =
readl(mite->mite_io_addr + MITE_UNKNOWN_DMA_BURST_REG);
@@ -179,9 +184,9 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
csigr_bits = readl(mite->mite_io_addr + MITE_CSIGR);
mite->num_channels = mite_csigr_dmac(csigr_bits);
if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
- printk
- ("mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
- mite->num_channels, MAX_MITE_DMA_CHANNELS);
+ printk(KERN_WARNING "mite: bug? chip claims to have %i dma "
+ "channels. Setting to %i.\n",
+ mite->num_channels, MAX_MITE_DMA_CHANNELS);
mite->num_channels = MAX_MITE_DMA_CHANNELS;
}
dump_chip_signature(csigr_bits);
@@ -194,16 +199,18 @@ int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1)
mite->mite_io_addr + MITE_CHCR(i));
}
mite->fifo_size = mite_fifo_size(mite, 0);
- printk("mite: fifo size is %i.\n", mite->fifo_size);
+ printk(KERN_INFO "mite: fifo size is %i.\n", mite->fifo_size);
mite->used = 1;
return 0;
}
+EXPORT_SYMBOL(mite_setup2);
int mite_setup(struct mite_struct *mite)
{
return mite_setup2(mite, 0);
}
+EXPORT_SYMBOL(mite_setup);
void mite_cleanup(void)
{
@@ -238,22 +245,23 @@ void mite_unsetup(struct mite_struct *mite)
mite->used = 0;
}
+EXPORT_SYMBOL(mite_unsetup);
void mite_list_devices(void)
{
struct mite_struct *mite, *next;
- printk("Available NI device IDs:");
+ printk(KERN_INFO "Available NI device IDs:");
if (mite_devices)
for (mite = mite_devices; mite; mite = next) {
next = mite->next;
- printk(" 0x%04x", mite_device_id(mite));
+ printk(KERN_INFO " 0x%04x", mite_device_id(mite));
if (mite->used)
- printk("(used)");
+ printk(KERN_INFO "(used)");
}
- printk("\n");
-
+ printk(KERN_INFO "\n");
}
+EXPORT_SYMBOL(mite_list_devices);
struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
struct
@@ -265,7 +273,9 @@ struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
unsigned long flags;
struct mite_channel *channel = NULL;
- /* spin lock so mite_release_channel can be called safely from interrupts */
+ /* spin lock so mite_release_channel can be called safely
+ * from interrupts
+ */
spin_lock_irqsave(&mite->lock, flags);
for (i = min_channel; i <= max_channel; ++i) {
if (mite->channel_allocated[i] == 0) {
@@ -278,6 +288,7 @@ struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
spin_unlock_irqrestore(&mite->lock, flags);
return channel;
}
+EXPORT_SYMBOL(mite_request_channel_in_range);
void mite_release_channel(struct mite_channel *mite_chan)
{
@@ -289,8 +300,10 @@ void mite_release_channel(struct mite_channel *mite_chan)
if (mite->channel_allocated[mite_chan->channel]) {
mite_dma_disarm(mite_chan);
mite_dma_reset(mite_chan);
-/* disable all channel's interrupts (do it after disarm/reset so
-MITE_CHCR reg isn't changed while dma is still active!) */
+ /*
+ * disable all channel's interrupts (do it after disarm/reset so
+ * MITE_CHCR reg isn't changed while dma is still active!)
+ */
writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
@@ -302,6 +315,7 @@ MITE_CHCR reg isn't changed while dma is still active!) */
}
spin_unlock_irqrestore(&mite->lock, flags);
}
+EXPORT_SYMBOL(mite_release_channel);
void mite_dma_arm(struct mite_channel *mite_chan)
{
@@ -310,8 +324,10 @@ void mite_dma_arm(struct mite_channel *mite_chan)
unsigned long flags;
MDPRINTK("mite_dma_arm ch%i\n", channel);
- /* memory barrier is intended to insure any twiddling with the buffer
- is done before writing to the mite to arm dma transfer */
+ /*
+ * memory barrier is intended to insure any twiddling with the buffer
+ * is done before writing to the mite to arm dma transfer
+ */
smp_mb();
/* arm */
chor = CHOR_START;
@@ -322,6 +338,7 @@ void mite_dma_arm(struct mite_channel *mite_chan)
spin_unlock_irqrestore(&mite->lock, flags);
/* mite_dma_tcr(mite, channel); */
}
+EXPORT_SYMBOL(mite_dma_arm);
/**************************************/
@@ -354,7 +371,7 @@ int mite_buf_change(struct mite_dma_descriptor_ring *ring,
n_links * sizeof(struct mite_dma_descriptor),
&ring->descriptors_dma_addr, GFP_KERNEL);
if (!ring->descriptors) {
- printk("mite: ring buffer allocation failed\n");
+ printk(KERN_ERR "mite: ring buffer allocation failed\n");
return -ENOMEM;
}
ring->n_links = n_links;
@@ -370,11 +387,14 @@ int mite_buf_change(struct mite_dma_descriptor_ring *ring,
}
ring->descriptors[n_links - 1].next =
cpu_to_le32(ring->descriptors_dma_addr);
- /* barrier is meant to insure that all the writes to the dma descriptors
- have completed before the dma controller is commanded to read them */
+ /*
+ * barrier is meant to insure that all the writes to the dma descriptors
+ * have completed before the dma controller is commanded to read them
+ */
smp_wmb();
return 0;
}
+EXPORT_SYMBOL(mite_buf_change);
void mite_prep_dma(struct mite_channel *mite_chan,
unsigned int num_device_bits, unsigned int num_memory_bits)
@@ -395,16 +415,19 @@ void mite_prep_dma(struct mite_channel *mite_chan,
* Link Complete Interrupt: interrupt every time a link
* in MITE_RING is completed. This can generate a lot of
* extra interrupts, but right now we update the values
- * of buf_int_ptr and buf_int_count at each interrupt. A
+ * of buf_int_ptr and buf_int_count at each interrupt. A
* better method is to poll the MITE before each user
* "read()" to calculate the number of bytes available.
*/
chcr |= CHCR_SET_LC_IE;
if (num_memory_bits == 32 && num_device_bits == 16) {
- /* Doing a combined 32 and 16 bit byteswap gets the 16 bit samples into the fifo in the right order.
- Tested doing 32 bit memory to 16 bit device transfers to the analog out of a pxi-6281,
- which has mite version = 1, type = 4. This also works for dma reads from the counters
- on e-series boards. */
+ /*
+ * Doing a combined 32 and 16 bit byteswap gets the 16 bit
+ * samples into the fifo in the right order. Tested doing 32 bit
+ * memory to 16 bit device transfers to the analog out of a
+ * pxi-6281, which has mite version = 1, type = 4. This also
+ * works for dma reads from the counters on e-series boards.
+ */
chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
}
if (mite_chan->dir == COMEDI_INPUT)
@@ -425,7 +448,8 @@ void mite_prep_dma(struct mite_channel *mite_chan,
mcr |= CR_PSIZE32;
break;
default:
- printk("mite: bug! invalid mem bit width for dma transfer\n");
+ printk(KERN_WARNING "mite: bug! invalid mem bit width for dma "
+ "transfer\n");
break;
}
writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel));
@@ -444,7 +468,8 @@ void mite_prep_dma(struct mite_channel *mite_chan,
dcr |= CR_PSIZE32;
break;
default:
- printk("mite: bug! invalid dev bit width for dma transfer\n");
+ printk(KERN_WARNING "mite: bug! invalid dev bit width for dma "
+ "transfer\n");
break;
}
writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel));
@@ -462,6 +487,7 @@ void mite_prep_dma(struct mite_channel *mite_chan,
MDPRINTK("exit mite_prep_dma\n");
}
+EXPORT_SYMBOL(mite_prep_dma);
u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
{
@@ -469,48 +495,53 @@ u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
return readl(mite->mite_io_addr + MITE_DAR(mite_chan->channel));
}
-u32 mite_bytes_in_transit(struct mite_channel * mite_chan)
+u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
{
struct mite_struct *mite = mite_chan->mite;
return readl(mite->mite_io_addr +
MITE_FCR(mite_chan->channel)) & 0x000000FF;
}
+EXPORT_SYMBOL(mite_bytes_in_transit);
-/* returns lower bound for number of bytes transferred from device to memory */
-u32 mite_bytes_written_to_memory_lb(struct mite_channel * mite_chan)
+/* returns lower bound for number of bytes transferred from device to memory */
+u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
{
u32 device_byte_count;
device_byte_count = mite_device_bytes_transferred(mite_chan);
return device_byte_count - mite_bytes_in_transit(mite_chan);
}
+EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
-/* returns upper bound for number of bytes transferred from device to memory */
-u32 mite_bytes_written_to_memory_ub(struct mite_channel * mite_chan)
+/* returns upper bound for number of bytes transferred from device to memory */
+u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
{
u32 in_transit_count;
in_transit_count = mite_bytes_in_transit(mite_chan);
return mite_device_bytes_transferred(mite_chan) - in_transit_count;
}
+EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
-/* returns lower bound for number of bytes read from memory for transfer to device */
-u32 mite_bytes_read_from_memory_lb(struct mite_channel * mite_chan)
+/* returns lower bound for number of bytes read from memory to device */
+u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
{
u32 device_byte_count;
device_byte_count = mite_device_bytes_transferred(mite_chan);
return device_byte_count + mite_bytes_in_transit(mite_chan);
}
+EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
-/* returns upper bound for number of bytes read from memory for transfer to device */
-u32 mite_bytes_read_from_memory_ub(struct mite_channel * mite_chan)
+/* returns upper bound for number of bytes read from memory to device */
+u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
{
u32 in_transit_count;
in_transit_count = mite_bytes_in_transit(mite_chan);
return mite_device_bytes_transferred(mite_chan) + in_transit_count;
}
+EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
unsigned mite_dma_tcr(struct mite_channel *mite_chan)
{
@@ -525,6 +556,7 @@ unsigned mite_dma_tcr(struct mite_channel *mite_chan)
return tcr;
}
+EXPORT_SYMBOL(mite_dma_tcr);
void mite_dma_disarm(struct mite_channel *mite_chan)
{
@@ -535,6 +567,7 @@ void mite_dma_disarm(struct mite_channel *mite_chan)
chor = CHOR_ABORT;
writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
}
+EXPORT_SYMBOL(mite_dma_disarm);
int mite_sync_input_dma(struct mite_channel *mite_chan,
struct comedi_async *async)
@@ -544,7 +577,7 @@ int mite_sync_input_dma(struct mite_channel *mite_chan,
const unsigned bytes_per_scan = cfc_bytes_per_scan(async->subdevice);
old_alloc_count = async->buf_write_alloc_count;
- /* write alloc as much as we can */
+ /* write alloc as much as we can */
comedi_buf_write_alloc(async, async->prealloc_bufsz);
nbytes = mite_bytes_written_to_memory_lb(mite_chan);
@@ -571,6 +604,7 @@ int mite_sync_input_dma(struct mite_channel *mite_chan,
async->events |= COMEDI_CB_BLOCK;
return 0;
}
+EXPORT_SYMBOL(mite_sync_input_dma);
int mite_sync_output_dma(struct mite_channel *mite_chan,
struct comedi_async *async)
@@ -593,7 +627,7 @@ int mite_sync_output_dma(struct mite_channel *mite_chan,
(int)(nbytes_ub - stop_count) > 0)
nbytes_ub = stop_count;
if ((int)(nbytes_ub - old_alloc_count) > 0) {
- printk("mite: DMA underrun\n");
+ printk(KERN_ERR "mite: DMA underrun\n");
async->events |= COMEDI_CB_OVERFLOW;
return -1;
}
@@ -607,6 +641,7 @@ int mite_sync_output_dma(struct mite_channel *mite_chan,
}
return 0;
}
+EXPORT_SYMBOL(mite_sync_output_dma);
unsigned mite_get_status(struct mite_channel *mite_chan)
{
@@ -625,6 +660,7 @@ unsigned mite_get_status(struct mite_channel *mite_chan)
spin_unlock_irqrestore(&mite->lock, flags);
return status;
}
+EXPORT_SYMBOL(mite_get_status);
int mite_done(struct mite_channel *mite_chan)
{
@@ -638,6 +674,7 @@ int mite_done(struct mite_channel *mite_chan)
spin_unlock_irqrestore(&mite->lock, flags);
return done;
}
+EXPORT_SYMBOL(mite_done);
#ifdef DEBUG_MITE
@@ -719,46 +756,51 @@ void mite_dump_regs(struct mite_channel *mite_chan)
unsigned long addr = 0;
unsigned long temp = 0;
- printk("mite_dump_regs ch%i\n", mite_chan->channel);
- printk("mite address is =0x%08lx\n", mite_io_addr);
+ printk(KERN_DEBUG "mite_dump_regs ch%i\n", mite_chan->channel);
+ printk(KERN_DEBUG "mite address is =0x%08lx\n", mite_io_addr);
addr = mite_io_addr + MITE_CHOR(channel);
- printk("mite status[CHOR]at 0x%08lx =0x%08lx\n", addr, temp =
- readl(addr));
+ printk(KERN_DEBUG "mite status[CHOR]at 0x%08lx =0x%08lx\n", addr,
+ temp = readl(addr));
mite_decode(mite_CHOR_strings, temp);
addr = mite_io_addr + MITE_CHCR(channel);
- printk("mite status[CHCR]at 0x%08lx =0x%08lx\n", addr, temp =
- readl(addr));
+ printk(KERN_DEBUG "mite status[CHCR]at 0x%08lx =0x%08lx\n", addr,
+ temp = readl(addr));
mite_decode(mite_CHCR_strings, temp);
addr = mite_io_addr + MITE_TCR(channel);
- printk("mite status[TCR] at 0x%08lx =0x%08x\n", addr, readl(addr));
- addr = mite_io_addr + MITE_MCR(channel);
- printk("mite status[MCR] at 0x%08lx =0x%08lx\n", addr, temp =
+ printk(KERN_DEBUG "mite status[TCR] at 0x%08lx =0x%08x\n", addr,
readl(addr));
+ addr = mite_io_addr + MITE_MCR(channel);
+ printk(KERN_DEBUG "mite status[MCR] at 0x%08lx =0x%08lx\n", addr,
+ temp = readl(addr));
mite_decode(mite_MCR_strings, temp);
addr = mite_io_addr + MITE_MAR(channel);
- printk("mite status[MAR] at 0x%08lx =0x%08x\n", addr, readl(addr));
- addr = mite_io_addr + MITE_DCR(channel);
- printk("mite status[DCR] at 0x%08lx =0x%08lx\n", addr, temp =
+ printk(KERN_DEBUG "mite status[MAR] at 0x%08lx =0x%08x\n", addr,
readl(addr));
+ addr = mite_io_addr + MITE_DCR(channel);
+ printk(KERN_DEBUG "mite status[DCR] at 0x%08lx =0x%08lx\n", addr,
+ temp = readl(addr));
mite_decode(mite_DCR_strings, temp);
addr = mite_io_addr + MITE_DAR(channel);
- printk("mite status[DAR] at 0x%08lx =0x%08x\n", addr, readl(addr));
- addr = mite_io_addr + MITE_LKCR(channel);
- printk("mite status[LKCR]at 0x%08lx =0x%08lx\n", addr, temp =
+ printk(KERN_DEBUG "mite status[DAR] at 0x%08lx =0x%08x\n", addr,
readl(addr));
+ addr = mite_io_addr + MITE_LKCR(channel);
+ printk(KERN_DEBUG "mite status[LKCR]at 0x%08lx =0x%08lx\n", addr,
+ temp = readl(addr));
mite_decode(mite_LKCR_strings, temp);
addr = mite_io_addr + MITE_LKAR(channel);
- printk("mite status[LKAR]at 0x%08lx =0x%08x\n", addr, readl(addr));
-
- addr = mite_io_addr + MITE_CHSR(channel);
- printk("mite status[CHSR]at 0x%08lx =0x%08lx\n", addr, temp =
+ printk(KERN_DEBUG "mite status[LKAR]at 0x%08lx =0x%08x\n", addr,
readl(addr));
+ addr = mite_io_addr + MITE_CHSR(channel);
+ printk(KERN_DEBUG "mite status[CHSR]at 0x%08lx =0x%08lx\n", addr,
+ temp = readl(addr));
mite_decode(mite_CHSR_strings, temp);
addr = mite_io_addr + MITE_FCR(channel);
- printk("mite status[FCR] at 0x%08lx =0x%08x\n\n", addr, readl(addr));
+ printk(KERN_DEBUG "mite status[FCR] at 0x%08lx =0x%08x\n\n", addr,
+ readl(addr));
}
+EXPORT_SYMBOL(mite_dump_regs);
static void mite_decode(char **bit_str, unsigned int bits)
{
@@ -766,10 +808,11 @@ static void mite_decode(char **bit_str, unsigned int bits)
for (i = 31; i >= 0; i--) {
if (bits & (1 << i))
- printk(" %s", bit_str[i]);
+ printk(KERN_DEBUG " %s", bit_str[i]);
}
- printk("\n");
+ printk(KERN_DEBUG "\n");
}
+EXPORT_SYMBOL(mite_decode);
#endif
#ifdef MODULE
@@ -785,36 +828,4 @@ void __exit cleanup_module(void)
{
mite_cleanup();
}
-
-EXPORT_SYMBOL(mite_dma_tcr);
-EXPORT_SYMBOL(mite_dma_arm);
-EXPORT_SYMBOL(mite_dma_disarm);
-EXPORT_SYMBOL(mite_sync_input_dma);
-EXPORT_SYMBOL(mite_sync_output_dma);
-EXPORT_SYMBOL(mite_setup);
-EXPORT_SYMBOL(mite_setup2);
-EXPORT_SYMBOL(mite_unsetup);
-#if 0
-EXPORT_SYMBOL(mite_kvmem_segment_load);
-EXPORT_SYMBOL(mite_ll_from_kvmem);
-EXPORT_SYMBOL(mite_setregs);
-#endif
-EXPORT_SYMBOL(mite_devices);
-EXPORT_SYMBOL(mite_list_devices);
-EXPORT_SYMBOL(mite_request_channel_in_range);
-EXPORT_SYMBOL(mite_release_channel);
-EXPORT_SYMBOL(mite_prep_dma);
-EXPORT_SYMBOL(mite_buf_change);
-EXPORT_SYMBOL(mite_bytes_written_to_memory_lb);
-EXPORT_SYMBOL(mite_bytes_written_to_memory_ub);
-EXPORT_SYMBOL(mite_bytes_read_from_memory_lb);
-EXPORT_SYMBOL(mite_bytes_read_from_memory_ub);
-EXPORT_SYMBOL(mite_bytes_in_transit);
-EXPORT_SYMBOL(mite_get_status);
-EXPORT_SYMBOL(mite_done);
-#ifdef DEBUG_MITE
-EXPORT_SYMBOL(mite_decode);
-EXPORT_SYMBOL(mite_dump_regs);
-#endif
-
#endif
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-09 10:15:11 +0000