Age | Commit message (Collapse) | Author |
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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commit a9ad21fed09cb95d34af9474be0831525b30c4c6 upstream.
When SMP_ON_UP is used and the spinlocks are inlined, we end up with
inline spinlocks in the exit code, with references from the SMP
alternatives section to the exit sections. This causes link time
errors. Avoid this by placing the exit sections in the init-discarded
region.
Tested-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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commit 53399053eb505cf541b2405bd9d9bca5ecfb96fb upstream.
Ensure a predictable endian state when entering signal handlers. This
avoids programs which use SETEND to momentarily switch their endian
state from having their signal handlers entered with an unpredictable
endian state.
Acked-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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commit 4f444e2b59dd4255d121b57ec41a4a8c5d6bce46 upstream.
Since commit 7a5b4e16c880f8350d255dc188f81622905618c1, simpad devices don't
boot anymore, since platform devices are registered too early. Fix by moving
the registration from map_io to arch_initcall as done on other sa1100 boards.
Signed-off-by: Jochen Friedrich <jochen@scram.de>
Acked-by: Kristoffer Ericson <kristoffer.ericson@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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commit d14dd7e20d5e526557f5d3cfef4046a642f80924 upstream.
Always allow backtraces when using oprofile on ARM, even if a PMU
isn't present. Restores functionality originally introduced in commit
1b7b56982fdcd9d85effd76f3928cf5d6eb26155 ("oprofile: Always allow
backtraces on ARM") by Richard Purdie.
It is not that obvious, but there is now only one oprofile_arch_init()
function. So the .backtrace callback is available also in timer mode.
Implemented by removing code and using stubs for oprofile_perf_{init,
exit} provided by <linux/oprofile.h>. This allows cleaning of other
architecture specific implementations too.
Signed-off-by: Ari Kauppi <kauppi@papupata.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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commit e98ff0f55a0232b578c9aa7f1c245868277ac7bc upstream.
Allow non-ARM SMP processors to use the SMP_ON_UP feature. CPUs
supporting SMP must have the new CPU ID format, so check for this first.
Then check for ARM11MPCore, which fails the MPIDR check. Lastly check
the MPIDR reports multiprocessing extensions and that the CPU is part of
a multiprocessing system.
Reported-and-Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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commit 0eb0511d176534674600a1986c3c766756288908 upstream.
Use r0,r3-r6 rather than r0,r3,r4,r6,r7, which makes it easier to
understand which registers can be modified. Also document which
registers hold values which must be preserved.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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commit b0a2679d27408d97ce31e5f800b44227d3388b84 upstream.
Disable the initrd if the passed address already overlaps the reserved
region. This avoids oopses on Netwinders when NeTTrom tells the kernel
that an initrd is located at mem+4MB, but this overlaps the BSS,
resulting in the kernels in-use BSS being freed.
This should be applied to v2.6.37-stable.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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commit a50eb1c7680973f5441ca20ac4da0af2055d0d87 upstream.
This patch is applied according to the commit 1a8e41cd672f894bbd74874eac601e6cedf838fb
(ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).
Actually, S5PV310 has same cache controller(PL310).
Following is from Catalin Marinas' commit.
Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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arm trace clock fix missing include
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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Be nice to perf by reserving the PMU before using the trace clock.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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Trace clock get may fail
ARM pmu reservation may fail, so we have to change the trace clock get
prototype.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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arm 32v6k fix comment 2-byte cmpxchg
commit ecd322c9b3e4ac70f9f108badde3eb6b99c7993d introduced a 2-byte cmpxchg with
a comment mismatch (labeled __cmpxchg1).
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
CC: Catalin Marinas <catalin.marinas@arm.com>
CC: Nicolas Pitre <nico@cam.org>
CC: Russell King <rmk+kernel@arm.linux.org.uk>
CC: Alexander Shishkin <virtuoso@slind.org>
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omap3 trace clock header moved to plat
Fixes:
CC arch/arm/mach-omap2/pm34xx.o
In file included from
/home/fabroy01/src/linux-2.6-lttng/arch/arm/include/asm/trace-clock.h:1,
from arch/arm/mach-omap2/pm34xx.c:45:
arch/arm/mach-omap2/include/mach/trace-clock.h:12: fatal error:
mach/clock.h: No such file or directory
compilation terminated.
Also updates the plat/ header including missing bits from the mach/ header.
Remove the now unused mach/ header to complete transition.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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omap fix disable timer missing declaration
Reported by: Jarkko Nikula
From: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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omap trace clock use del timer sync and raw_spinlock
Needed for RT kernels.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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arm trace clock use cpufreq get (v2)
> test.freq_change: 10.429663096 "prechange", oldfreq = 600000, newfreq =
> 125000, const = 0, quickfreq = 600000
> test.freq_change: 10.434801182 "postchange", oldfreq = 600000, newfreq =
> 125000, const = 0, quickfreq = 600000
Ah, yes, I think this explains our issue.
In arch/arm/mach-omap2/trace-clock.c:
cpufreq_trace_clock() calls resync_on_32k(pm_count, cpu) at
CPUFREQ_POSTCHANGE. This function expects cpufreq_quick_get() to return
the new frequency value rather than the old one (we're "post" frequency
change after all!). Here is a patch that only calls cpufreq_quick_get() when
returning from PM and tracing start, use the new frequency when called from
DVFS, and use the cached frequency when doing the periodic resync.
- Use the internally cached frequency value for periodic time resync.
- Use the new freq value upon dvfs frequency change.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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omap stop ccnt in idle
Let's play safe: don't assume the ccnt register is stopped while we are in
idle/sleep modes. Stop it ourself.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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omap move resync timer to cpufreq event
Remove a periodic timer to save energy.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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omap merge fix plat mach
Temporary fixup for integration from linux omap to mainline tree.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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OMAP move trace clock header to mach
Reported-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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OMAP debug trace clock
Test if trace clock runs backward.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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OMAP dvfs support
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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omap trace clock pm update
Update OMAP trace clock locking.
* Differs from omap tree *
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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omap : trace clock support pm
Support power management for omap trace clock.
- Updated for 2.6.32-rc8 kernel.
- Fix trace pm suspend exit (was a 2nd entry).
* Differs from omap tree *
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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arm trace clock update clocksource
* Differs from omap tree *
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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arm trace clock update include
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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OMAP trace clock fix
- fix interval for timer clearing the top bit.
- fix the read_ccnt() primitive to clear the top bit.
- Make the printk output only show once when clock is started, otherwise it is
shown at every return from idle.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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OMAP trace clock use spinlock
useful for power management
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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omap trace clock fix mutex
This is just a quick note to let you know that I think that the mutex in
kernel/trace/trace-clock-32-to-64.c might be incorrect or at least
incorrectly used.
I get these warnings with CONFIG_DEBUG_SPINLOCK_SLEEP, looks like irqs
are disabled when the mutex is locked/unlocked.
[ 174.994348] BUG: sleeping function called from invalid context at
kernel/mutex.c:207
[ 175.002283] in_atomic(): 1, irqs_disabled(): 0, pid: 1678, name:
lttctl
[ 175.009058] INFO: lockdep is turned off.
[ 175.013055] [<c0030628>] (dump_stack+0x0/0x14) from [<c004db20>]
(__might_sleep+0x108/0x128)
[ 175.021661] [<c004da18>] (__might_sleep+0x0/0x128) from [<c0275158>]
(mutex_lock_nested+0x28/0x2dc)
[ 175.030908] r4:c0885810
[ 175.033472] [<c0275130>] (mutex_lock_nested+0x0/0x2dc) from
[<c008e1e0>] (get_synthetic_tsc+0x1c/0xa4)
[ 175.042963] [<c008e1c4>] (get_synthetic_tsc+0x0/0xa4) from
[<c003e7b4>] (_start_trace_clock+0x108/0x16c)
[ 175.052667] r5:00000000 r4:00577f46
[ 175.056299] [<c003e6ac>] (_start_trace_clock+0x0/0x16c) from
[<c003e848>] (get_trace_clock+0x30/0x44)
[ 175.065668] [<c003e818>] (get_trace_clock+0x0/0x44) from [<c014b69c>]
(ltt_trace_alloc+0x60/0x3ac)
[ 175.074854] [<c014b63c>] (ltt_trace_alloc+0x0/0x3ac) from
[<c014e954>] (alloc_write+0xe8/0x128)
[ 175.083734] [<c014e86c>] (alloc_write+0x0/0x128) from [<c00b6b14>]
(vfs_write+0xbc/0x14c)
[ 175.092065] r6:c4f1df70 r5:4000c2c8 r4:c4e4f9a0
[ 175.096765] [<c00b6a58>] (vfs_write+0x0/0x14c) from [<c00b72d8>]
(sys_write+0x48/0xfc)
[ 175.104822] r7:00000001 r6:c4e4f9a0 r5:00000000 r4:00000000
[ 175.110615] [<c00b7290>] (sys_write+0x0/0xfc) from [<c002c8e0>]
(ret_fast_syscall+0x0/0x2c)
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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OMAP trace clock basic PM fix
This patch sets the whole trace clock when resynchronising with the 32k timer.
Just setting the cycle counter is not enough, because we would lose bits for
long sleeps.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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omap trace clock add write value
Allow update of trace clock after a long period of time.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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omap trace clock
Implement LTTng trace clock for omap. Should eventually make it so it can be
compiled-out, but that would imply fixing other architecture's trace clocks
too.
It only supports uniprocessor for now. IPIs would be needed to restore each
CPU's ccnt register in sync with the 32k clock upon resync_trace_clock to
support SMP.
Eventually, looking at how much time is lost lost when clearing the top
ccnt bit should be done, so we can compensate for the cycles lost.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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omap lttng statedump arm
Syscall table dump for arm.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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LTTng - ARM instrumentation
Changelog : fixed the syscall_exit return value.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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LTTng Kernel Trace Thread Flag ARM
Add a thread flag to activate system-wide syscall tracing.
folded omap-arm-fix-syscall-exit-trace-flag.patch.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
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New assemblers need -march=armv7-a+sec on command line or
.arch_extension sec inline to enable use of the smc instruction.
This patch uses as-instr to check the latter to conditionally
enable the former in AFLAGS for files that use smc.
Checked on both old and new binutils to verify that it does
not break old versions.
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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commit a5624323866c06156ca548b8515d9347fdd5188e angstrom-linux
EHCI enable power pin is inverted (active high) in comparison
to vanilla beagle which is active low. Handle this case conditionally.
Without this fix, Beagle XM 4 port EHCI will not function and no
networking will be available
[nm@ti.com: split up, added descriptive changelogs]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Koen Kooi <koen@beagleboard.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
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Before this patch, the following error would sometimes occur after a
resume on pxa3xx:
/path/to/mm/memory.c:144: bad pmd 8040542e.
The problem was that a temporary page table mapping was being improperly
restored.
The PXA3xx resume code creates a temporary mapping of resume_turn_on_mmu
to avoid a prefetch abort. The pxa3xx_resume_after_mmu code requires
that the r1 register holding the address of this mapping not be
modified, however, resume_turn_on_mmu does modify it. It is mostly
correct in that r1 receives the base table address, but it may also
get other bits in 13:0. This results in pxa3xx_resume_after_mmu
restoring the original mapping to the wrong place, corrupting memory
and leaving the temporary mapping in place.
Signed-off-by: Matt Reimer <mreimer@sdgsystems.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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The commit 6ac6b817f3f4c23c5febd960d8deb343e13af5f3 (ARM: pxa: encode
IRQ number into .nr_irqs) removed definition of ITE_LAST_IRQ which
caused the following build error:
CC arch/arm/common/it8152.o
arch/arm/common/it8152.c: In function 'it8152_init_irq':
arch/arm/common/it8152.c:86: error: 'IT8152_LAST_IRQ' undeclared (first use in this function)
arch/arm/common/it8152.c:86: error: (Each undeclared identifier is reported only once
arch/arm/common/it8152.c:86: error: for each function it appears in.)
make[2]: *** [arch/arm/common/it8152.o] Error 1
Defining the IT8152_LAST_IRQ in the arch/arm/include/hardware/it8152.c
fixes the build.
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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As arch/arm/mach-pxa/eseries.c references w100fb_gpio_{read,write}()
directly.
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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This patch fixes below build error by adding the missing asm/memory.h,
which is needed for arch_is_coherent().
$ make pxa3xx_defconfig; make
CC init/do_mounts_rd.o
In file included from include/linux/list_bl.h:5,
from include/linux/rculist_bl.h:7,
from include/linux/dcache.h:7,
from include/linux/fs.h:381,
from init/do_mounts_rd.c:3:
include/linux/bit_spinlock.h: In function 'bit_spin_unlock':
include/linux/bit_spinlock.h:61: error: implicit declaration of function 'arch_is_coherent'
make[1]: *** [init/do_mounts_rd.o] Error 1
make: *** [init] Error 2
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Peter Huewe <peterhuewe@gmx.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc:
mmc: Fix re-probing with PM_POST_RESTORE notification
mmc: atmel-mci: fix multiblock SDIO transfers
mmc: at91_mci: fix multiblock SDIO transfers
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