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From 8ab9a20c73acedbb636a41842a681872af8ae1d6 Mon Sep 17 00:00:00 2001
From: David Holsgrove <david.holsgrove@xilinx.com>
Date: Wed, 8 May 2013 11:03:36 +1000
Subject: [PATCH 01/16] [Patch, microblaze]: Add wdc.ext.clear and
wdc.ext.flush insns
Added two new instructions, wdc.ext.clear and wdc.ext.flush,
to enable MicroBlaze to flush an external cache, which is
used with the new coherency support for multiprocessing.
Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
Upstream-Status: Pending
---
opcodes/microblaze-opc.h | 5 ++++-
opcodes/microblaze-opcm.h | 6 +++---
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index e3cc1d9..f453097 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -91,6 +91,7 @@
#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
/* New Mask for msrset, msrclr insns. */
@@ -101,7 +102,7 @@
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
-#define MAX_OPCODES 289
+#define MAX_OPCODES 291
struct op_code_struct
{
@@ -174,7 +175,9 @@ struct op_code_struct
{"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
{"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
{"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
+ {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
{"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+ {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 6868389..8f5c1cb 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -31,9 +31,9 @@ enum microblaze_instr
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
- wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
- brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
- bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+ wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar,
+ br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned,
+ blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
--
1.9.0
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