path: root/common/recipes-kernel/linux/files/0857-drm-amd-dal-Use-native-memset-directly.patch

From 2242a5491fe574b3bf90f4ad6d0e1c7e2b4b908e Mon Sep 17 00:00:00 2001
From: Harry Wentland <harry.wentland@amd.com>
Date: Sat, 27 Feb 2016 14:39:32 -0500
Subject: [PATCH 0857/1110] drm/amd/dal: Use native memset directly

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
 .../gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c |  5 ---
 .../gpu/drm/amd/dal/dc/adapter/adapter_service.c   |  2 +-
 .../amd/dal/dc/asic_capability/asic_capability.c   |  2 +-
 drivers/gpu/drm/amd/dal/dc/audio/audio_base.c      |  2 +-
 .../gpu/drm/amd/dal/dc/basics/register_logger.c    |  4 +--
 drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c      | 20 +++++------
 drivers/gpu/drm/amd/dal/dc/bios/command_table.c    | 42 +++++++++++-----------
 .../dal/dc/bios/dce80/bios_parser_helper_dce80.c   |  2 +-
 drivers/gpu/drm/amd/dal/dc/core/dc.c               |  2 +-
 drivers/gpu/drm/amd/dal/dc/core/dc_link.c          |  4 +--
 drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c      |  2 +-
 drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c       | 14 ++++----
 drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c     |  2 +-
 drivers/gpu/drm/amd/dal/dc/core/dc_resource.c      |  2 +-
 drivers/gpu/drm/amd/dal/dc/core/dc_stream.c        |  2 +-
 .../drm/amd/dal/dc/dce110/dce110_clock_source.c    |  4 +--
 .../drm/amd/dal/dc/dce110/dce110_hw_sequencer.c    |  2 +-
 drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c |  4 +--
 .../gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c   |  2 +-
 .../amd/dal/dc/dce110/dce110_timing_generator.c    |  2 +-
 drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c   |  4 +--
 drivers/gpu/drm/amd/dal/dc/dm_services.h           |  2 --
 .../amd/dal/dc/gpu/dce110/display_clock_dce110.c   |  8 ++---
 .../drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c |  4 +--
 drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c     |  2 +-
 25 files changed, 67 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
index 26208eb..5823789 100644
--- a/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/dal/amdgpu_dm/amdgpu_dm_services.c
@@ -45,11 +45,6 @@ void dm_memmove(void *dst, const void *src, uint32_t size)
 	memmove(dst, src, size);
 }
 
-void dm_memset(void *p, int32_t c, uint32_t count)
-{
-	memset(p, c, count);
-}
-
 int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count)
 {
 	return memcmp(p1, p2, count);
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 339f046..9a68ed9 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -597,7 +597,7 @@ static bool generate_feature_set(
 	uint32_t entry_num = 0;
 	const struct feature_source_entry *entry = NULL;
 
-	dm_memset(adapter_feature_set, 0, sizeof(adapter_feature_set));
+	memset(adapter_feature_set, 0, sizeof(adapter_feature_set));
 	entry_num = get_feature_entries_num();
 
 	while (i != entry_num) {
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
index f7fa96c..75e0e27 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -55,7 +55,7 @@ static bool construct(
 	bool asic_supported = false;
 
 	cap->ctx = ctx;
-	dm_memset(cap->data, 0, sizeof(cap->data));
+	memset(cap->data, 0, sizeof(cap->data));
 
 	/* ASIC data */
 	cap->data[ASIC_DATA_VRAM_TYPE] = init->vram_type;
diff --git a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
index 269c75d..c297d95 100644
--- a/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
+++ b/drivers/gpu/drm/amd/dal/dc/audio/audio_base.c
@@ -157,7 +157,7 @@ static struct audio_feature_support get_supported_features(struct audio *audio)
 	/*DCE specific, must be implemented in derived*/
 	struct audio_feature_support features;
 
-	dm_memset(&features, 0, sizeof(features));
+	memset(&features, 0, sizeof(features));
 
 	features.ENGINE_DIGA = 1;
 	features.ENGINE_DIGB = 1;
diff --git a/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
index 6d32b1b..b8d57d9 100644
--- a/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
+++ b/drivers/gpu/drm/amd/dal/dc/basics/register_logger.c
@@ -137,7 +137,7 @@ void dal_reg_logger_push(const char *caller_func)
 	if (NULL == free_stack_location)
 		return;
 
-	dm_memset(free_stack_location, 0, sizeof(*free_stack_location));
+	memset(free_stack_location, 0, sizeof(*free_stack_location));
 
 	free_stack_location->current_caller_func = caller_func;
 	free_stack_location->current_pid = dm_get_pid();
@@ -170,7 +170,7 @@ void dal_reg_logger_pop(void)
 			dm_get_pid(),
 			dm_get_tgid());
 
-	dm_memset(top_stack_location, 0, sizeof(*top_stack_location));
+	memset(top_stack_location, 0, sizeof(*top_stack_location));
 }
 
 void dal_reg_logger_rw_count_increment(void)
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
index f433f8e..0fe8afc 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/bios_parser.c
@@ -377,7 +377,7 @@ static enum bp_result bios_parser_get_oem_ddc_info(struct dc_bios *dcb,
 			ATOM_I2C_RECORD record;
 			ATOM_I2C_ID_CONFIG_ACCESS *config;
 
-			dm_memset(&record, 0, sizeof(record));
+			memset(&record, 0, sizeof(record));
 
 			config = &tbl->sucI2cId + index - 1;
 
@@ -873,7 +873,7 @@ static enum bp_result get_firmware_info_v1_4(
 	if (!firmware_info)
 		return BP_RESULT_BADBIOSTABLE;
 
-	dm_memset(info, 0, sizeof(*info));
+	memset(info, 0, sizeof(*info));
 
 	/* Pixel clock pll information. We need to convert from 10KHz units into
 	 * KHz units */
@@ -924,7 +924,7 @@ static enum bp_result get_firmware_info_v2_1(
 	if (!firmwareInfo)
 		return BP_RESULT_BADBIOSTABLE;
 
-	dm_memset(info, 0, sizeof(*info));
+	memset(info, 0, sizeof(*info));
 
 	/* Pixel clock pll information. We need to convert from 10KHz units into
 	 * KHz units */
@@ -1010,7 +1010,7 @@ static enum bp_result get_firmware_info_v2_2(
 	if (!firmware_info)
 		return BP_RESULT_BADBIOSTABLE;
 
-	dm_memset(info, 0, sizeof(*info));
+	memset(info, 0, sizeof(*info));
 
 	/* Pixel clock pll information. We need to convert from 10KHz units into
 	 * KHz units */
@@ -1115,7 +1115,7 @@ static enum bp_result get_ss_info_v3_1(
 	tbl = (ATOM_ASIC_SS_ASSIGNMENT_V3 *)
 				&ss_table_header_include->asSpreadSpectrum[0];
 
-	dm_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
+	memset(ss_info, 0, sizeof(struct spread_spectrum_info));
 
 	for (i = 0; i < table_size; i++) {
 		if (tbl[i].ucClockIndication != (uint8_t) id)
@@ -1661,7 +1661,7 @@ static enum bp_result get_ss_info_from_internal_ss_info_tbl_V2_1(
 	header = GET_IMAGE(ATOM_ASIC_INTERNAL_SS_INFO_V2,
 		DATA_TABLES(ASIC_InternalSS_Info));
 
-	dm_memset(info, 0, sizeof(struct spread_spectrum_info));
+	memset(info, 0, sizeof(struct spread_spectrum_info));
 
 	tbl_size = (le16_to_cpu(header->sHeader.usStructureSize)
 			- sizeof(ATOM_COMMON_TABLE_HEADER))
@@ -1765,7 +1765,7 @@ static enum bp_result get_ss_info_from_ss_info_table(
 		if (id_local != (uint32_t)tbl->asSS_Info[i].ucSS_Id)
 			continue;
 
-		dm_memset(ss_info, 0, sizeof(struct spread_spectrum_info));
+		memset(ss_info, 0, sizeof(struct spread_spectrum_info));
 
 		if (ATOM_EXTERNAL_SS_MASK &
 				tbl->asSS_Info[i].ucSpreadSpectrumType)
@@ -1857,7 +1857,7 @@ static enum bp_result get_embedded_panel_info_v1_2(
 		|| 2 > lvds->sHeader.ucTableContentRevision)
 		return BP_RESULT_UNSUPPORTED;
 
-	dm_memset(info, 0, sizeof(struct embedded_panel_info));
+	memset(info, 0, sizeof(struct embedded_panel_info));
 
 	/* We need to convert from 10KHz units into KHz units*/
 	info->lcd_timing.pixel_clk =
@@ -1975,7 +1975,7 @@ static enum bp_result get_embedded_panel_info_v1_3(
 			&& (3 <= lvds->sHeader.ucTableContentRevision)))
 		return BP_RESULT_UNSUPPORTED;
 
-	dm_memset(info, 0, sizeof(struct embedded_panel_info));
+	memset(info, 0, sizeof(struct embedded_panel_info));
 
 	/* We need to convert from 10KHz units into KHz units */
 	info->lcd_timing.pixel_clk =
@@ -3826,7 +3826,7 @@ static enum bp_result patch_bios_image_from_ext_display_connection_info(
 	if (!opm_object)
 		return BP_RESULT_UNSUPPORTED;
 
-	dm_memset(&ext_display_connection_info_tbl, 0,
+	memset(&ext_display_connection_info_tbl, 0,
 			sizeof(ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO));
 
 	connector_tbl_offset = bp->object_info_tbl_offset
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
index 2ea0576..ccd1c7e 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/command_table.c
@@ -365,7 +365,7 @@ static enum bp_result transmitter_control_v2(
 	enum connector_id connector_id =
 		dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	switch (cntl->transmitter) {
 	case TRANSMITTER_UNIPHY_A:
@@ -489,7 +489,7 @@ static enum bp_result transmitter_control_v3(
 	bool dual_link_conn = (CONNECTOR_ID_DUAL_LINK_DVII == conn_id)
 					|| (CONNECTOR_ID_DUAL_LINK_DVID == conn_id);
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	switch (cntl->transmitter) {
 	case TRANSMITTER_UNIPHY_A:
@@ -638,7 +638,7 @@ static enum bp_result transmitter_control_v4(
 			dal_graphics_object_id_get_connector_id(cntl->connector_obj_id);
 	const struct command_table_helper *cmd = bp->cmd_helper;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	switch (cntl->transmitter) {
 	case TRANSMITTER_UNIPHY_A:
@@ -776,7 +776,7 @@ static enum bp_result transmitter_control_v1_5(
 	const struct command_table_helper *cmd = bp->cmd_helper;
 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 params;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
 	params.ucAction = (uint8_t)cntl->action;
 	params.ucLaneNum = (uint8_t)cntl->lanes_number;
@@ -842,7 +842,7 @@ static enum bp_result transmitter_control_v1_6(
 	const struct command_table_helper *cmd = bp->cmd_helper;
 	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 params;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 	params.ucPhyId = cmd->phy_id_to_atom(cntl->transmitter);
 	params.ucAction = (uint8_t)cntl->action;
 
@@ -946,7 +946,7 @@ static enum bp_result set_pixel_clock_v3(
 	PIXEL_CLOCK_PARAMETERS_V3 *params;
 	SET_PIXEL_CLOCK_PS_ALLOCATION allocation;
 
-	dm_memset(&allocation, 0, sizeof(allocation));
+	memset(&allocation, 0, sizeof(allocation));
 
 	if (CLOCK_SOURCE_ID_PLL1 == bp_params->pll_id)
 		allocation.sPCLKInput.ucPpll = ATOM_PPLL1;
@@ -1019,7 +1019,7 @@ static enum bp_result set_pixel_clock_v5(
 	uint8_t controller_id;
 	uint32_t pll_id;
 
-	dm_memset(&clk, 0, sizeof(clk));
+	memset(&clk, 0, sizeof(clk));
 
 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
 			&& bp->cmd_helper->controller_id_to_atom(
@@ -1076,7 +1076,7 @@ static enum bp_result set_pixel_clock_v6(
 	uint8_t controller_id;
 	uint32_t pll_id;
 
-	dm_memset(&clk, 0, sizeof(clk));
+	memset(&clk, 0, sizeof(clk));
 
 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
 			&& bp->cmd_helper->controller_id_to_atom(
@@ -1155,7 +1155,7 @@ static enum bp_result set_pixel_clock_v7(
 	uint8_t controller_id;
 	uint32_t pll_id;
 
-	dm_memset(&clk, 0, sizeof(clk));
+	memset(&clk, 0, sizeof(clk));
 
 	if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
 			&& bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) {
@@ -1265,7 +1265,7 @@ static enum bp_result enable_spread_spectrum_on_ppll_v1(
 	enum bp_result result = BP_RESULT_FAILURE;
 	ENABLE_SPREAD_SPECTRUM_ON_PPLL params;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	if ((enable == true) && (bp_params->percentage > 0))
 		params.ucEnable = ATOM_ENABLE;
@@ -1309,7 +1309,7 @@ static enum bp_result enable_spread_spectrum_on_ppll_v2(
 	enum bp_result result = BP_RESULT_FAILURE;
 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 params;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	if (bp_params->pll_id == CLOCK_SOURCE_ID_PLL1)
 		params.ucSpreadSpectrumType = ATOM_PPLL_SS_TYPE_V2_P1PLL;
@@ -1361,7 +1361,7 @@ static enum bp_result enable_spread_spectrum_on_ppll_v3(
 	enum bp_result result = BP_RESULT_FAILURE;
 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 params;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	switch (bp_params->pll_id) {
 	case CLOCK_SOURCE_ID_PLL0:
@@ -1482,7 +1482,7 @@ static enum bp_result adjust_display_pll_v3(
 	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 params;
 	uint32_t pixel_clk_10_kHz_in = bp_params->pixel_clock / 10;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	/* We need to convert from KHz units into 10KHz units and then convert
 	 * output pixel clock back 10KHz-->KHz */
@@ -1729,7 +1729,7 @@ static enum signal_type dac_load_detection_v3(
 	DAC_LOAD_DETECTION_PS_ALLOCATION params;
 	enum signal_type signal = SIGNAL_TYPE_NONE;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	/* load detection is cupported for CRT, TV and CV */
 	switch (display_signal) {
@@ -2131,7 +2131,7 @@ static enum bp_result select_crtc_source_v2(
 	uint32_t atom_engine_id;
 	enum signal_type s = bp_params->signal;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	/* set controller id */
 	if (bp->cmd_helper->controller_id_to_atom(
@@ -2172,7 +2172,7 @@ static enum bp_result select_crtc_source_v3(
 	uint32_t atom_engine_id;
 	enum signal_type s = bp_params->signal;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,
 			&atom_controller_id))
@@ -2343,7 +2343,7 @@ static enum bp_result program_clock_v5(
 	SET_PIXEL_CLOCK_PS_ALLOCATION_V5 params;
 	uint32_t atom_pll_id;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 	if (!bp->cmd_helper->clock_source_id_to_atom(
 			bp_params->pll_id, &atom_pll_id)) {
 		BREAK_TO_DEBUGGER(); /* Invalid Inpute!! */
@@ -2374,7 +2374,7 @@ static enum bp_result program_clock_v6(
 	SET_PIXEL_CLOCK_PS_ALLOCATION_V6 params;
 	uint32_t atom_pll_id;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	if (!bp->cmd_helper->clock_source_id_to_atom(
 			bp_params->pll_id, &atom_pll_id)) {
@@ -2433,7 +2433,7 @@ static enum bp_result compute_memore_engine_pll_v4(
 	enum bp_result result = BP_RESULT_FAILURE;
 	COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 params;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	params.ulClock = cpu_to_le32(bp_params->target_display_clock / 10);
 
@@ -2489,7 +2489,7 @@ static enum bp_result external_encoder_control_v3(
 	struct graphics_object_id encoder;
 	bool is_input_signal_dp = false;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	cntl_params = &params.sExtEncoder;
 
@@ -2687,7 +2687,7 @@ static enum bp_result set_dce_clock_v2_1(
 	uint32_t atom_clock_type;
 	const struct command_table_helper *cmd = bp->cmd_helper;
 
-	dm_memset(&params, 0, sizeof(params));
+	memset(&params, 0, sizeof(params));
 
 	if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
 			!cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type))
diff --git a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
index b6ee5bf..4973132 100644
--- a/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/bios/dce80/bios_parser_helper_dce80.c
@@ -580,7 +580,7 @@ static void get_bios_event_info(
 	uint32_t s2, s6;
 	uint32_t clear_mask;
 
-	dm_memset(info, 0, sizeof(struct bios_event_info));
+	memset(info, 0, sizeof(struct bios_event_info));
 
 	/* Handle backlight event ONLY. PPLib still handling other events */
 	s6 = dm_read_reg(ctx, mmBIOS_SCRATCH_6);
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index ef238a0..9ae1bc7 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -224,7 +224,7 @@ static struct adapter_service *create_as(
 	struct adapter_service *as = NULL;
 	struct as_init_data init_data;
 
-	dm_memset(&init_data, 0, sizeof(init_data));
+	memset(&init_data, 0, sizeof(init_data));
 
 	init_data.ctx = dc_ctx;
 
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index 9bfa35b..58c7d43 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -1100,7 +1100,7 @@ static void dpcd_configure_panel_mode(
 	union dpcd_edp_config edp_config_set;
 	bool panel_mode_edp = false;
 
-	dm_memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
+	memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
 
 	if (DP_PANEL_MODE_DEFAULT != panel_mode) {
 
@@ -1226,7 +1226,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
 			normalized_pix_clk,
 			stream->public.timing.flags.LTE_340MCSC_SCRAMBLE);
 
-	dm_memset(&stream->sink->link->public.cur_link_settings, 0,
+	memset(&stream->sink->link->public.cur_link_settings, 0,
 			sizeof(struct dc_link_settings));
 
 	link->link_enc->funcs->enable_tmds_output(
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
index f211408..f7a14a2 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_ddc.c
@@ -1051,7 +1051,7 @@ struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
 
 void dal_ddc_service_reset_dp_receiver_id_info(struct ddc_service *ddc_service)
 {
-	dm_memset(&ddc_service->dp_receiver_id_info,
+	memset(&ddc_service->dp_receiver_id_info,
 		0, sizeof(struct dp_receiver_id_info));
 }
 
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
index 31f8ce3..ca7aa20 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_dp.c
@@ -467,7 +467,7 @@ static void get_lane_status_and_drive_settings(
 	struct link_training_settings request_settings = {{0}};
 	uint32_t lane;
 
-	dm_memset(req_settings, '\0', sizeof(struct link_training_settings));
+	memset(req_settings, '\0', sizeof(struct link_training_settings));
 
 	core_link_read_dpcd(
 		link,
@@ -848,8 +848,8 @@ static bool perform_clock_recovery_sequence(
 	while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
 	(retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
 
-		dm_memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
-		dm_memset(&dpcd_lane_status_updated, '\0',
+		memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
+		memset(&dpcd_lane_status_updated, '\0',
 		sizeof(dpcd_lane_status_updated));
 
 		/* 1. call HWSS to set lane settings*/
@@ -975,7 +975,7 @@ bool perform_link_training(
 	struct link_training_settings lt_settings;
 
 	status = false;
-	dm_memset(&lt_settings, '\0', sizeof(lt_settings));
+	memset(&lt_settings, '\0', sizeof(lt_settings));
 
 	lt_settings.link_settings.link_rate = link_setting->link_rate;
 	lt_settings.link_settings.lane_count = link_setting->lane_count;
@@ -1751,10 +1751,10 @@ static void retrieve_link_cap(struct core_link *link)
 	union edp_configuration_cap edp_config_cap;
 	union dp_downstream_port_present ds_port = { 0 };
 
-	dm_memset(dpcd_data, '\0', sizeof(dpcd_data));
-	dm_memset(&down_strm_port_count,
+	memset(dpcd_data, '\0', sizeof(dpcd_data));
+	memset(&down_strm_port_count,
 		'\0', sizeof(union down_stream_port_count));
-	dm_memset(&edp_config_cap, '\0',
+	memset(&edp_config_cap, '\0',
 		sizeof(union edp_configuration_cap));
 
 	core_link_read_dpcd(
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
index 63ff4b0..98ff372 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link_hwss.c
@@ -89,7 +89,7 @@ void dp_disable_link_phy(struct core_link *link, enum signal_type signal)
 	link->link_enc->funcs->disable_output(link->link_enc, signal);
 
 	/* Clear current link setting.*/
-	dm_memset(&link->public.cur_link_settings, 0,
+	memset(&link->public.cur_link_settings, 0,
 			sizeof(link->public.cur_link_settings));
 }
 
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index e397751..c214870 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -900,7 +900,7 @@ static enum ds_color_space build_default_color_space(
 static void translate_info_frame(const struct hw_info_frame *hw_info_frame,
 	struct encoder_info_frame *encoder_info_frame)
 {
-	dm_memset(
+	memset(
 		encoder_info_frame, 0, sizeof(struct encoder_info_frame));
 
 	/* For gamut we recalc checksum */
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
index 4ceee56..c78366a 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_stream.c
@@ -46,7 +46,7 @@ static void build_bit_depth_reduction_params(
 		const struct core_stream *stream,
 		struct bit_depth_reduction_params *fmt_bit_depth)
 {
-	dm_memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
+	memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
 
 	/*TODO: Need to un-hardcode, refer to function with same name
 	 * in dal2 hw_sequencer*/
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
index 033afe8..d9c1d86 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
@@ -475,7 +475,7 @@ static uint32_t dce110_get_pix_clk_dividers(
 		return pll_calc_error;
 	}
 
-	dm_memset(pll_settings, 0, sizeof(*pll_settings));
+	memset(pll_settings, 0, sizeof(*pll_settings));
 
 	if (cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
 		pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
@@ -581,7 +581,7 @@ static bool calculate_ss(
 	if (pll_settings == NULL)
 		return false;
 
-	dm_memset(ds_data, 0, sizeof(struct delta_sigma_data));
+	memset(ds_data, 0, sizeof(struct delta_sigma_data));
 
 	/* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
 	/* 6 decimal point support in fractional feedback divider */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 716a762..de727fb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -1559,7 +1559,7 @@ static void enable_timing_synchronization(
 
 	/* Reset slave controllers on master VSync */
 	DC_SYNC_INFO("GSL: enabling trigger-reset\n");
-	dm_memset(&trigger_params, 0, sizeof(trigger_params));
+	memset(&trigger_params, 0, sizeof(trigger_params));
 
 	trigger_params.edge = TRIGGER_EDGE_DEFAULT;
 	trigger_params.source = SYNC_SOURCE_GSL_GROUP0;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
index 08df2ba..5fb827a 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc.c
@@ -618,7 +618,7 @@ static void set_rgb_limited_range_adjustment(
 	matrix[6] = change_matrix[10];
 	matrix[7] = change_matrix[11];
 
-	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
+	memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
 
 	setup_reg_format(matrix, reg_matrix.regval);
 
@@ -692,7 +692,7 @@ static void set_yuv_adjustment(
 		calculate_adjustments(
 			ideals, &adjustments, matrix);
 
-	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
+	memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
 
 	setup_reg_format(matrix, reg_matrix.regval);
 
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
index 2e50e5a..216e275 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_opp_csc_v.c
@@ -804,7 +804,7 @@ static void set_yuv_adjustment(
 		calculate_adjustments(
 			ideals, &adjustments, matrix);
 
-	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
+	memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
 
 	setup_reg_format(matrix, reg_matrix.regval);
 
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
index ceb91fc..70b82f1 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_timing_generator.c
@@ -518,7 +518,7 @@ bool dce110_timing_generator_program_timing_generator(
 			dc_crtc_timing->h_front_porch;
 	uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset;
 
-	dm_memset(&bp_params, 0, sizeof(struct bp_hw_crtc_timing_parameters));
+	memset(&bp_params, 0, sizeof(struct bp_hw_crtc_timing_parameters));
 
 	/* Due to an asic bug we need to apply the Front Porch workaround prior
 	 * to programming the timing.
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
index a8ad163..464f0ad 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_opp_csc.c
@@ -619,7 +619,7 @@ static void set_rgb_limited_range_adjustment(
 	matrix[6] = change_matrix[10];
 	matrix[7] = change_matrix[11];
 
-	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
+	memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
 
 	setup_reg_format(matrix, reg_matrix.regval);
 
@@ -693,7 +693,7 @@ static void set_yuv_adjustment(
 		calculate_adjustments(
 			ideals, &adjustments, matrix);
 
-	dm_memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
+	memset(&reg_matrix, 0, sizeof(struct out_csc_color_matrix));
 
 	setup_reg_format(matrix, reg_matrix.regval);
 
diff --git a/drivers/gpu/drm/amd/dal/dc/dm_services.h b/drivers/gpu/drm/amd/dal/dc/dm_services.h
index d3820f8..2d33187 100644
--- a/drivers/gpu/drm/amd/dal/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/dal/dc/dm_services.h
@@ -44,8 +44,6 @@
 #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL)
 #define dm_free(ptr) kfree(ptr)
 
-void dm_memset(void *p, int32_t c, uint32_t count);
-
 void dm_memmove(void *dst, const void *src, uint32_t size);
 
 int32_t dm_memcmp(const void *p1, const void *p2, uint32_t count);
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
index 2ee5773..ba9a1fa 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce110/display_clock_dce110.c
@@ -649,8 +649,8 @@ static bool display_clock_integrated_info_construct(
 	struct display_clock *base = &disp_clk->disp_clk_base;
 	bool res;
 
-	dm_memset(&info, 0, sizeof(struct integrated_info));
-	dm_memset(&fw_info, 0, sizeof(struct firmware_info));
+	memset(&info, 0, sizeof(struct integrated_info));
+	memset(&fw_info, 0, sizeof(struct firmware_info));
 
 	res = dal_adapter_service_get_integrated_info(as, &info);
 
@@ -784,7 +784,7 @@ static void set_clock(
 	struct dc_bios *bp = dal_adapter_service_get_bios_parser(base->as);
 
 	/* Prepare to program display clock*/
-	dm_memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
+	memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
 
 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
 	pxl_clk_params.pll_id = base->id;
@@ -907,7 +907,7 @@ static bool dal_display_clock_dce110_construct(
 			struct spread_spectrum_info info;
 			bool result;
 
-			dm_memset(&info, 0, sizeof(info));
+			memset(&info, 0, sizeof(info));
 
 			result =
 				dal_adapter_service_get_ss_info(
diff --git a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
index 5346ded..74d5b2e 100644
--- a/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/dal/dc/gpu/dce80/display_clock_dce80.c
@@ -473,7 +473,7 @@ static void set_clock(
 	struct dc_bios *bp = dal_adapter_service_get_bios_parser(dc->as);
 
 	/* Prepare to program display clock*/
-	dm_memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
+	memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
 
 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
 	pxl_clk_params.pll_id = dc->id;
@@ -701,7 +701,7 @@ static void display_clock_ss_construct(
 		struct spread_spectrum_info ss_info;
 		bool res;
 
-		dm_memset(&ss_info, 0, sizeof(struct spread_spectrum_info));
+		memset(&ss_info, 0, sizeof(struct spread_spectrum_info));
 
 		res = dal_adapter_service_get_ss_info(as,
 			AS_SIGNAL_TYPE_GPU_PLL, 0, &ss_info);
diff --git a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
index 7042d10..725e183 100644
--- a/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
+++ b/drivers/gpu/drm/amd/dal/dc/i2caux/aux_engine.c
@@ -264,7 +264,7 @@ static bool read_command(
 	ctx.request.delay = 0;
 
 	do {
-		dm_memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
+		memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
 
 		ctx.request.data = ctx.buffer + ctx.offset;
 		ctx.request.length = ctx.current_read_length;
-- 
2.7.4