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From 956addaed13b272c5129c2e6be79ccdacb89d04d Mon Sep 17 00:00:00 2001
From: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Date: Thu, 28 Jan 2016 11:25:57 -0500
Subject: [PATCH 0748/1110] drm/amd/dal: Reset clock when refcount drops to 0.
Also, don't share PLL for 2 dual link DVIs and set
0xff mask for controlers when power down pll by BIOS table.
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 10 ++++++++++
drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c | 4 ++--
drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c | 2 +-
drivers/gpu/drm/amd/dal/dc/inc/clock_source.h | 2 +-
4 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index fcda0cb..65523e3 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -66,8 +66,13 @@ void unreference_clock_source(
for (i = 0; i < res_ctx->pool.clk_src_count; i++) {
if (res_ctx->pool.clock_sources[i] == clock_source) {
res_ctx->clock_source_ref_count[i]--;
+
+ if (res_ctx->clock_source_ref_count[i] == 0)
+ clock_source->funcs->cs_power_down(clock_source);
}
}
+
+
}
void reference_clock_source(
@@ -101,6 +106,11 @@ static bool is_sharable_clk_src(
if (id == CLOCK_SOURCE_ID_EXTERNAL)
return false;
+ /* Sharing dual link is not working */
+ if (stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK ||
+ stream_with_clk_src->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
+ return false;
+
if(!is_same_timing(
&stream_with_clk_src->public.timing, &stream->public.timing))
return false;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
index c5a081a..f0cf18f 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_clock_source.c
@@ -798,7 +798,7 @@ static bool dce110_program_pix_clk(
}
static bool dce110_clock_source_power_down(
- struct clock_source *clk_src, enum controller_id controller_id)
+ struct clock_source *clk_src)
{
struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
enum bp_result bp_result;
@@ -808,7 +808,7 @@ static bool dce110_clock_source_power_down(
return true;
/* If Pixel Clock is 0 it means Power Down Pll*/
- bp_pixel_clock_params.controller_id = controller_id;
+ bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
bp_pixel_clock_params.pll_id = clk_src->id;
bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
index 2981307..e1ed527 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_hw_sequencer.c
@@ -896,7 +896,7 @@ static void power_down_clock_sources(struct dc *dc)
for (i = 0; i < dc->res_pool.clk_src_count; i++) {
if (dc->res_pool.clock_sources[i]->funcs->cs_power_down(
- dc->res_pool.clock_sources[i], i+1) == false)
+ dc->res_pool.clock_sources[i]) == false)
dal_error("Failed to power down pll! (clk src index=%d)\n", i);
}
}
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h b/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h
index d7a9a0c..0120ee2 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/clock_source.h
@@ -158,7 +158,7 @@ struct calc_pll_clock_source {
struct clock_source_funcs {
bool (*cs_power_down)(
- struct clock_source *, enum controller_id);
+ struct clock_source *);
bool (*program_pix_clk)(struct clock_source *,
struct pixel_clk_params *, struct pll_settings *);
uint32_t (*get_pix_clk_dividers)(
--
2.7.4
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