diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1070-Revert-Revert-drm-amdgpu-Program-ring-for-vce-instan.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1070-Revert-Revert-drm-amdgpu-Program-ring-for-vce-instan.patch | 161 |
1 files changed, 0 insertions, 161 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1070-Revert-Revert-drm-amdgpu-Program-ring-for-vce-instan.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1070-Revert-Revert-drm-amdgpu-Program-ring-for-vce-instan.patch deleted file mode 100644 index f4c12dfc..00000000 --- a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/1070-Revert-Revert-drm-amdgpu-Program-ring-for-vce-instan.patch +++ /dev/null @@ -1,161 +0,0 @@ -From 13413ecc53f6937a2e945f4f81f786663de3770e Mon Sep 17 00:00:00 2001 -From: Rex Zhu <Rex.Zhu@amd.com> -Date: Thu, 19 Oct 2017 14:54:16 +0800 -Subject: [PATCH 1070/4131] Revert "Revert "drm/amdgpu: Program ring for vce - instance 1 at its register space"" - -This reverts commit b65f7dba6f8642e644080549095f3ed6fc53ac12. ---- - drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 95 +++++++++++++++++++++++++---------- - 1 file changed, 68 insertions(+), 27 deletions(-) - -diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c -index 9ef8145..242dfb1 100644 ---- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c -+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c -@@ -77,13 +77,26 @@ static int vce_v3_0_set_clockgating_state(void *handle, - static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) - { - struct amdgpu_device *adev = ring->adev; -+ u32 v; -+ -+ mutex_lock(&adev->grbm_idx_mutex); -+ if (adev->vce.harvest_config == 0 || -+ adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) -+ WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); -+ else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) -+ WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); - - if (ring == &adev->vce.ring[0]) -- return RREG32(mmVCE_RB_RPTR); -+ v = RREG32(mmVCE_RB_RPTR); - else if (ring == &adev->vce.ring[1]) -- return RREG32(mmVCE_RB_RPTR2); -+ v = RREG32(mmVCE_RB_RPTR2); - else -- return RREG32(mmVCE_RB_RPTR3); -+ v = RREG32(mmVCE_RB_RPTR3); -+ -+ WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); -+ mutex_unlock(&adev->grbm_idx_mutex); -+ -+ return v; - } - - /** -@@ -96,13 +109,26 @@ static uint64_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring) - static uint64_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring) - { - struct amdgpu_device *adev = ring->adev; -+ u32 v; -+ -+ mutex_lock(&adev->grbm_idx_mutex); -+ if (adev->vce.harvest_config == 0 || -+ adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) -+ WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); -+ else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) -+ WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); - - if (ring == &adev->vce.ring[0]) -- return RREG32(mmVCE_RB_WPTR); -+ v = RREG32(mmVCE_RB_WPTR); - else if (ring == &adev->vce.ring[1]) -- return RREG32(mmVCE_RB_WPTR2); -+ v = RREG32(mmVCE_RB_WPTR2); - else -- return RREG32(mmVCE_RB_WPTR3); -+ v = RREG32(mmVCE_RB_WPTR3); -+ -+ WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); -+ mutex_unlock(&adev->grbm_idx_mutex); -+ -+ return v; - } - - /** -@@ -116,12 +142,22 @@ static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring) - { - struct amdgpu_device *adev = ring->adev; - -+ mutex_lock(&adev->grbm_idx_mutex); -+ if (adev->vce.harvest_config == 0 || -+ adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) -+ WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); -+ else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) -+ WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); -+ - if (ring == &adev->vce.ring[0]) - WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); - else if (ring == &adev->vce.ring[1]) - WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); - else - WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); -+ -+ WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT); -+ mutex_unlock(&adev->grbm_idx_mutex); - } - - static void vce_v3_0_override_vce_clock_gating(struct amdgpu_device *adev, bool override) -@@ -231,33 +267,38 @@ static int vce_v3_0_start(struct amdgpu_device *adev) - struct amdgpu_ring *ring; - int idx, r; - -- ring = &adev->vce.ring[0]; -- WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); -- WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); -- WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); -- WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); -- WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); -- -- ring = &adev->vce.ring[1]; -- WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); -- WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); -- WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); -- WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); -- WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); -- -- ring = &adev->vce.ring[2]; -- WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); -- WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); -- WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); -- WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); -- WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4); -- - mutex_lock(&adev->grbm_idx_mutex); - for (idx = 0; idx < 2; ++idx) { - if (adev->vce.harvest_config & (1 << idx)) - continue; - - WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx)); -+ -+ /* Program instance 0 reg space for two instances or instance 0 case -+ program instance 1 reg space for only instance 1 available case */ -+ if (idx != 1 || adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) { -+ ring = &adev->vce.ring[0]; -+ WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); -+ WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); -+ WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); -+ WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); -+ WREG32(mmVCE_RB_SIZE, ring->ring_size / 4); -+ -+ ring = &adev->vce.ring[1]; -+ WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); -+ WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); -+ WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); -+ WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); -+ WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4); -+ -+ ring = &adev->vce.ring[2]; -+ WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); -+ WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); -+ WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); -+ WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); -+ WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4); -+ } -+ - vce_v3_0_mc_resume(adev, idx); - WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1); - --- -2.7.4 - |