diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0204-drm-amd-display-use-disp-clock-value-in-context-rath.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0204-drm-amd-display-use-disp-clock-value-in-context-rath.patch | 154 |
1 files changed, 0 insertions, 154 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0204-drm-amd-display-use-disp-clock-value-in-context-rath.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0204-drm-amd-display-use-disp-clock-value-in-context-rath.patch deleted file mode 100644 index 20bb79af..00000000 --- a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/0204-drm-amd-display-use-disp-clock-value-in-context-rath.patch +++ /dev/null @@ -1,154 +0,0 @@ -From ce80ff7d53df179b51ec25e47a261706a6797824 Mon Sep 17 00:00:00 2001 -From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> -Date: Thu, 2 Feb 2017 17:08:19 -0500 -Subject: [PATCH 0204/4131] drm/amd/display: use disp clock value in context - rather than bw_results - -Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> -Reviewed-by: Jordan Lazare <Jordan.Lazare@amd.com> -Acked-by: Harry Wentland <Harry.Wentland@amd.com> -Signed-off-by: Alex Deucher <alexander.deucher@amd.com> ---- - drivers/gpu/drm/amd/display/dc/core/dc.c | 14 ++++++-------- - drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 2 +- - .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 10 +++++----- - drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 1 + - drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 1 + - drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +- - 6 files changed, 15 insertions(+), 15 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c -index 9d2f78f..4c405f4 100644 ---- a/drivers/gpu/drm/amd/display/dc/core/dc.c -+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c -@@ -925,7 +925,7 @@ void pplib_apply_display_requirements( - /* TODO: dce11.2*/ - pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; - -- pp_display_cfg->disp_clk_khz = context->bw_results.dispclk_khz; -+ pp_display_cfg->disp_clk_khz = context->dispclk_khz; - - fill_display_configs(context, pp_display_cfg); - -@@ -1065,8 +1065,7 @@ bool dc_pre_update_surfaces_to_stream( - { - int i, j; - struct core_dc *core_dc = DC_TO_CORE(dc); -- int prev_disp_clk = core_dc->current_context->bw_results.dispclk_khz; -- int new_disp_clk; -+ int prev_disp_clk = core_dc->current_context->dispclk_khz; - struct dc_stream_status *stream_status = NULL; - struct validate_context *context; - struct validate_context *temp_context; -@@ -1152,17 +1151,16 @@ bool dc_pre_update_surfaces_to_stream( - ret = false; - goto unexpected_fail; - } -- new_disp_clk = context->bw_results.dispclk_khz; - - if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment) -- && prev_disp_clk < new_disp_clk) { -+ && prev_disp_clk < context->dispclk_khz) { - pplib_apply_display_requirements(core_dc, context, - &context->pp_display_cfg); - context->res_ctx.pool->display_clock->funcs->set_clock( - context->res_ctx.pool->display_clock, -- new_disp_clk * 115 / 100); -- core_dc->current_context->bw_results.dispclk_khz = new_disp_clk; -- core_dc->current_context->dispclk_khz = new_disp_clk; -+ context->dispclk_khz * 115 / 100); -+ core_dc->current_context->bw_results.dispclk_khz = context->dispclk_khz; -+ core_dc->current_context->dispclk_khz = context->dispclk_khz; - } - - for (i = 0; i < new_surface_count; i++) -diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c -index 800b22e7..55501b3 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c -@@ -770,7 +770,7 @@ enum dc_status dce100_validate_bandwidth( - struct validate_context *context) - { - /* TODO implement when needed but for now hardcode max value*/ -- context->bw_results.dispclk_khz = 681000; -+ context->dispclk_khz = 681000; - - return DC_OK; - } -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -index a1a5dc6..5e99f6c 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c -@@ -1651,7 +1651,7 @@ static void apply_min_clocks( - /* get the required state based on state dependent clocks: - * display clock and pixel clock - */ -- req_clocks.display_clk_khz = context->bw_results.dispclk_khz; -+ req_clocks.display_clk_khz = context->dispclk_khz; - - req_clocks.pixel_clk_khz = get_max_pixel_clock_for_all_paths( - dc, context, true); -@@ -1776,11 +1776,11 @@ enum dc_status dce110_apply_ctx_to_hw( - /*TODO: when pplib works*/ - apply_min_clocks(dc, context, &clocks_state, true); - -- if (context->bw_results.dispclk_khz -- > dc->current_context->bw_results.dispclk_khz) -+ if (context->dispclk_khz -+ > dc->current_context->dispclk_khz) - context->res_ctx.pool->display_clock->funcs->set_clock( - context->res_ctx.pool->display_clock, -- context->bw_results.dispclk_khz * 115 / 100); -+ context->dispclk_khz * 115 / 100); - - for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { - struct pipe_ctx *pipe_ctx_old = -@@ -2289,7 +2289,7 @@ static void dce110_set_bandwidth(struct core_dc *dc) - - dc->current_context->res_ctx.pool->display_clock->funcs->set_clock( - dc->current_context->res_ctx.pool->display_clock, -- dc->current_context->bw_results.dispclk_khz * 115 / 100); -+ dc->current_context->dispclk_khz * 115 / 100); - } - - static void dce110_program_front_end_for_pipe( -diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c -index 4c108d0..ee4fda5 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c -@@ -926,6 +926,7 @@ enum dc_status dce110_validate_bandwidth( - result = DC_FAIL_BANDWIDTH_VALIDATE; - else - result = DC_OK; -+ context->dispclk_khz = context->bw_results.dispclk_khz; - - if (result == DC_FAIL_BANDWIDTH_VALIDATE) - dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, -diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c -index 7e99b2b..54af84e 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c -@@ -857,6 +857,7 @@ enum dc_status dce112_validate_bandwidth( - result = DC_FAIL_BANDWIDTH_VALIDATE; - else - result = DC_OK; -+ context->dispclk_khz = context->bw_results.dispclk_khz; - - if (result == DC_FAIL_BANDWIDTH_VALIDATE) - dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, -diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c -index fea60aa..3de8bfb 100644 ---- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c -+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c -@@ -785,7 +785,7 @@ enum dc_status dce80_validate_bandwidth( - struct validate_context *context) - { - /* TODO implement when needed but for now hardcode max value*/ -- context->bw_results.dispclk_khz = 681000; -+ context->dispclk_khz = 681000; - context->bw_results.required_yclk = 250000 * MEMORY_TYPE_MULTIPLIER; - - return DC_OK; --- -2.7.4 - |