diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1220-drm-amd-display-Disable-Stutter-for-Stereo-3D.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1220-drm-amd-display-Disable-Stutter-for-Stereo-3D.patch | 135 |
1 files changed, 135 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1220-drm-amd-display-Disable-Stutter-for-Stereo-3D.patch b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1220-drm-amd-display-Disable-Stutter-for-Stereo-3D.patch new file mode 100644 index 00000000..43bd8d3a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux-4.19/linux-yocto-4.19.8/1220-drm-amd-display-Disable-Stutter-for-Stereo-3D.patch @@ -0,0 +1,135 @@ +From c3ea97a441c6c7754108cd41f5f88adc9218e716 Mon Sep 17 00:00:00 2001 +From: Wesley Chalmers <Wesley.Chalmers@amd.com> +Date: Tue, 22 Jan 2019 18:57:06 -0500 +Subject: [PATCH 1220/2940] drm/amd/display: Disable Stutter for Stereo 3D + +[WHY] +Bandwidth calculation formulas currently do not take Stereo 3D + Stutter +properly into account. Disable stutter feature when we detect a Stereo +3D mode as a temporary workaround. + +Change-Id: Icad94f294c662740b988592c6ed0228705b02071 +Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Acked-by: Martin Leung <Martin.Leung@amd.com> +--- + .../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 19 ++++++++++-------- + .../drm/amd/display/dc/dcn10/dcn10_hubbub.h | 2 +- + .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 20 ++++++++++++++++++- + 3 files changed, 31 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +index 5a4614c371bc..e161ad836812 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +@@ -88,11 +88,18 @@ void hubbub1_wm_read_state(struct hubbub *hubbub, + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); + } + +-void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub) ++void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow) + { + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); +- REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL, +- DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, 0); ++ ++ /* ++ * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 1 means do not allow stutter ++ * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0 means allow stutter ++ */ ++ ++ REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, ++ DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, ++ DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow); + } + + bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub) +@@ -262,8 +269,6 @@ void hubbub1_program_watermarks( + bool safe_to_lower) + { + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); +- +- uint32_t force_en = hubbub1->base.ctx->dc->debug.disable_stutter ? 1 : 0; + /* + * Need to clamp to max of the register values (i.e. no wrap) + * for dcn1, all wm registers are 21-bit wide +@@ -537,9 +542,7 @@ void hubbub1_program_watermarks( + REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, + DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68); + +- REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, +- DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, +- DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en); ++ hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); + + #if 0 + REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +index c681e1cc9290..9cd4a5194154 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +@@ -204,7 +204,7 @@ void hubbub1_program_watermarks( + unsigned int refclk_mhz, + bool safe_to_lower); + +-void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub); ++void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow); + + bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 2ec8badd86c1..2d7096bb0146 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -1011,7 +1011,7 @@ static void dcn10_init_hw(struct dc *dc) + */ + if (allow_self_fresh_force_enable == false && + hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub)) +- hubbub1_disable_allow_self_refresh(dc->res_pool->hubbub); ++ hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true); + + disable_vga(dc->hwseq); + } +@@ -2383,6 +2383,22 @@ static void dcn10_apply_ctx_for_surface( + hubbub1_wm_change_req_wa(dc->res_pool->hubbub); + } + ++static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context) ++{ ++ uint8_t i; ++ ++ for (i = 0; i < context->stream_count; i++) { ++ if (context->streams[i]->timing.timing_3d_format ++ == TIMING_3D_FORMAT_HW_FRAME_PACKING) { ++ /* ++ * Disable stutter ++ */ ++ hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false); ++ break; ++ } ++ } ++} ++ + static void dcn10_prepare_bandwidth( + struct dc *dc, + struct dc_state *context) +@@ -2404,6 +2420,7 @@ static void dcn10_prepare_bandwidth( + &context->bw.dcn.watermarks, + dc->res_pool->ref_clock_inKhz / 1000, + true); ++ dcn10_stereo_hw_frame_pack_wa(dc, context); + + if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) + dcn_bw_notify_pplib_of_wm_ranges(dc); +@@ -2433,6 +2450,7 @@ static void dcn10_optimize_bandwidth( + &context->bw.dcn.watermarks, + dc->res_pool->ref_clock_inKhz / 1000, + true); ++ dcn10_stereo_hw_frame_pack_wa(dc, context); + + if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) + dcn_bw_notify_pplib_of_wm_ranges(dc); +-- +2.17.1 + |