diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4932-drm-amd-display-add-pp-to-dc-powerlevel-enum-transla.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4932-drm-amd-display-add-pp-to-dc-powerlevel-enum-transla.patch | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4932-drm-amd-display-add-pp-to-dc-powerlevel-enum-transla.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4932-drm-amd-display-add-pp-to-dc-powerlevel-enum-transla.patch new file mode 100644 index 00000000..a84f2486 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4932-drm-amd-display-add-pp-to-dc-powerlevel-enum-transla.patch @@ -0,0 +1,70 @@ +From 058991fab747d124a939ffe67af8f19f18af6dab Mon Sep 17 00:00:00 2001 +From: Mikita Lipski <mikita.lipski@amd.com> +Date: Tue, 26 Jun 2018 09:52:29 -0400 +Subject: [PATCH 4932/5725] drm/amd/display: add pp to dc powerlevel enum + translator + +[why] +Add a switch statement to translate pp's powerlevel enum +to dc powerlevel statement enum +[how] +Add a translator function + +Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> +Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 29 +++++++++++++++++++++- + 1 file changed, 28 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +index 50e8630..c69ae78 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +@@ -192,6 +192,33 @@ static enum amd_pp_clock_type dc_to_pp_clock_type( + return amd_pp_clk_type; + } + ++static enum dm_pp_clocks_state pp_to_dc_powerlevel_state( ++ enum PP_DAL_POWERLEVEL max_clocks_state) ++{ ++ switch (max_clocks_state) { ++ case PP_DAL_POWERLEVEL_0: ++ return DM_PP_CLOCKS_DPM_STATE_LEVEL_0; ++ case PP_DAL_POWERLEVEL_1: ++ return DM_PP_CLOCKS_DPM_STATE_LEVEL_1; ++ case PP_DAL_POWERLEVEL_2: ++ return DM_PP_CLOCKS_DPM_STATE_LEVEL_2; ++ case PP_DAL_POWERLEVEL_3: ++ return DM_PP_CLOCKS_DPM_STATE_LEVEL_3; ++ case PP_DAL_POWERLEVEL_4: ++ return DM_PP_CLOCKS_DPM_STATE_LEVEL_4; ++ case PP_DAL_POWERLEVEL_5: ++ return DM_PP_CLOCKS_DPM_STATE_LEVEL_5; ++ case PP_DAL_POWERLEVEL_6: ++ return DM_PP_CLOCKS_DPM_STATE_LEVEL_6; ++ case PP_DAL_POWERLEVEL_7: ++ return DM_PP_CLOCKS_DPM_STATE_LEVEL_7; ++ default: ++ DRM_ERROR("DM_PPLIB: invalid powerlevel state: %d!\n", ++ max_clocks_state); ++ return DM_PP_CLOCKS_STATE_INVALID; ++ } ++} ++ + static void pp_to_dc_clock_levels( + const struct amd_pp_clocks *pp_clks, + struct dm_pp_clock_levels *dc_clks, +@@ -441,7 +468,7 @@ bool dm_pp_get_static_clocks( + if (ret) + return false; + +- static_clk_info->max_clocks_state = pp_clk_info.max_clocks_state; ++ static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state); + static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock; + static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock; + +-- +2.7.4 + |