diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4874-drm-amdgpu-pin-the-csb-buffer-on-hw-init-v2.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4874-drm-amdgpu-pin-the-csb-buffer-on-hw-init-v2.patch | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4874-drm-amdgpu-pin-the-csb-buffer-on-hw-init-v2.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4874-drm-amdgpu-pin-the-csb-buffer-on-hw-init-v2.patch new file mode 100644 index 00000000..e337d1c3 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4874-drm-amdgpu-pin-the-csb-buffer-on-hw-init-v2.patch @@ -0,0 +1,93 @@ +From 8a909db2019c5a407176bd61f2ff601bef3ab72b Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Wed, 4 Jul 2018 16:21:52 +0800 +Subject: [PATCH 4874/5725] drm/amdgpu: pin the csb buffer on hw init v2 + +Without this pin, the csb buffer will be filled with inconsistent +data after S3 resume. And that will causes gfx hang on gfxoff +exit since this csb will be executed then. + +v2: fit amdgpu_bo_pin change(take one less argument) + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 +++++++++++++++++++++++++++++++++++ + 1 file changed, 40 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index cd5668a..f424cb8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -954,6 +954,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) + dst_ptr = adev->gfx.rlc.cs_ptr; + gfx_v9_0_get_csb_buffer(adev, dst_ptr); + amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); ++ amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); + } + +@@ -982,6 +983,39 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) + return 0; + } + ++static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev) ++{ ++ int r; ++ ++ r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); ++ if (unlikely(r != 0)) ++ return r; ++ ++ r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, ++ AMDGPU_GEM_DOMAIN_VRAM); ++ if (!r) ++ adev->gfx.rlc.clear_state_gpu_addr = ++ amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); ++ ++ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); ++ ++ return r; ++} ++ ++static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev) ++{ ++ int r; ++ ++ if (!adev->gfx.rlc.clear_state_obj) ++ return; ++ ++ r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); ++ if (likely(r == 0)) { ++ amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); ++ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); ++ } ++} ++ + static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) + { + amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); +@@ -3132,6 +3166,10 @@ static int gfx_v9_0_hw_init(void *handle) + + gfx_v9_0_gpu_init(adev); + ++ r = gfx_v9_0_csb_vram_pin(adev); ++ if (r) ++ return r; ++ + r = gfx_v9_0_rlc_resume(adev); + if (r) + return r; +@@ -3240,6 +3278,8 @@ static int gfx_v9_0_hw_fini(void *handle) + gfx_v9_0_cp_enable(adev, false); + gfx_v9_0_rlc_stop(adev); + ++ gfx_v9_0_csb_vram_unpin(adev); ++ + return 0; + } + +-- +2.7.4 + |