blob: 19c0825f776cc0bdc95b0e87dd67c8da9578b56c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
|
From bbefde394205a1b317eae31942bfc13afce0b0ac Mon Sep 17 00:00:00 2001
From: Bruce Ashfield <bruce.ashfield@windriver.com>
Date: Fri, 5 Apr 2013 00:11:33 -0400
Subject: [PATCH 2/2] oprofile/mips: do not set perf_irq for qemu mips 64
In a similar manner to the following commit:
oprofile/mips: override register writes for qemu mips 64
Even when oprofile timer mode is enabled, during oprofile arch init
there are writes to registers that do not exist in the qemu malta
64 bit pseudo machine.
To allow initialization to continue and the fallback to oprofile
timer mode to take effect, we stub the register writes.
These two defines are only appropriate for qemu-system-mips.
This should not merge to a common location, and only be applied
to emulated boards.
We also cannot set perf_irq to mipsxx_perfcount_handler during oprofile
arch init, or unsupported register reads will be triggered before the
fallback to timer mode occurs. This commit is also only appropriate for
qemu mips based boards, and should not be applied to any general branch.
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
---
arch/mips/oprofile/op_model_mipsxx.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 1ab4f15..16ecbf4 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -419,7 +419,9 @@ static int __init mipsxx_init(void)
}
save_perf_irq = perf_irq;
+#if 0
perf_irq = mipsxx_perfcount_handler;
+#endif
if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
--
1.7.10.4
|
