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From 09c63dde5c4a2430bc1f15eebe76de1ca357f175 Mon Sep 17 00:00:00 2001
From: Weixing Shi <weixing.shi@windriver.com>
Date: Mon, 12 Apr 2010 14:59:38 +0800
Subject: [PATCH 3/8] 4kc cache tlb hazard: tlbp cache coherency
Add a no-op before tlbp, to avoid DMA cache coherency issues that cause
data loss seen on unmount.
Signed-off-by: <weixing.shi@windriver.com> Weixing Shi
Signed-off-by: <james.perkins@windriver.com> James Perkins
---
arch/mips/mm/tlbex.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 0de0e41..e12b9bd 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -244,6 +244,7 @@ static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
case CPU_R5000:
case CPU_R5000A:
case CPU_NEVADA:
+ case CPU_4KC:
uasm_i_nop(p);
uasm_i_tlbp(p);
break;
@@ -299,6 +300,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R4700:
case CPU_R5000:
case CPU_R5000A:
+ case CPU_4KC:
uasm_i_nop(p);
tlbw(p);
uasm_i_nop(p);
@@ -315,7 +317,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
case CPU_R10000:
case CPU_R12000:
case CPU_R14000:
- case CPU_4KC:
case CPU_4KEC:
case CPU_SB1:
case CPU_SB1A:
--
1.6.5.2
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