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The TI AM65x SoCs Gigabit Ethernet Switch subsystem (CPSW2G NUSS) has
two ports - One Ethernet port (port 1) with selectable RGMII and RMII
interfaces and an internal Communications Port Programming Interface (CPPI)
port (Host port 0) and with ALE in between. It also contains
- Management Data Input/Output (MDIO) interface for physical layer device (PHY) management;
- Updated Address Lookup Engine (ALE) module;
- (TBD) New version of Common platform time sync (CPTS) module;
Signed-off-by: Jun Miao <jun.miao@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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CONFIG_NETDEVICES is set twice, remove one of them.
Signed-off-by: Yanfei Xu <yanfei.xu@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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Two types spi-nor flash support on TI's AM654 EVM:
ospi-nor: mt35xu512aba Octal flash with 512-Mbit
spi-nor : mt25ql128aba SPI NOR Flash with 128-Mbit
Signed-off-by: Jun Miao <jun.miao@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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Add scc/cfg kernel fragment to build and boot AM65X GP EVM board with am6548 soc.
Signed-off-by: Jun Miao <jun.miao@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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Jun Miao
Yanfei Xu