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Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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1/2 [
Author: Thomas Gleixner
Email: tglx@linutronix.de
Subject: x86/alternatives: Sync core before enabling interrupts
Date: Thu, 7 Dec 2023 20:49:24 +0100
text_poke_early() does:
local_irq_save(flags);
memcpy(addr, opcode, len);
local_irq_restore(flags);
sync_core();
That's not really correct because the synchronization should happen before
interrupts are reenabled to ensure that a pending interrupt observes the
complete update of the opcodes.
It's not entirely clear whether the interrupt entry provides enough
serialization already, but moving the sync_core() invocation into interrupt
disabled region does no harm and is obviously correct.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
]
2/2 [
Author: Thomas Gleixner
Email: tglx@linutronix.de
Subject: x86/alternatives: Disable interrupts and sync when optimizing NOPs in place
Date: Thu, 7 Dec 2023 20:49:26 +0100
apply_alternatives() treats alternatives with the ALT_FLAG_NOT flag set
special as it optimizes the existing NOPs in place.
Unfortunately this happens with interrupts enabled and does not provide any
form of core synchronization.
So an interrupt hitting in the middle of the update and using the affected
code path will observe a half updated NOP and crash and burn. The following
3 NOP sequence was observed to expose this crash halfways reliably under
QEMU 32bit:
0x90 0x90 0x90
which is replaced by the optimized 3 byte NOP:
0x8d 0x76 0x00
So an interrupt can observe:
1) 0x90 0x90 0x90 nop nop nop
2) 0x8d 0x90 0x90 undefined
3) 0x8d 0x76 0x90 lea -0x70(%esi),%esi
4) 0x8d 0x76 0x00 lea 0x0(%esi),%esi
Where only #1 and #4 are true NOPs. The same problem exists for 64bit obviously.
Disable interrupts around this NOP optimization and invoke sync_core()
before reenabling them.
Fixes: 270a69c4485d ("x86/alternative: Support relocations in alternatives")
Reported-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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The revert isn't necessary with the 6.4 kernel.
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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1/1 [
Author: Bruce Ashfield
Email: bruce.ashfield@gmail.com
Subject: Revert "tick/common: Align tick period with the HZ tick."
Date: Wed, 14 Jun 2023 23:08:03 -0400
This reverts commit 290e26ec0d012b70ab7e4a9a59924682d0ed4ce8.
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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1/1 [
Author: Naveen Saini
Email: naveen.kumar.saini@intel.com
Subject: x86_64_defconfig: Fix warnings
Date: Fri, 21 Jan 2022 16:46:21 +0800
Configure CONFIG_EEEPC_LAPTOP & CONFIG_SND_SEQ_DUMMY as modules, because
dependencies are configured as modules.
[NOTE]: 'CONFIG_EEEPC_LAPTOP' last val (y) and .config val (m) do not match
[NOTE]: 'CONFIG_SND_SEQ_DUMMY' last val (y) and .config val (m) do not match
Added dependency configurations:
CONFIG_HID_LOGITECH for CONFIG_LOGITECH_FF
CONFIG_NET_VENDOR_DEC for CONFIG_NET_TULIP
CONFIG_IOMMU_SUPPORT for CONFIG_AMD_IOOMU & CONFIG_INTEL_IOMMU
CONFIG_NET_VENDOR_NVIDIA for CONFIG_FORCEDETH
Config 'LOGITECH_FF' has the following Direct dependencies (LOGITECH_FF=n):
HID_LOGITECH(=n) && HID(=y) && INPUT(=y)
Parent dependencies are:
HID_LOGITECH [n] HID [y] INPUT [y]
[INFO]: config 'CONFIG_LOGITECH_FF' was set, but it wasn't assignable, check (parent) dependencies
Config 'NET_TULIP' has the following Direct dependencies (NET_TULIP=n):
PCI(=y) || EISA(=n) || CARDBUS(=y) (=y) && NET_VENDOR_DEC(=n) && ETHERNET(=y) && NETDEVICES(=y)
Parent dependencies are:
NET_VENDOR_DEC [n] ETHERNET [y] EISA [n] PCI [y] CARDBUS [y] NETDEVICES [y]
[INFO]: config 'CONFIG_NET_TULIP' was set, but it wasn't assignable, check (parent) dependencies
Config 'FORCEDETH' has the following Direct dependencies (FORCEDETH=n):
PCI(=y) && NET_VENDOR_NVIDIA(=n) && ETHERNET(=y) && NETDEVICES(=y)
Parent dependencies are:
NETDEVICES [y] PCI [y] NET_VENDOR_NVIDIA [n] ETHERNET [y]
[INFO]: config 'CONFIG_FORCEDETH' was set, but it wasn't assignable, check (parent) dependencies
Tested with qemux86-64 machine:
$ oe-selftest --run-tests kerneldevelopment.KernelConfigs
Disabled debug configurations. Yocto-kernel-cahce have seperate debug configurations.
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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1/1 [
Author: Yongxin Liu
Email: yongxin.liu@windriver.com
Subject: Revert "platform/x86: wmi: Destroy on cleanup rather than unregister"
Date: Wed, 27 Nov 2019 16:46:58 +0800
This reverts commit 7b11e8989618581bc0226ad313264cdc05d48d86.
Consider the following hardware setting.
|-PNP0C14:00
| |-- device #1
|-PNP0C14:01
| |-- device #2
When unloading wmi driver module, device #2 will be first unregistered.
But device_destroy() using MKDEV(0, 0) will locate PNP0C14:00 first
and unregister it. This is incorrect. Should use device_unregister() to
unregister the real parent device.
Signed-off-by: Yongxin Liu <yongxin.liu@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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Signed-off-by: Yann CARDAILLAC <ycnakajsph@gmail.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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1/1 [
Author: Bruce Ashfield
Email: bruce.ashfield@gmail.com
Subject: arch/x86/boot: use prefix map to avoid embedded paths
Date: Thu, 8 Aug 2019 23:39:26 -0400
It was observed that the kernel embeds the path in the x86 boot
artifacts.
From https://bugzilla.yoctoproject.org/show_bug.cgi?id=13458:
[
If you turn on the buildpaths QA test, or try a reproducible build, you
discover that the kernel image contains build paths.
$ strings bzImage-5.0.19-yocto-standard |grep tmp/
out of pgt_buf in
/data/poky-tmp/reproducible/tmp/work-shared/qemux86-64/kernel-source/arch/x86/boot/compressed/kaslr_64.c!?
But what's this in the top-level Makefile:
$ git grep prefix-map
Makefile:KBUILD_CFLAGS += $(call
cc-option,-fmacro-prefix-map=$(srctree)/=)
So the __FILE__ shouldn't be using the full path. However
arch/x86/boot/compressed/Makefile has this:
KBUILD_CFLAGS := -m$(BITS) -O2
So that clears KBUILD_FLAGS, removing the -fmacro-prefix-map option.
]
Other architectures do not clear the flags, but instead prune before
adding boot or specific options. There's no obvious reason why x86 isn't
doing the same thing (pruning vs clearing) and no build or boot issues
have been observed.
So we make x86 can do the same thing, and we no longer have embedded paths.
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@gmail.com>
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These patches are not appropriate for the dev kernel, so we drop them
until BSP ports can be performed.
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/1 [
Author: Jussi Laako
Email: jussi.laako@linux.intel.com
Subject: gpio-pca953x: add "drive" property
Date: Thu, 10 Mar 2016 11:58:11 -0800
Galileo gen 2 has support for setting GPIO modes. Expose these
properties through the GPIO sysfs interface. This approach is bit hacky,
since it changes the interface semantics.
The original patch was by Josef Ahmad <josef.ahmad@linux.intel.com> and
made on top of kernel 3.8.
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Jussi Laako <jussi.laako@linux.intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/6 [
Author: Ismo Puustinen
Email: ismo.puustinen@intel.com
Subject: acpi: added a custom DSDT file.
Date: Fri, 19 Feb 2016 07:18:25 -0800
The file has fixed GPIO IRQ assignment and moved SPI devices to be under
the SPI bus in the ACPI definitions as assumed by ACPI version 5.
Upstream-status: Inappropriate, custom firmware
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
2/6 [
Author: Andy Shevchenko
Email: andriy.shevchenko@linux.intel.com
Subject: gpio: pca953x: provide GPIO base based on _UID
Date: Fri, 19 Feb 2016 07:18:26 -0800
Custom kernel for Intel Galileo Gen2 provides and moreover libmraa relies on
the continuous GPIO space. To do such we have to configure GPIO base per each
GPIO expander. The only value we can use is the ACPI _UID.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Upstream-status: Inappropriate, custom code for legacy userspace
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
3/6 [
Author: Josef Ahmad
Email: josef.ahmad@linux.intel.com
Subject: pca9685: PCA9685 PWM and GPIO multi-function device.
Date: Fri, 19 Feb 2016 07:18:27 -0800
There is also a driver for the same chip in drivers/pwm. This version
has support for setting the output in GPIO mode in addition to the PWM
mode.
Upstream-status: Forward-ported from Intel IOT Develper Kit Quark BSP.
Inappropriate to the upstream kernel, because the
upstream kernel already uses a different (non-mfd)
driver for handling the same chip, and doesn't need
to be backwards compatible.
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
4/6 [
Author: Ismo Puustinen
Email: ismo.puustinen@intel.com
Subject: spi-pxa2xx: fixed ACPI-based enumeration of SPI devices.
Date: Fri, 19 Feb 2016 07:18:28 -0800
Slave devices were not enumerated by ACPI data because the ACPI handle
for the spi-pxa2xx controller was NULL if it was itself enumerated by
PCI.
Original patch by Mika Westerberg <mika.westerberg@intel.com>.
Upstream-status: Inappropriate, will be fixed with a bigger overhaul of
SPI/ACPI interaction.
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
5/6 [
Author: Todor Minchev
Email: todor@minchev.co.uk
Subject: staging:iio: add support for ADC1x8s102.
Date: Fri, 19 Feb 2016 07:18:29 -0800
Adds new config and support for Texas Instruments ADC1x8S102 driver"
config ADC1x8S102
tristate "Texas Instruments ADC1x8S102 driver"
depends on SPI
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Say yes here to build support for Texas Instruments ADC1x8S102 ADC.
Provides direct access via sysfs.
To compile this driver as a module, choose M here: the module will
be called adc1x8s102
Upstream-status: Forward-ported from Intel IOT Develper Kit Quark BSP
Original author is Bogdan Pricop <bogdan.pricop@emutex.com>.
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
6/6 [
Author: Ismo Puustinen
Email: ismo.puustinen@intel.com
Subject: adc1x8s102: support ACPI-based enumeration.
Date: Fri, 19 Feb 2016 07:18:30 -0800
Upstream-status: Pending for ADC1x8s102 patch upstreaming to Linux kernel
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/1 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: spi/pxa2xx-pci: Add common clock framework support in PCI glue layer
Date: Fri, 25 Jul 2014 01:10:54 +0800
SPI PXA2XX core layer has dependency on common clock framework
to obtain information on host supported clock rate. Thus, we
setup the clock device in the PCI glue layer to enable PCI mode
host pass in the clock rate information.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Kweh, Hock Leong <hock.leong.kweh@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/24 [
Author: Thomas Gleixner
Email: tglx@linutronix.de
Subject: genirq: x86: Ensure that dynamic irq allocation does not conflict
Date: Thu, 24 Apr 2014 09:50:53 +0200
On x86 the allocation of irq descriptors may allocate interrupts which
are in the range of the GSI interrupts. That's wrong as those
interrupts are hardwired and we don't have the irq domain translation
like PPC. So one of these interrupts can be hooked up later to one of
the devices which are hard wired to it and the io_apic init code for
that particular interrupt line happily reuses that descriptor with a
completely different configuration so hell breaks lose.
Inside x86 we allocate dynamic interrupts from above nr_gsi_irqs,
except for a few usage sites which have not yet blown up in our face
for whatever reason. But for drivers which need an irq range, like the
GPIO drivers, we have no limit in place and we don't want to expose
such a detail to a driver.
To cure this introduce a function which an architecture can implement
to impose a lower bound on the dynamic interrupt allocations.
Implement it for x86 and set the lower bound to nr_gsi_irqs, which is
the end of the hardwired interrupt space, so all dynamic allocations
happen above.
That not only allows the GPIO driver to work sanely, it also protects
the bogus callsites of create_irq_nr() in hpet, uv, irq_remapping and
htirq code. They need to be cleaned up as well, but that's a separate
issue.
Reported-by: Jin Yao <yao.jin@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Mathias Nyman <mathias.nyman@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Krogerus Heikki <heikki.krogerus@intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1404241617360.28206@ionos.tec.linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
(cherry picked from commit 62a08ae2a5763aabeee98264605236b001503e0c)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
2/24 [
Author: Mika Westerberg
Email: mika.westerberg@linux.intel.com
Subject: pwm: add support for Intel Low Power Subsystem PWM
Date: Thu, 20 Mar 2014 22:04:23 +0800
Add support for Intel Low Power I/O subsystem PWM controllers found on
Intel BayTrail SoC.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Chew, Kean Ho <kean.ho.chew@intel.com>
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit d16a5aa9e821633a3095d7a88cd1d2cd108bf966)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
3/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: ACPI / LPSS: Add Intel BayTrail ACPI mode PWM
Date: Wed, 19 Feb 2014 02:24:29 +0800
Intel BayTrail LPSS consists of two PWM controllers which can
be enumerated from ACPI namespace. This change will cause
platform device objects to be created for Intel BayTrail PWM
controllers which will allow the pwm-lpss driver to bind to them
and handle those devices.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
(cherry picked from commit e1c7481797542f4d2039d5a458ef80603298ad78)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
4/24 [
Author: Mika Westerberg
Email: mika.westerberg@linux.intel.com
Subject: i2c: designware-pci: Add Baytrail PCI IDs
Date: Wed, 19 Feb 2014 16:10:29 +0200
Intel Baytrail I2C controllers can be enumerated from PCI as well as from
ACPI. In order to support this add the Baytrail PCI IDs to the driver.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit 089c729ae440c6df35eeac7998525718fcee0323)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
5/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: sdhci: Allow for irq being shared
Date: Tue, 11 Mar 2014 10:09:36 +0200
If the SDHCI irq is shared with another device then the interrupt
handler can get called while SDHCI is runtime suspended. That is
harmless but the warning message is not useful so remove it. Also
returning IRQ_NONE is more appropriate.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 655bca7616bf6076d30b14d1478bca6807d49c45)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
6/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: dma: dw: Add suspend and resume handling for PCI mode DW_DMAC.
Date: Sat, 15 Mar 2014 02:02:39 +0800
This is to disable/enable DW_DMAC hw during late suspend/early resume.
Since DMA is providing service to other clients (eg: SPI, HSUART),
we need to ensure DMA suspends after the clients and resume
before the clients are active.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
(cherry picked from commit 4501fe61b286e35be5b372a4f1ffcf5881ceeaed)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
7/24 [
Author: "Chew, Kean ho"
Email: kean.ho.chew@intel.com
Subject: i2c: i801: enable Intel BayTrail SMBUS
Date: Sat, 1 Mar 2014 00:03:56 +0800
Add Device ID of Intel BayTrail SMBus Controller.
Signed-off-by: Chew, Kean ho <kean.ho.chew@intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit 1b31e9b76ef8c62291e698dfdb973499986a7f68)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
8/24 [
Author: "Chew, Kean Ho"
Email: kean.ho.chew@intel.com
Subject: pinctrl-baytrail: add function mux checking in gpio pin request
Date: Thu, 6 Mar 2014 21:59:49 +0800
The requested gpio pin must has the func_pin_mux field set
to GPIO function by BIOS/FW in advanced. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any gpio pins which shall be used for alternate functions,
for eg: wakeup pin, I/O interfaces for LPSS, etc.
Signed-off-by: Chew, Kean Ho <kean.ho.chew@intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: Darren Hart <dvhart@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 42bd00706ce95d74ad6ebcb8528ee1fbbb992f6a)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
9/24 [
Author: Paul Drews
Email: paul.drews@intel.com
Subject: ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs
Date: Mon, 25 Nov 2013 14:15:55 -0800
This adds the new ACPI ID (INT33FC) for the BayTrail GPIO
banks as seen on a BayTrail M System-On-Chip platform. This
ACPI ID is used by the BayTrail GPIO (pinctrl) driver to
manage the Low Power Subsystem (LPSS).
Signed-off-by: Paul Drews <paul.drews@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
(cherry picked from commit f6308b36c411dc5afd6a6f73e6454722bfde57b7)
This patch has been reverted in mainline, but the revert should not
longer be necessary with the x86 irq fix from Thomas Gleixner now in
mainline:
b6dae3b genirq: x86: Ensure that dynamic irq allocation does not conflict
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
10/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C
Date: Fri, 7 Mar 2014 22:12:50 +0800
All the I2C controllers on Intel BayTrail LPSS subsystem able
to support 10-bit addressing mode functionality.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Ong, Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit ceccd298f6fd537457576017d604fc5aa6d3c82a)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
11/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: sdhci-acpi: Fix broken card detect for ACPI HID 80860F14
Date: Mon, 10 Mar 2014 15:02:42 +0200
Some 80860F14 devices do not support card detect and must rely
completely on GPIO. Presently the card detect GPIO is used
only to wake-up from runtime suspend. Change to using
mmc_gpioid_request_cd() which will cause the SDHCI driver to
prefer the GPIO to the host controller's native card detect.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 4fd4409c81e2c756a5cfbedc598c48d6a3ed3fd5)
]
12/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: slot-gpio: Record GPIO descriptors instead of GPIO numbers
Date: Mon, 10 Mar 2014 15:02:39 +0200
In preparation for adding a descriptor-based CD GPIO API, switch from
recording GPIO numbers to recording GPIO descriptors.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 842f4bdd37c7a0984e22aa919ad1f043137ac5c8)
]
13/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: slot-gpio: Split out CD IRQ request into a separate function
Date: Mon, 10 Mar 2014 15:02:40 +0200
In preparation for adding a descriptor-based CD GPIO API, split out
CD IRQ request into a separate function.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 26652671338a443fd33cf47b50658dd8b095d54a)
]
14/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: slot-gpio: Add GPIO descriptor based CD GPIO API
Date: Mon, 10 Mar 2014 15:02:41 +0200
Add functions to request a CD GPIO using the GPIO descriptor API.
Note that the new request function is paired with mmc_gpiod_free_cd()
not mmc_gpio_free_cd(). Note also that it must be called prior to
mmc_add_host() otherwise the caller must also call
mmc_gpiod_request_cd_irq().
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 740a221ef0e579dc7c675cf6b90f5313509788f7)
]
15/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: sdhci-acpi: Add device id 80860F16
Date: Mon, 10 Mar 2014 15:02:43 +0200
Add ACPI HID 80860F16 as a host controller for a SD card.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit aad95dc49c6dad19b49af7cd90c53473ec0536d1)
]
16/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value
Date: Tue, 11 Mar 2014 19:33:45 +0800
On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in optimal
HCNT/LCNT/SDA hold time values to core layer since the core
layer supports cofigurable HCNT/LCNT/SDA hold time values now.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit 8efd1e9ee3bd55e20cb36e56ca53096cf2b3a930)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
17/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: sdhci-acpi: Intel SDIO has broken card detect
Date: Thu, 3 Apr 2014 14:58:39 +0300
Intel SDIO has broken card detect so add a quirk to reflect that.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit c67480173f72e883235dd0ad09d90156c8f87600)
]
18/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: spi/pxa2xx-pci: Add PCI mode support for BayTrail LPSS SPI
Date: Fri, 18 Apr 2014 00:26:06 +0800
Similar to CE4100, BayTrail LPSS SPI can be PCI enumerated
as well. Thus, the functions are renamed from ce4100_xxx
to pxa2xx_spi_pci_xxx to clarify that this is a generic
PCI glue layer. Also, added required infrastructure to
support SPI hosts with different configurations.
This patch is based on Mika Westerberg's previous work.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit d6ba32d5c60f569d252ec9dcd96cd46b19785b60)
From linux-next
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
19/24 [
Author: Darren Hart
Email: dvhart@linux.intel.com
Subject: drm/i915/vlv: reset VLV media force wake request register
Date: Fri, 9 May 2014 08:43:09 -0700
Media force wake get hangs the machine when the system is booted without
displays attached. The assumption is that (at least some versions of)
the firmware has skipped some initialization in that case.
Empirical evidence suggests we need to reset the media force wake
request register in addition to the render one to avoid hangs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75895
Reported-by: Imre Deak <imre.deak@intel.com>
Reported-by: Darren Hart <dvhart@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
]
20/24 [
Author: Alan Cox
Email: alan@linux.intel.com
Subject: pwm: lpss: Add support for PCI devices
Date: Fri, 18 Apr 2014 19:17:40 +0800
Not all systems enumerate the PWM devices via ACPI. They can also be
exposed via the PCI interface.
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 093e00bb3f82f3c67e2d1682e316fc012bcd0d92)
From linux-next/next-20140512
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
21/24 [
Author: Thierry Reding
Email: thierry.reding@gmail.com
Subject: pwm: lpss: Fix const qualifier and sparse warnings
Date: Wed, 7 May 2014 10:27:57 +0200
Fixes the following warnings reported by the 0-DAY kernel build testing
backend:
drivers/pwm/pwm-lpss.c: In function 'pwm_lpss_probe_pci':
>> drivers/pwm/pwm-lpss.c:192:2: warning: passing argument 3 of 'pwm_lpss_probe' discards 'const' qualifier from pointer target type [enabled by default]
lpwm = pwm_lpss_probe(&pdev->dev, &pdev->resource[0], info);
^
drivers/pwm/pwm-lpss.c:130:30: note: expected 'struct pwm_lpss_boardinfo *' but argument is of type 'const struct pwm_lpss_boardinfo *'
static struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev,
^
>> drivers/pwm/pwm-lpss.c:143:28: sparse: incorrect type in return expression (different address spaces)
drivers/pwm/pwm-lpss.c:143:28: expected struct pwm_lpss_chip *
drivers/pwm/pwm-lpss.c:143:28: got void [noderef] <asn:2>*regs
>> drivers/pwm/pwm-lpss.c:192:63: sparse: incorrect type in argument 3 (different modifiers)
drivers/pwm/pwm-lpss.c:192:63: expected struct pwm_lpss_boardinfo *info
drivers/pwm/pwm-lpss.c:192:63: got struct pwm_lpss_boardinfo const *[assigned] info
drivers/pwm/pwm-lpss.c: In function 'pwm_lpss_probe_pci':
drivers/pwm/pwm-lpss.c:192:2: warning: passing argument 3 of 'pwm_lpss_probe' discards 'const' qualifier from pointer target type [enabled by default]
lpwm = pwm_lpss_probe(&pdev->dev, &pdev->resource[0], info);
^
drivers/pwm/pwm-lpss.c:130:30: note: expected 'struct pwm_lpss_boardinfo *' but argument is of type 'const struct pwm_lpss_boardinfo *'
static struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev,
^
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 89c0339e0aa097384b3efed894b23820814c21d3)
From linux-next/next-20140512
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
22/24 [
Author: Darren Hart
Email: dvhart@linux.intel.com
Subject: clkdev: Export clk_register_clkdev
Date: Fri, 9 May 2014 14:14:45 -0700
Allow spi-pxa2xx-pci with common clock framework support to build as a
module by exporting clk_register_clkdev.
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
Cc: "Chew, Chiau Ee" <chiau.ee.chew@intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
]
23/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: spi/pxa2xx: Add common clock framework support in PCI glue layer
Date: Thu, 8 May 2014 15:36:11 -0700
SPI PXA2XX core layer has dependency on common clock framework
to obtain information on host supported clock rate. Thus, we
setup the clock device in the PCI glue layer to enable PCI mode
host pass in the clock rate information.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
PENDING: Out for review
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
24/24 [
Author: Darren Hart
Email: dvhart@linux.intel.com
Subject: acpi_lpss: Add Bay Trail pinctrl HID
Date: Mon, 28 Apr 2014 07:16:46 -0700
Add the newer Bay Trail pinctrl HID to the acpi_lpss acpi match table.
Without this, the pinctrl-baytrail.c driver doesn't match the device and
the GPIO are not visible.
PENDING: Out for review
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
|
Bruce Ashfield
Yann CARDAILLAC
Bruce Ashfield