Age | Commit message (Collapse) | Author |
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Duplicate what was done in 2023.1 to allow qemu-xilinx to build.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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arm: Add support for r52 IMP_PERIPHPREGIONR register
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Changelog:
(none)
Signed-off-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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xlnx-versal-aes: Fix 128 bit key loads
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
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Revert "hw/misc/xlnx-versal-pmc-clk-rst.c: fix the PL reset polarity"
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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pmx-efuse-ctrl: Fix the eFuse key load
sodimm-spd: Add the SPD data for 4GB Micron model
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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hw/misc/xlnx-versal-pmc-clk-rst.c: fix the PL reset polarity
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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xilinx_axienet: Set phy link status
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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hw/misc/xlnx-versal-pmx-global: Implement pmx_global_gd_monitor_enabled
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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hw/nvram: pmx-efuse: Build Xilinx PMX eFuse devices
hw/nvram: pmx-efuse: Introduce Xilinx PMX eFuse cache
hw/nvram: pmx-efuse: Introduce Xilinx PMX eFuse controller
hw/nvram: pmx-efuse: Introduce Xilinx PMX eFuse tiles
hw/nvram: Add get_puf/_sysmon abstractions to Xilinx EFuse
xlnx-efuse: Add get_puf/_sysmon abstractions
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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hw/nvram: Add get_u32 abstraction to Xilinx eFuse
xlnx-efuse: Add get_u32 abstraction
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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mdio: handle 16 bit mdio writes
versal: efuse: Block reset from setting 2 registers
hw/nvram: Fix incorrect guest-error log from Xilinx Zynqmp eFuse
hw/nvram: Fix incorrect guest-error log from Xilinx Versal eFuse
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
xlnx-efuse: Avoid unnecessary backstore write
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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versal-pmx-iou-slcr: Init the mux configuration
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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xlnx_dp: fetch data after vertical sync
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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