aboutsummaryrefslogtreecommitdiffstats
path: root/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
diff options
context:
space:
mode:
Diffstat (limited to 'meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch')
-rw-r--r--meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch68
1 files changed, 0 insertions, 68 deletions
diff --git a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
deleted file mode 100644
index d0b534bc..00000000
--- a/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-10/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 328bd339c292b63d2068a132a245bdc037815d6b Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Wed, 17 Oct 2018 16:56:14 +0530
-Subject: [PATCH 52/63] fixing the 32bit LTO related issue9(1014024)
-
----
- gcc/config/microblaze/microblaze.h | 24 ++++++++++++++----------
- 1 file changed, 14 insertions(+), 10 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index bd5e216..ab541f7 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe;
- #define WORD_REGISTER_OPERATIONS 1
-
- #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
--/*
--#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
-- if (GET_MODE_CLASS (MODE) == MODE_INT \
-- && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
-- (MODE) = TARGET_MB_64 ? DImode : SImode;
--*/
-+
-+#ifndef __arch64__
-+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
-+ if (GET_MODE_CLASS (MODE) == MODE_INT \
-+ && GET_MODE_SIZE (MODE) < 4) \
-+ (MODE) = SImode;
-+#endif
-+
- /* Standard register usage. */
-
- /* On the MicroBlaze, we have 32 integer registers */
-@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info;
-
- #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
-
-+#ifdef __aarch64__
- #define LIBCALL_VALUE(MODE) \
- gen_rtx_REG (MODE,GP_RETURN)
--
--/*#define LIBCALL_VALUE(MODE) \
-+#else
-+#define LIBCALL_VALUE(MODE) \
- gen_rtx_REG ( \
- ((GET_MODE_CLASS (MODE) != MODE_INT \
- || GET_MODE_SIZE (MODE) >= 4) \
- ? (MODE) \
- : SImode), GP_RETURN)
--*/
-+#endif
-+
- /* 1 if N is a possible register number for a function value.
- On the MicroBlaze, R2 R3 are the only register thus used.
- Currently, R2 are only implemented here (C has no complex type) */
-@@ -518,7 +522,7 @@ typedef struct microblaze_args
- /* 4 insns + 2 words of data. */
- #define TRAMPOLINE_SIZE (6 * 4)
-
--#define TRAMPOLINE_ALIGNMENT 64
-+#define TRAMPOLINE_ALIGNMENT (TARGET_MB_64 ? 64 : 32)
-
- #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
-
---
-2.7.4
-