diff options
Diffstat (limited to 'recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-FROMLIST-arm64-dts-qcom-sc7280-Add-UFS-nodes-for-sc7.patch')
| -rw-r--r-- | recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-FROMLIST-arm64-dts-qcom-sc7280-Add-UFS-nodes-for-sc7.patch | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-FROMLIST-arm64-dts-qcom-sc7280-Add-UFS-nodes-for-sc7.patch b/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-FROMLIST-arm64-dts-qcom-sc7280-Add-UFS-nodes-for-sc7.patch new file mode 100644 index 0000000..3b17ae4 --- /dev/null +++ b/recipes-kernel/linux/linux-yocto/qcm6490-dtsi/0001-FROMLIST-arm64-dts-qcom-sc7280-Add-UFS-nodes-for-sc7.patch @@ -0,0 +1,97 @@ +From 92c06bd8d2125f45ff52c9a6819c6cd8bf7a575d Mon Sep 17 00:00:00 2001 +From: Nitin Rawat <quic_nitirawa@quicinc.com> +Date: Fri, 29 Sep 2023 18:49:34 +0530 +Subject: [PATCH] FROMLIST: arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 + soc + +Add UFS host controller and PHY nodes for sc7280 soc. + +Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> +Signed-off-by: Manish Pandey <quic_mapa@quicinc.com> +Signed-off-by: Salendarsingh Gaud <quic_sgaud@quicinc.com> +Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com> +Upstream-Status: Submitted [https://lore.kernel.org/all/20230929131936.29421-3-quic_nitirawa@quicinc.com/] +--- + arch/arm64/boot/dts/qcom/sc7280.dtsi | 66 ++++++++++++++++++++++++++++ + 1 file changed, 66 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi +index 042908048d09..19705df517dd 100644 +--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi ++++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi +@@ -3321,6 +3321,72 @@ opp-202000000 { + }; + }; + ++ ufs_mem_hc: ufs@1d84000 { ++ compatible = "qcom,sc7280-ufshc", "qcom,ufshc", ++ "jedec,ufs-2.0"; ++ reg = <0x0 0x01d84000 0x0 0x3000>; ++ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; ++ phys = <&ufs_mem_phy>; ++ phy-names = "ufsphy"; ++ lanes-per-direction = <2>; ++ #reset-cells = <1>; ++ resets = <&gcc GCC_UFS_PHY_BCR>; ++ reset-names = "rst"; ++ ++ power-domains = <&gcc GCC_UFS_PHY_GDSC>; ++ required-opps = <&rpmhpd_opp_nom>; ++ ++ iommus = <&apps_smmu 0x80 0x0>; ++ dma-coherent; ++ ++ interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, ++ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_UFS_MEM_CFG 0>; ++ ++ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, ++ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, ++ <&gcc GCC_UFS_PHY_AHB_CLK>, ++ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, ++ <&rpmhcc RPMH_CXO_CLK>, ++ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, ++ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, ++ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; ++ clock-names = "core_clk", ++ "bus_aggr_clk", ++ "iface_clk", ++ "core_clk_unipro", ++ "ref_clk", ++ "tx_lane0_sync_clk", ++ "rx_lane0_sync_clk", ++ "rx_lane1_sync_clk"; ++ freq-table-hz = ++ <75000000 300000000>, ++ <0 0>, ++ <0 0>, ++ <75000000 300000000>, ++ <0 0>, ++ <0 0>, ++ <0 0>, ++ <0 0>; ++ status = "disabled"; ++ }; ++ ++ ufs_mem_phy: phy@1d87000 { ++ compatible = "qcom,sc7280-qmp-ufs-phy"; ++ reg = <0x0 0x01d87000 0x0 0xe00>; ++ clocks = <&rpmhcc RPMH_CXO_CLK>, ++ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, ++ <&gcc GCC_UFS_1_CLKREF_EN>; ++ clock-names = "ref", "ref_aux", "qref"; ++ ++ resets = <&ufs_mem_hc 0>; ++ reset-names = "ufsphy"; ++ ++ #clock-cells = <1>; ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; ++ + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sc7280-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; +-- +2.25.1 + |