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From e0d8f3c34e54b7f7563360131e89be0d9405d436 Mon Sep 17 00:00:00 2001
From: Chunming Zhou <david1.zhou@amd.com>
Date: Tue, 21 Jul 2015 17:43:41 +0800
Subject: [PATCH 0393/1050] drm/amdgpu: add sched isr to fence process
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index be43ae4..1580d8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -346,8 +346,24 @@ void amdgpu_fence_process(struct amdgpu_ring *ring)
}
} while (atomic64_xchg(&ring->fence_drv.last_seq, seq) > seq);
- if (wake)
+ if (wake) {
+ if (amdgpu_enable_scheduler) {
+ uint64_t handled_seq =
+ amd_sched_get_handled_seq(ring->scheduler);
+ uint64_t latest_seq =
+ atomic64_read(&ring->fence_drv.last_seq);
+ if (handled_seq == latest_seq) {
+ DRM_ERROR("ring %d, EOP without seq update (lastest_seq=%llu)\n",
+ ring->idx, latest_seq);
+ return;
+ }
+ do {
+ amd_sched_isr(ring->scheduler);
+ } while (amd_sched_get_handled_seq(ring->scheduler) < latest_seq);
+ }
+
wake_up_all(&ring->adev->fence_queue);
+ }
}
/**
--
1.9.1
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