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From a20e66cd94137e196ae5ef627b8d71d5bc6a52ed Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Thu, 16 Apr 2015 20:40:31 +0200
Subject: [PATCH 05/29] radeonsi: set an optimal value for
DB_Z_INFO_ZRANGE_PRECISION
Required because of a VI hw bug.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
---
src/gallium/drivers/radeonsi/si_state.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index f24cbbd..dc19d29 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1948,12 +1948,6 @@ static void si_init_depth_surface(struct si_context *sctx,
z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
S_028040_ALLOW_EXPCLEAR(1);
- /* This is optimal for the clear value of 1.0 and using
- * the LESS and LEQUAL test functions. Set this to 0
- * for the opposite case. This can only be changed when
- * clearing. */
- z_info |= S_028040_ZRANGE_PRECISION(1);
-
/* Use all of the htile_buffer for depth, because we don't
* use HTILE for stencil because of FAST_STENCIL_DISABLE. */
s_info |= S_028044_TILE_STENCIL_DISABLE(1);
@@ -2183,7 +2177,8 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
- radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
+ radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
+ S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
--
1.9.1
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