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From 583c9f7ae716367cb1e623dfa492146a8ccf7bc2 Mon Sep 17 00:00:00 2001
From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Date: Wed, 17 Jul 2019 18:33:48 -0400
Subject: [PATCH 3420/4256] drm/amd/display: Update DML parameters
[Why]
Need to add DML struct members that were omitted in previous
DML implemenations.
[How]
- Add missing enum values
- Add missing struct members
- Set new input values in the fetch functions
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
.../amd/display/dc/dml/display_mode_enums.h | 22 ++++++++++++++-----
.../amd/display/dc/dml/display_mode_structs.h | 3 +++
.../drm/amd/display/dc/dml/display_mode_vba.c | 9 ++++++++
.../drm/amd/display/dc/dml/display_mode_vba.h | 18 +++++++++++++++
4 files changed, 46 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index 0c2fab1e93b6..1c97083b8d0b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -37,11 +37,14 @@ enum source_format_class {
dm_444_64 = 2,
dm_420_8 = 3,
dm_420_10 = 4,
- dm_422_8 = 5,
- dm_422_10 = 6,
- dm_444_8 = 7,
+ dm_420_12 = 5,
+ dm_422_8 = 6,
+ dm_422_10 = 7,
+ dm_444_8 = 8,
dm_mono_8 = dm_444_8,
- dm_mono_16 = dm_444_16
+ dm_mono_16 = dm_444_16,
+ dm_rgbe = 9,
+ dm_rgbe_alpha = 10,
};
enum output_bpc_class {
dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
@@ -83,7 +86,7 @@ enum dm_swizzle_mode {
dm_sw_var_d_x = 30,
dm_sw_64kb_r_x,
dm_sw_gfx7_2d_thin_lvp,
- dm_sw_gfx7_2d_thin_gl
+ dm_sw_gfx7_2d_thin_gl,
};
enum lb_depth {
dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
@@ -112,7 +115,8 @@ enum output_standard {
enum mpc_combine_affinity {
dm_mpc_always_when_possible,
dm_mpc_reduce_voltage,
- dm_mpc_reduce_voltage_and_clocks
+ dm_mpc_reduce_voltage_and_clocks,
+ dm_mpc_never
};
enum self_refresh_affinity {
@@ -157,4 +161,10 @@ enum writeback_config {
dm_whole_buffer_for_single_stream_interleave,
};
+enum odm_combine_mode {
+ dm_odm_combine_mode_disabled,
+ dm_odm_combine_mode_2to1,
+ dm_odm_combine_mode_4to1,
+};
+
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index ab34fd26702f..f4c1ef9046bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -109,6 +109,9 @@ struct _vcs_dpi_soc_bounding_box_st {
int use_urgent_burst_bw;
unsigned int num_states;
struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES];
+ bool do_urgent_latency_adjustment;
+ double urgent_latency_adjustment_fabric_clock_component_us;
+ double urgent_latency_adjustment_fabric_clock_reference_mhz;
};
struct _vcs_dpi_ip_params_st {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 88e63f16f7fc..bd634dce6f3a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -262,6 +262,13 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
//mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mhz;
mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz;
}
+
+ mode_lib->vba.DoUrgentLatencyAdjustment =
+ soc->do_urgent_latency_adjustment;
+ mode_lib->vba.UrgentLatencyAdjustmentFabricClockComponent =
+ soc->urgent_latency_adjustment_fabric_clock_component_us;
+ mode_lib->vba.UrgentLatencyAdjustmentFabricClockReference =
+ soc->urgent_latency_adjustment_fabric_clock_reference_mhz;
}
static void fetch_ip_params(struct display_mode_lib *mode_lib)
@@ -385,8 +392,10 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
src->viewport_y_c;
mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch;
mode_lib->vba.SurfaceHeightY[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height;
+ mode_lib->vba.SurfaceWidthY[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width;
mode_lib->vba.PitchC[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch_c;
mode_lib->vba.SurfaceHeightC[mode_lib->vba.NumberOfActivePlanes] = src->viewport_height_c;
+ mode_lib->vba.SurfaceWidthC[mode_lib->vba.NumberOfActivePlanes] = src->viewport_width_c;
mode_lib->vba.DCCMetaPitchY[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch;
mode_lib->vba.DCCMetaPitchC[mode_lib->vba.NumberOfActivePlanes] = src->meta_pitch_c;
mode_lib->vba.HRatio[mode_lib->vba.NumberOfActivePlanes] = scl->hscl_ratio;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 0347f74cda3a..52d2583b2f74 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -290,6 +290,7 @@ struct vba_vars_st {
double PixelClock[DC__NUM_DPP__MAX];
double PixelClockBackEnd[DC__NUM_DPP__MAX];
bool DCCEnable[DC__NUM_DPP__MAX];
+ bool FECEnable[DC__NUM_DPP__MAX];
unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
@@ -317,6 +318,7 @@ struct vba_vars_st {
double DCCRate[DC__NUM_DPP__MAX];
double AverageDCCCompressionRate;
bool ODMCombineEnabled[DC__NUM_DPP__MAX];
+ enum odm_combine_mode ODMCombineTypeEnabled[DC__NUM_DPP__MAX];
double OutputBpp[DC__NUM_DPP__MAX];
bool DSCEnabled[DC__NUM_DPP__MAX];
unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
@@ -395,6 +397,7 @@ struct vba_vars_st {
double FabricClockPerState[DC__VOLTAGE_STATES + 1];
double SOCCLKPerState[DC__VOLTAGE_STATES + 1];
double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
+ double DTBCLKPerState[DC__VOLTAGE_STATES + 1];
double MaxDppclk[DC__VOLTAGE_STATES + 1];
double MaxDSCCLK[DC__VOLTAGE_STATES + 1];
double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1];
@@ -488,6 +491,7 @@ struct vba_vars_st {
unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
int NoOfDPPThisState[DC__NUM_DPP__MAX];
bool ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
+ bool ODMCombineTypeEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
unsigned int SwathWidthYThisState[DC__NUM_DPP__MAX];
unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
@@ -513,6 +517,7 @@ struct vba_vars_st {
bool DIOSupport[DC__VOLTAGE_STATES + 1];
bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1];
bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
+ bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1];
bool ROBSupport[DC__VOLTAGE_STATES + 1];
bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1][2];
@@ -605,6 +610,7 @@ struct vba_vars_st {
double MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
double MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
bool odm_combine_dummy[DC__NUM_DPP__MAX];
+ enum odm_combine_mode odm_combine_mode_dummy[DC__NUM_DPP__MAX];
double dummy1[DC__NUM_DPP__MAX];
double dummy2[DC__NUM_DPP__MAX];
double dummy3[DC__NUM_DPP__MAX];
@@ -625,6 +631,11 @@ struct vba_vars_st {
unsigned int dummyinteger10;
unsigned int dummyinteger11;
unsigned int dummyinteger12;
+ unsigned int dummyintegerarr1[DC__NUM_DPP__MAX];
+ unsigned int dummyintegerarr2[DC__NUM_DPP__MAX];
+ unsigned int dummyintegerarr3[DC__NUM_DPP__MAX];
+ unsigned int dummyintegerarr4[DC__NUM_DPP__MAX];
+ long dummylongarr1[DC__NUM_DPP__MAX];
bool dummysinglestring;
bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
double PlaneRequiredDISPCLKWithODMCombine2To1;
@@ -633,6 +644,7 @@ struct vba_vars_st {
bool LinkDSCEnable;
bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES + 1];
bool ODMCombineEnableThisState[DC__NUM_DPP__MAX];
+ enum odm_combine_mode ODMCombineEnableTypeThisState[DC__NUM_DPP__MAX];
unsigned int SwathWidthCThisState[DC__NUM_DPP__MAX];
bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
@@ -641,6 +653,7 @@ struct vba_vars_st {
unsigned int NotEnoughUrgentLatencyHiding;
unsigned int NotEnoughUrgentLatencyHidingPre;
long PTEBufferSizeInRequestsForLuma;
+ long PTEBufferSizeInRequestsForChroma;
// Missing from VBA
long dpte_group_bytes_chroma;
@@ -787,6 +800,9 @@ struct vba_vars_st {
unsigned int PDEProcessingBufIn64KBReqs;
double MaxTotalVActiveRDBandwidth;
+ bool DoUrgentLatencyAdjustment;
+ double UrgentLatencyAdjustmentFabricClockComponent;
+ double UrgentLatencyAdjustmentFabricClockReference;
double MinUrgentLatencySupportUs;
double MinFullDETBufferingTime;
double AverageReadBandwidthGBytePerSecond;
@@ -801,6 +817,8 @@ struct vba_vars_st {
bool ModeIsSupported;
bool ODMCombine4To1Supported;
+ unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
+ unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
--
2.17.1
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