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From aa07dc450ffff6826e4877f410143ebcd01f6e0e Mon Sep 17 00:00:00 2001
From: Nikola Cornij <nikola.cornij@amd.com>
Date: Wed, 19 Jun 2019 14:30:52 -0400
Subject: [PATCH 3046/4256] drm/amd/display: Power-gate all DSCs at driver init
time
[why]
DSC should be powered-on only on as-needed basis, i.e. if the mode
requires it
[how]
Loop over all the DSCs at driver init time and power-gate each
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index db57c2a99a15..b753e40c4196 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -599,6 +599,12 @@ static void dcn20_init_hw(struct dc *dc)
}
}
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ /* Power gate DSCs */
+ for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+ dcn20_dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+#endif
+
/* Blank pixel data with OPP DPG */
for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
struct timing_generator *tg = dc->res_pool->timing_generators[i];
--
2.17.1
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