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From 19957c34d58af28e207fb4f3fb6c7877120b7a35 Mon Sep 17 00:00:00 2001
From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Date: Tue, 9 Apr 2019 11:50:38 -0400
Subject: [PATCH 2513/2940] drm/amd/display: Fix ODM combine data format
[Why]
OPTC data format was left at its default value (444) when enabling
ODM combine. This caused issues with FPGA capture.
[How]
Write the OPTC_DATA_FORMAT field when enabling ODM combine.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ++++--
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 11 ++++++++++-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 4 +++-
.../gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 3 ++-
5 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index cd9b662fbea9..02599eb92ca6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -463,6 +463,7 @@ struct dcn_optc_registers {
type OPTC_SEG0_SRC_SEL;\
type OPTC_SEG1_SRC_SEL;\
type OPTC_MEM_SEL;\
+ type OPTC_DATA_FORMAT;\
type OPTC_DSC_MODE;\
type OPTC_DSC_BYTES_PER_PIXEL;\
type OPTC_DSC_SLICE_WIDTH;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fbcb4d860e7a..2ea72e965c1b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -703,7 +703,8 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->stream_res.tg->funcs->set_odm_combine(
pipe_ctx->stream_res.tg,
odm_pipe->stream_res.opp->inst,
- pipe_ctx->stream->timing.h_addressable/2);
+ pipe_ctx->stream->timing.h_addressable/2,
+ pipe_ctx->stream->timing.pixel_encoding);
/* HW program guide assume display already disable
* by unplug sequence. OTG assume stop.
*/
@@ -1007,7 +1008,8 @@ static void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pip
pipe_ctx->stream_res.tg->funcs->set_odm_combine(
pipe_ctx->stream_res.tg,
combine_pipe->stream_res.opp->inst,
- pipe_ctx->plane_res.scl_data.h_active);
+ pipe_ctx->plane_res.scl_data.h_active,
+ pipe_ctx->stream->timing.pixel_encoding);
else
pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index ea6a19063b22..d0b317ea3a7c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -238,11 +238,13 @@ void optc2_set_odm_bypass(struct timing_generator *optc,
OPTC_MEM_SEL, 0);
}
-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, int mpcc_hactive)
+void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
+ int mpcc_hactive, enum dc_pixel_encoding pixel_encoding)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
/* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192 */
int memory_mask = mpcc_hactive <= 2560 ? 0x3 : 0xf;
+ uint32_t data_fmt = 0;
/* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
* REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
@@ -255,6 +257,13 @@ void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, in
REG_SET(OPTC_MEMORY_CONFIG, 0,
OPTC_MEM_SEL, memory_mask << (optc->inst * 4));
+ if (pixel_encoding == PIXEL_ENCODING_YCBCR422)
+ data_fmt = 1;
+ else if (pixel_encoding == PIXEL_ENCODING_YCBCR420)
+ data_fmt = 2;
+
+ REG_SET(OPTC_DATA_FORMAT_CONTROL, 0, OPTC_DATA_FORMAT, data_fmt);
+
REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
OPTC_NUM_OF_INPUT_SEGMENT, 1,
OPTC_SEG0_SRC_SEL, optc->inst,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index a21781332a06..ebf07c582da2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -66,6 +66,7 @@
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+ SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
@@ -95,7 +96,8 @@ void optc2_set_dsc_config(struct timing_generator *optc,
void optc2_set_odm_bypass(struct timing_generator *optc,
const struct dc_crtc_timing *dc_crtc_timing);
-void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id, int mpcc_hactive);
+void optc2_set_odm_combine(struct timing_generator *optc, int combine_opp_id,
+ int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
void optc2_get_optc_source(struct timing_generator *optc,
uint32_t *num_of_src_opp,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 2dee10f7f1fe..5e93bc0e8ff9 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -268,7 +268,8 @@ struct timing_generator_funcs {
uint32_t dsc_slice_width);
#endif
void (*set_odm_bypass)(struct timing_generator *tg, const struct dc_crtc_timing *dc_crtc_timing);
- void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id, int mpcc_hactive);
+ void (*set_odm_combine)(struct timing_generator *tg, int combine_opp_id,
+ int mpcc_hactive, enum dc_pixel_encoding pixel_encoding);
void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
void (*set_gsl_source_select)(struct timing_generator *optc,
int group_idx,
--
2.17.1
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